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Cottagers best ever XI: Who is Fulham’s best goalkeeper?
In a new series to take us back to domestic football, we look at Fulham's best XI, starting with the goalkeeper position. Let us know in the comments who you think is the winner?
Trane inks business, marketing partnership with Bank of America Stadium
Trane Technologies is deepening its ties to Bank of America Stadium as a cornerstone partner that will lead HVAC upgrades as part of the $1.3 billion upgrade of the downtown Charlotte venue. The agreement will put Trane’s name on the stadium’s 300-level Silver Club section, starting in 2029, Tepper Sports & Entertainment said in a […]
Department of Health: Segregated rate revision to change how redemption centers pay for recycled bottles and cans
Hawaiʻi’s Deposit Beverage Container Program will change how redemption centers convert container weight into container counts starting Oct. 1, the state Department of Health announced.
The Grand Theft Auto VI Digital Issue Is Now Live
Subscribers can read the digital version of our latest magazine starting today. - Game Informer
It’s all up to Michael Penix Jr. now
The talented young quarterback is healthy and has his opportunity to lock up Atlanta’s starting job for the long haul.
A popular GLP-1 provider just made its weight loss medications cheaper
Mochi Health has lower starting prices for compounded semaglutide and tirzepatide, plus a new lab testing service designed to help patients monitor their health.
New campaign disclosures reveal how much American political campaigns spend on AI tools
Though politicians are quiet about how they use AI, the book Rewiring Democracy examines how AI is starting to influence American politics
Confusion and Angst Follow State's Early Rollout of Medicaid Work Rules
In most states, people with Medicaid coverage will have to prove they’re working, volunteering, or studying starting Jan. 1. But Montana put the rules into effect early, and they’re sowing uncertainty and anxiety.
Leaked: Roma’s possible third Centenary kit
Roma’s centenary is also starting to take shape through the jerseys. FootyHeadlines has published the first previews of the third kit the club is expected to wear in the 2027-2028 season, the centen...
Case Keenum Shines as Bears Dominate Eagles in Statement Win!
The Chicago Bears delivered one of their biggest performances of the young season Monday night, taking down the Philadelphia Eagles 27-7 at Soldier Field. With starting quarterback Caleb Williams sidelined by a hamstring injury, Chicago turned to veteran Case Keenum, and the longtime NFL quarterback delivered when his team needed him most. Keenum threw for…
Rams could be without starting cornerback, tight end vs. Eagles
Jaylen Watson and Terrance Ferguson are likely to miss Sunday’s game against the Eagles, while the Rams remain hopeful Puka Nacua can return
Golden Knights Starting Over, but Fueled by ‘Unfinished Business’
A certain energy has crackled in the air at City National Arena throughout training camp and the preseason. There is a hunger, a sense of urgency that has nothing to do with the shortened preseason. And everyone in the Vegas Golden Knights organization, from the players to the head coach to the general manager, speaks of unfinished business.
Golden Knights Starting Over, but Fueled by ‘Unfinished Business’
A certain energy has crackled in the air at City National Arena throughout training camp and the preseason. There is a hunger, a sense of urgency that has nothing to do with the shortened preseason. And everyone in the Vegas Golden Knights organization, from the players to the head coach to the general manager, speaks of unfinished business.
Broadcast To Hit A Double, Peacock Going Deep In NBC Sports Coverage Of MLB Wild Card Playoffs
Sports fans of a certain age can readily recall NBC’s coverage of the Major League Baseball playoffs regularly pre-empting the network’s “Must-See TV” primetime lineup in the 1990s. While today’s ratings and programming landscape has changed dramatically in the intervening decades, this year’s playoffs (starting Tuesday) are shaping up as a back-to-the-future milestone for NBC …
Jameis Winston to remain starting QB
Giants QB Jameis Winston will remain starter even after J.J. McCarthy trade
TCL’s new ‘Designer’ Google TVs are just like Samsung’s The Frame, starting at $899
TCL has launched a new “Designer Series” of TV sets running Google TV with a flush mount design and matte...
Panthers could be down 2 key defensive backs vs. Lions
The Carolina Panthers could be missing both starting cornerbacks in their Sunday night game against the Detroit Lions.
The 3 most disappointing college football teams this season
A month into the 2026 college football season, the preseason polls are already starting to look like works of fiction. For every team exceeding expectations, there’s another whose fan base is wondering what went wrong, and in some cases, whether the head coach will make it to November. Nearly every team entered the 2026 season…
Pixel Buds app update lets Gemini control audio and settings
We’re now starting to see Gemini audio controls with the latest Pixel Buds companion app update. This is part of...
Houston Astros rebound from 11 games under .500 and win AL West
Houston will host the Chicago White Sox in a best-of-three Wild Card Series starting Tuesday.
Houston Astros rebound from 11 games under .500 and win AL West
Houston will host the Chicago White Sox in a best-of-three Wild Card Series starting Tuesday.
Kansas’ New-Look Roster Is Starting to Take Shape
Kansas’ New-Look Roster Is Starting to Take Shape
Google is officially killing Gemini Gems
The Gems manager in Gemini is now showing a banner officially announcing that Gems will be migrated to Skills starting November 17.
In brief: '9 to 5' headed back to theaters and more
Pour yourself a cup of ambition and head out to your local movie theater. 9 to 5 is headed back to movie theaters for a special, weeklong run starting on Oct. 9. This will be a newly restored version of the classic satirical workplace comedy starring the late Dolly Parton. Additionally, Disney is set to donate net proceeds from each ticket purchased for the rerelease in the U.S. to the Dollywood Foundation in support of its flagship program, Dolly Parton’s Imagination Library. Disney is the parent company of ABC News ...Off Campus star Ella Bright has found her next gig. The actress confirmed she will star opposite Mason Thames in the movie Narcs in a post shared to her Instagram Story. This marks Bright's first major studio feature role. The upcoming coming-of-age comedy will be made for Sony Pictures. While the movie's plot is being kept under wraps, it will serve as the directorial debut of John Phillips, the writer of No Hard Feelings, Good Boys and Dirty Grandpa ... TNCMS.AdManager.render({region: 'fixed-big-ad-top-asset', slot: 1, fold: "above"}); Did you miss Evil Dead Burn in theaters? Not to worry. The film is set to make its global streaming debut on HBO Max on Oct. 2. Souheila Yacoub, Tandi Wright, Hunter Doohan, Luciane Buchanan, Erroll Shand and Maude Davey star in the film that was directed by Sébastien Vaniček ...Copyright © 2026, ABC Audio. All rights reserved. Thank you for reading kmaland.comAt KMA, we attempt to be accurate in our reporting. If you see a typo or mistake in a story, please contact us by emailing kmaradio@kmaland.com.
What do the numbers tell us about Hogh's Celtic start?
It is fair to say Kasper Hogh has not had the start he or Celtic would have wanted after the club spent a club-record fee to sign the Denmark striker from Bodo/Glimt. Having bagged 53 goals in 102 appearances for his previous team, a handful of which came in the Champions League against top-level opposition, the 25-year-old arrived to fanfare following the signing of fellow big-money capture Camilo Duran. Now, with Martin O'Neill's men on a three-game losing run, serious questions are starting to be asked after Hogh's underwhelming introduction.
Brock Purdy Enters Intriguing Conversation After 49ers’ Week 3 Win
The San Francisco 49ers are off to a 3-0 start after beating the Arizona Cardinals in Week 3, 36-20, on Sept. 27 at Levi’s Stadium. Moreover, this start for the Niners has one analyst recognizing starting QB Brock Purdy as arguably one of the best players at his position. Purdy went 15-for-27 on his pass […] The post Brock Purdy Enters Intriguing Conversation After 49ers’ Week 3 Win appeared first on HEAVY.
Mariota stars as Commanders end Seahawks' winning run
Marcus Mariota threw three touchdown passes as the Washington Commanders claimed a 33-31 victory over Seattle to end the Seahawks' long winning streak. Seattle had won a dozen games in a row, following up last season's Super Bowl triumph by starting their campaign with back-to-back triumphs, but Mariota starred in the absence of the injured Jayden Daniels.
Mariota stars as Commanders end Seahawks' winning run
Marcus Mariota threw three touchdown passes as the Washington Commanders claimed a 33-31 victory over Seattle to end the Seahawks' long winning streak. Seattle had won a dozen games in a row, following up last season's Super Bowl triumph by starting their campaign with back-to-back triumphs, but Mariota starred in the absence of the injured Jayden Daniels.
Losing the Same Weight Didn’t Produce the Same Health Benefits
Among several diets tested in a clinical trial, a ketogenic diet produced the greatest improvements in liver and metabolic health. Losing the same amount of weight does not necessarily produce the same metabolic benefits. In a randomized clinical trial, three very different diets helped adults with obesity lose about 10% of their starting weight, but
Braelon Allen quiet in Week 3
Jets RB Braelon Allen not a big factor in Week 3 but may join starting line next week
Patriots bench Drake Maye after 3-turnover outing against Jaguars
The Patriots pulled their starting quarterback in the fourth quarter.
Giancarlo Stanton’s Yankees comeback could come without a starting job
Giancarlo Stanton took live at-bats again Friday. That’s good news for the Yankees, but it doesn’t mean he is about […]
Armani's business and creative evolution on show in Milan a year after founder's death
Giorgio Armani’s empire is taking shape a year after the designer’s death. His latest collection, previewed Sunday, showcases his signature elegance. Behind the scenes, discussions are starting...
Armani's business and creative evolution on show in Milan a year after founder's death
Giorgio Armani’s empire is taking shape a year after the designer’s death. His latest collection, previewed Sunday, showcases his signature elegance. Behind the scenes, discussions are starting...
Pedro Gabriel highlights confidence and intensity before three friendlies
Pedro Gabriel, left-back for the Brazil U-20 National TeamCredits: Nelson Terme/CBFThe Brazil U-20 National Team is wrapping up a week of intense work in Spain before starting a run of three friendlie...
Rafael Flores Jr. Has Earned the Pirates’ Starting Catcher Role
Many were critical of the Pittsburgh Pirates when they traded All-Star closer David Bednar to the New York Yankees at the 2025 trade deadline. Not only was Bednar a fan favorite, but a quality closer, and the return looked light compared to other relievers who were traded at the time. However, the headliner of the …
Fernando Alonso Says Car Is Improving Despite Starting in P19
The Spaniard suffers a lock-up in Q1 that leaves him nineteenth and he will start last due to engine penalties. He acknowledges that the AMR26 has improved in the corners but warns that the lack of top speed is an insurmountable burden in Azerbaijan.
Cavan Sullivan makes USMNT history with first start
By Ari LiljenwallCavan Sullivan's rapid rise has reached the international stage.The 16-year-old Philadelphia Union homegrown midfielder was named to Mauricio Pochettino's starting XI during Saturday'...
Clock Ticking on ‘Disastrous’ Baltimore Ravens Starter
Pressure mounting on "Disastrous" Baltimore Ravens starting offensive lineman. The post Clock Ticking on ‘Disastrous’ Baltimore Ravens Starter appeared first on HEAVY.
Presidents Cup 2026: Sunday singles matches, starting times
The 16th Presidents Cup will conclude with 12 singles match on Sunday at Medinah Country Club.
Phillies make stunning pitching announcement with season on the line
A veteran starting pitcher will take the ball on two days' rest in a surprise last-minute move.
This External GPU Uses Wi-Fi To Transform Any Device Into A Gaming Rig
The WiCi One is available for preorders starting at $1,999.
Just 4 Minutes a Day: The Surprising Habit Transforming Health After 65 - Futura-Sciences
Why Short Workouts Might Be a Big Deal Starting long or intense workout regimens puts off a lot of people—no surprise there. Yet, muscle strength and balance are crucial for maintaining independence as we age, and unfortunately, these abilities decline faster after age 65. With this in mind, researchers at...
Presidents Cup 2026: Day 3 foursomes matches, starting times
The U.S. and International teams will compete in four foursomes (alternate shot) matches Saturday afternoon at Medinah.
Detroit Tigers Reveal Lineup for Justin Verlander’s Final Start
The Detroit Tigers have revealed their starting lineup for Justin Verlander's final career start Saturday against the Pittsburgh Pirates.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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England projected starting lineup vs. Spain: Where will Bellingham play?
Svensson, Bellingham, Nwaneri and Bensebaini win for their countries
Daniel Svensson and the Swedish national team faced Romania in the UEFA Nations League. Svensson was not initially in the starting lineup, but came on in the 63rd minute with the score at 2-1 and help...
Jays Edge Reds 6-5
For most of the night, this looked like a typically frustrating 2026 Blue Jays loss. The starting pitching wasn’t very good, the bullpen did enough to keep them in range, and while the offence produce traffic on the bases it failed to turn that into runs. Luckily, things flipped late. The offence woke up and […]
Debate over James Rodríguez's starting spot intensifies
The recent clásico between Atlético Nacional and Millonarios sparked debate among fans about the role James Rodríguez should take on in the team.Gradual integration and technical contributionThe mi...
Trump promised to campaign in midterm battlegrounds. He's starting in deep red states instead
While organizers insist the rallies are in locations with media markets that span state lines and they will help bolster broader turnout, Trump's itinerary is yet another sign of the uphill fight that his party faces.
What to watch for when Arizona football visits Washington State
Though Arizona has already played a conference game, Saturday’s trip to Washington State feels like the end of the warmup portion of the 2026 season. Starting next week the rest of the opponents are in Big 12 play. The Wildcats (2-1) are seeking their fourth consecutive 3-1 start, which last happened during Rich Rodriguez’s first […]
Trump said he would campaign in midterm battlegrounds. He's starting in deep red states instead
President Donald Trump has vowed to campaign in 35 of the most competitive battleground districts in the final sprint to November’s midterm elections.
Bladen Small Business Center to host “Funding Toolbox” Small Business RoundTable
Small business owners and aspiring entrepreneurs are invited to attend the September Small Business RoundTable at Bladen Community College, featuring a practical discussion on one of the most important challenges facing entrepreneurs: finding the right funding for a business.The September RoundTable, “The Funding Toolbox,” will be held Monday, Sept.28, from 5:30–7 p.m. in Building 14, Room 135, at Bladen Community College.Sponsored by the Bladen Community College Small Business Center (SBC) and the Elizabethtown-White Lake Area Chamber of Commerce, the event will bring together experts familiar with the Small Business Center and SSBCI programs to help participants better understand the funding resources available to entrepreneurs and small businesses.Rather than focusing on one type of financing, “The Funding Toolbox” will explore a variety of funding tools and resources that may be available depending on a business's stage, needs and goals. Participants will have an opportunity to learn about available programs, how they work, what lenders and funding organizations look for, and how business owners can prepare to seek financing.Topics will include:Funding options for startups and existing businessesLoans and other financing resourcesSSBCI-supported funding opportunitiesHow to determine which funding option may fit your businessWhat lenders and funding organizations look forPreparing financial information and documentationResources available to help businesses become funding-ready“The Funding Toolbox” is designed for both aspiring entrepreneurs and established small business owners who are considering starting, expanding or investing in their businesses.The Small Business RoundTable provides an informal setting where local entrepreneurs can learn, ask questions, share experiences and connect with business-resource partners. The program is part of the ongoing efforts of the Bladen Community College Small Business Center and the Elizabethtown-White Lake Area Chamber of Commerce to strengthen and support small businesses throughout the community.The September RoundTable is free and open to the public.For more information or to register, contact the Bladen Community College Small Business Center at 910-879-5572.Event DetailsWhat: Small Business RoundTable – The Funding ToolboxWhen: Monday, Sept.28, 2026 | 5:30–7 p.m.Where: Bladen Community College, Building 14, Room 135Cost: FreeSponsors: Bladen Community College Small Business Center and Elizabethtown-White Lake Area Chamber of Commerce
From 650,000 players to the number one target
City's devotion to data is at the heart of their efforts to close the gap on Arsenal and BBC Sport has been given unprecedent access to the inner workings of the club's metrics machine as we uncover some of the secrets guiding their work - particularly regarding player recruitment and sales. The starting point for any new signing is City's database of 650,000 footballers from around the world.
Dodgers notes: Shohei Ohtani, Tyler Glasnow, first-round bye
Shohei Ohtani is back in the lineup and the Dodgers saved their best starting lineup for the final five games of the regular season. So far, the team has gone 2-18 with runners in scoring position while scoring just three runs over their two consecutive losses to the San Diego Padres. Ohtani was one of […]
Fewer relegations, fewer leagues: changes to the Nations League
The Nations League is set for a small revolution starting with the 2028/29 edition.While the competition currently operates with four leagues, League D will disappear. To ensure the transition, UEFA h...
QB Bryce Young starting to flourish, put up big numbers in Panthers offense
His 648 passing yards are second only to New Orleans' Tyler Shough. The Panthers are finally looking like a formidable offense for the first time since the Cam Newton era.
See Qantas' new business class seats for world's longest flights
Qantas' "Project Sunrise" planes will fly up to 22 hours nonstop between New York and London and Australia starting in 2027.
Virginia health committee considers mandating licensed nurses in every school
Virginia schools could be required to have a licensed nurse in every building starting in 2028, under a legislative proposal introduced Wednesday. The measure is designed to close healthcare gaps by placing experts in schools to manage complex medical conditions. Virginia permits school divisions to employ nurses, but state law doesn’t require it. About 8% […]
Ter Stegen hails “unstoppable” Barcelona under Hansi Flick
Marc-André ter Stegen has found regular playing time at Ajax during his loan spell from Barcelona, earning his way back into the starting XI for the German national team.The 34-year-old has been keep...
‘Worth the wait’: Social science faculty members describe move to newly renovated 2001 Sheridan Road
For decades, much of Northwestern’s anthropology department had been working out of a two-story house at 1810 Hinman Ave., an Evanston landmark which has faced maintenance issues and is nearly as old as the university. But starting in the 2026-27 academic year, anthropology is one of multiple social science departments moving into one of the...
Germany vs. Greece preview: Team news and predicted lineups
Germany came painfully close to starting the Jürgen Klopp era with a win in Amsterdam on Thursday night, but ultimately had to settle for a 1-1 draw against the Netherlands after Cody Gakpo scored a ...
New Pokemon TCG Premium Binders to Release Featuring Numbered...
Starting October 16th, Japan's Pokemon Centers will release a collection of nine Pokemon TCG binders themed after each generation -- with numbered card
Who on Earth Could Start Game 162 for the Astros?
There are three games remaining in the 2026 regular season, and somehow the Astros control their own destiny in the American League West. The Astros have won two of three games this week despite not having a starting pitcher complete three innings. Hunter Brown will start Friday’s game in West Sacramento, with Hayden Wesneski likely […]
Sharpe Predicted To Be Nets’ Most Efficient Player
Day'Ron Sharpe transitions into a starting role, prepared to anchor Brooklyn’s interior and expand his offensive range.
Norvell Blinded by QB Loyalty Ahead of Central Arkansas Game
Florida State coach continues to praise his starting quarterback, Ashton Daniels, even after throwing three interceptions in a 50-36 loss to Alabama last Saturday. Norvell praises his confidence and decision-making skills. Daniels has thrown three touchdown passes against ranked teams this season.
JJ Redick addresses Lakers starting lineup then drops viral quote
Who will join Luka Doncic, Austin Reaves and Walker Kessler in the Lakers starting lineup this season?
White Sox Move Detrimental Pitcher to Injured List
Luis Castillo struggled in both the starting rotation and bullpen, and the White Sox finally have an opportunity to move forward without him.
Rockies Finish Up at Home With Loss to Diamondbacks
Colorado Rockies starting pitcher Tanner Gordon was not sharp early on Thursday, helping the Arizona Diamondbacks get a victory at Coors Field.
Off-Day Open Thread
It is the last off-day of the regular season, before the series with the Reds. I forgot that today was an off-day. I went to see what time tonight’s game was starting and whoops there isn’t a tonight’s game. And there isn’t much for Jays news. Everything is about Vlad’s interview, and I think I […]
New York Giants starting quarterbacks since 2019 season
The New York Giants quarterback carousel continues as Jameis Winston steps in following Jaxson Dart's injury.
Avalanche chief joins Massive Entertainment as managing director
Francis will step into the role starting October 1st folloing Thomas Andren's recent appoint as general manager for the creative network.
Google rolling out blood pressure & insulin resistance, more on Pixel Watch 3, 4, 5
As previewed during last month’s Pixel Watch 5 launch, Google is now starting to roll out blood pressure trends, insulin resistance trends...
Macklemore announces concerts benefiting Palestinian aid organizations
Macklemore has announced a series of live performances called “Free Palestine,” with all proceeds going to Palestinian aid organizations. The tour kicks off in Europe next month, starting in Dublin
'I loved it' - Robertson grateful for United spell
Before the Champions League and Premier League titles, Scotland captaincy and Liverpool hero status, Andy Robertson was a skinny teenager starting his professional career at Tannadice. Dundee United plucked the then 19-year-old left-back from fourth-tier Queen's Park in June 2013 and paid him a few hundred quid a week. Within months he had earned a first Scotland call-up and by the end of the season he was off to Premier League Hull.
Frugal Fannie’s in Westwood is closing after 43 years in business
The longtime discount clothing store is holding a going-out-of-business sale starting Thursday. A final closing date is not set.
The Best Brighton XI of the last 11 seasons
A recent social media trend has seen fans pick out one player from each of the last eleven seasons to build an ultimate starting lineup for their club. Today we attempt this trend for Brighton and Hove Albion.
Lemonade the Rare Way: Harford County father turns life's lemons into a small business
Matthew Bartee of Lemonade the Rare Way uses fresh fruit and organic cane sugar to craft flavors he's been perfecting for more than a decade. Jumpstarting a small family business after being laid off.
Can Marcus Mariota Keep Washington Commanders' Offense on Track?
Jayden Daniels’ injury leaves Marcus Mariota with more than a starting job. He inherits an offense missing its biggest rushing threat, dealing with injuries along the offensive line and searching for more production from its WR1. Through it all, Mariota must keep Washington’s offense moving.
Analysis | One Republican could hold back the party’s candidates in Pennsylvania. And it’s not Trump.
Pennsylvania Republicans are starting to worry that the state’s lopsided race for governor is directly affecting four of the nation’s most competitive House races.
Commentary: Ohio is the nation’s No. 1 for business. Our challenge is to become No. 1 for students.
If Ohio wants to remain the best place for starting and growing a business, it also needs to become the best place for every student to learn, prepare for a career, and build a successful life.
Cubs’ Kevin Gausman Departs With Potential Injury: Latest Updates
The magic number for the Chicago Cubs to punch their ticket to the MLB postseason is one, but they’re certainly hoping right now that they’re not dealing with an injury to one of their most important players. During Wednesday evening’s contest at Wrigley Field against the Miami Marlins, starting pitcher Kevin Gausman dove to make […] The post Cubs’ Kevin Gausman Departs With Potential Injury: Latest Updates appeared first on HEAVY.
Dodgers on Deck: Thursday, September 24 vs. Padres
The Dodgers and San Diego Padres finish off their season series on Thursday, which is the Dodgers’ final home game of the 2026 regular season. Tyler Glasnow takes the ball for Los Angeles, with Nick Pivetta starting for San Diego. Both have battled injuries this season, with Thursday the 13th start for Glasnow and just […]
Microsoft unveils new Surface Pro 12-inch and Surface Laptop 13-inch with Snapdragon X2 Plus, brighter screens, and 5G options
The company is launching its new "entry premium" Surface Pro and Surface Laptop, both starting at over $1,000.
Serious business resumes for Wales boss Bellamy
With the Burnley interest firmly behind him, Craig Bellamy is focused on leading Wales in the Nations League, starting against Portugal in Lisbon.
English wonderkid is coming to replace Florian Wirtz
An exciting wonderkid is coming to oust Florian Wirtz from Liverpool's starting line-up. The Reds have invested a lot of money in the German working out at Anfield. Wirtz arrived as the solution to Li...
Mancini’s first Italy side takes shape for Belgium test
Roberto Mancini’s starting XI for Italy’s Nations League opener against Belgium is taking shape, with Francesco Pio Esposito, Nicolò Zaniolo and Daniel Maldini expected upfront.It kicks off at th...
OpenAI just upgraded ChatGPT Voice in three ways
Talking to ChatGPT is getting better in three ways starting today. OpenAI is rolling out a collection of improvements to...
Ravens Insider Delivers Final Verdict on Surprising Lamar Jackson Trend
The Baltimore Ravens are off to a mixed start to the 2026 season, but their starting quarterback, Lamar Jackson, has done plenty of good.Jackson has been throwing the ball more than the Ravens have seen from him in the past, and it seems to be working. When the running game struggled in their Week 2 […] The post Ravens Insider Delivers Final Verdict on Surprising Lamar Jackson Trend appeared first on HEAVY.
Presidents Cup 2026: Thursday's fourball matchups, starting times at Medinah
The first session features five fourball matches, the first of which tees off at 12:35 p.m. ET.
Why starting 3-0 matters for the 49ers
History shows that it’s way for the 49ers to fast track themselves to the playoffs
Codie Sanchez Doesn't Want to Compete With Sam Altman. She Says Founders Should Buy a Business Instead
Codie Sanchez argues that buying a proven small business can offer better odds, existing demand, and greater control than starting one from scratch.
Week 3 fantasy defense rankings: Top D/ST streamers, starts
With starting quarterback Jayden Daniels sidelined in Washington, the Seattle Seahawks are perched atop this week's fantasy defense rankings.
What would nearly brand new Scotland XI look like?
Eight of the Scotland squad are uncapped so what would the least experienced XI look like? And who would you pick for your starting line-up?
Shohei Ohtani expected to be activated on Wednesday
Ohtani has missed the last 13 games due to multiple injuries, spot in starting lineup remains undecided.
The Peninsula is getting a new dining option, with a taste of Tuscany
Starting early next year, The Lobby — a fifth-floor spot that serves breakfast, lunch and afternoon tea — will transform each evening into Italian restaurant Comunità.
Latest Kyrie Irving Trade News Could Be Great For Lakers
The NBA future of Kyrie Irving could see a big trade coming in his future. A new report confirms the Dallas Mavericks expecting to start the season with Irving as the starting point guard. Most teams around the league forecast him to get traded in the near future. Cooper Flagg becoming the face of the […] The post Latest Kyrie Irving Trade News Could Be Great For Lakers appeared first on HEAVY.
Health unit launches new healthcare services
First District announces flu clinics First District Health Unit will be offering three weeks of flu clinics in Minot in October, starting Monday, Oct. 5. During the first week, the first 50 people each day will receive a special gift. In addition, everyone who gets a flu shot during the three weeks will be entered […]