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Austin Transit Partnership reviews light rail design as business stresses about relocation

Austin’s long-debated light rail project moved into another phase as the Austin Transit Partnership met to discuss design and preconstruction work, while some b

Jun 17 • 6:48 PM EDT • Business • cbsaustin.com

iPhone Air With Dual Lens Camera Coming in Spring 2027

Apple is working on a new iPhone Air that's expected to launch in spring 2027, reports Bloomberg. The updated iPhone Air could get an Ultra Wide lens in addition to the Wide lens to make it a better value for the money. An iPhone Air with two camera lenses has reached the advanced testing phase. The device has the same design as the current model with the exception of the extra lens.

Jun 17 • 4:18 PM EDT • Technology • macrumors.com

Fortescue and IUCN chart a science-based path to net positive impact for biodiversity

Gland, Switzerland — IUCN and Fortescue have published findings from the first phase of their strategic collaboration, showing how science-based tools can guide a mining company’s journey toward net positive impact on biodiversity and Nature Positive contributions. The work, carried out at the Eliwana iron ore mine in Western Australia’s Pilbara region, demonstrates what rigorous, credible biodiversity action looks like in practice.

Jun 17 • 4:25 AM EDT • Science • iucn.org

Highest possible ambition: science-aligned fossil fuel phase-out…

This brief presents some timelines on what transitioning away from fossil fuels could look like at both the global and national level, building on the Highest Possible Ambition scenario released last year by Climate Analytics and PIK. Focusing on fossil fuel demand, this brief provides data on the…

Jun 16 • 10:02 AM EDT • Science • climateanalytics.org

Ukraine's new drones give it strike capabilities that HIMARS couldn't

The Ukrainian mid-range strike drone is "heralding a new phase of the war" for Ukraine, George Barros of the ISW told Business Insider.

Jun 16 • 12:30 AM EDT • Business • businessinsider.com

Atom Computing and Phasecraft Partner on Material Science Algorithms

Neutral-atom quantum hardware developer Atom Computing and quantum software specialist Phasecraft have signed a Memorandum of Understanding to collaborate on application-focused algorithms. The partnership aims to adapt Phasecraft’s hardware-optimized software to

Jun 15 • 7:51 PM EDT • Science • quantumcomputingreport.com

HMNC Brain Health announces $50 million first closing of Series B financing and a strategic partnership with MEDICE

Financing will accelerate the development of HMNC’s neurosciences portfolio, including Phase 3-readiness activities for Ketabon (KET01) and Nelivabon (BH-200)Agreement grants MEDICE exclusive European commercialization rights for KET01, with tiered double-digit royalties and significant milestone payments MUNICH, Germany, June 15, 2026 – HMNC Brain Health ("HMNC" or the "Company"), a clinical-stage neuroscience company, today announced the successful $50 million first closing of its Series B fin

Jun 15 • 7:00 AM EDT • Health • finance.yahoo.com

Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?

Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.

Jun 14 • 3:14 PM EDT • Technology • newsletter.semianalysis.com

"Scammers have adapted": Valve confirms that physical Steam Gift Cards are dead. Once the current stocks are sold through, they're done.

Valve's Steam Gift Cards have been a staple in major retailers throughout the world for quite some time. But today, the firm confirmed they're being phased out.

Jun 10 • 5:25 AM EDT • Technology • windowscentral.com

Seattle Parks and Recreation Hosts Racquet Sports Strategy Meetings

Seattle Parks and Recreation (SPR) is hosting a second round of public engagement meetings for the Outdoor Racquet Sports Strategy to present findings from the first phase of public engagement and to hear additional feedback from the public. This strategy was developed in response to growing popularity of both sports, as well as from feedback […]

Jun 9 • 12:27 PM EDT • Sports • parkways.seattle.gov

UCLA Women’s Basketball Adds Second Freshman to Roster

UCLA women’s basketball signed Slovenian freshman guard Lina Jerkovic for the 2026-27 season, the team announced on Sunday. Jerkovic is just the second incoming freshman to join the squad alongside Spanish guard Somto Okafor. UCLA is entering a rebuilding phase after winning the national championship last season. Part of that rebuild involved signing five players […] The post UCLA Women’s Basketball Adds Second Freshman to Roster appeared first on LA Sports Report.

Jun 7 • 3:23 PM EDT • Sports • sports.yahoo.com

First came Congress. Now a national redistricting battle may turn to statehouses and city councils

A national redistricting battle is about to enter a new phase

Jun 7 • 12:12 AM EDT • Politics • washingtonpost.com

First came Congress. Now a national redistricting battle may turn to statehouses and city councils

A national redistricting battle is about to enter a new phase.

Jun 7 • 12:06 AM EDT • Politics • news4jax.com

NOVUS vet: viral mitigation remains top priority for nursery pig health

NOVUS veterinarian Dr. Alex Hintz says producers are looking for viral mitigation tools for nursery pigs. Speaking to Brownfield at the World Pork Expo in Des Moines Wednesday, he said producers and vets understand a viral outbreak in the nursery phase can be devastating, and a robust management program is key.

Jun 5 • 1:10 PM EDT • Health • brownfieldagnews.com

Wellin5 Moves Toward Its Next Phase of Behavioral Health Acquisitions

Wellin5 is arguing for the harder version. The company is a hybrid behavioral health platform that has operated in the category for more than a decade and has served tens of thousands of patients through virtual therapy services.

Jun 3 • 3:32 PM EDT • Health • usatoday.com

Orlando Health unveils details of new hospital plans for Viera

Orlando Health will build a 240-bed hospital in Viera with an emergency department opening in the fall of 2027.

Jun 2 • 11:35 AM EDT • Health • floridatoday.com

Science and AI-enabled research platforms

In an Editorial, Vaughan C. Turekian, Executive Director of the Office of International Networks, Cooperation, and Security at the National Academies of Sciences, Engineering, and Medicine argues that science is entering a new phase. In an era of vast computational power, automated experiments, and AI, science will increasingly be built around integrated platforms that link data, models, computing, and instrumentation at scale.

Jun 2 • 8:00 AM EDT • Science • eurekalert.org

Jazz pre-draft process progressing this week

The next phase of the pre-draft process gets underway for the Utah Jazz this week. Now that the NBA combine is over and the deadline has passed for players to decide if they want to remain in the draft or return to college, it’s time for teams to take another step toward draft night. After the combine concluded, team officials and draft prospects remained in Chicago as team physicians and medical experts arrived.

May 31 • 6:15 PM EDT • Sports • sports.yahoo.com

Trump Hits the Stalemate Phase of His Interventions in Gaza, Ukraine and Now Iran

In Ukraine, Gaza and now Iran, President Trump’s early declarations of easy wins have given way to harsh reality.

May 31 • 4:07 PM EDT • Politics • nytimes.com

This strange new phase of matter could transform quantum technology

By stacking custom-designed silver nanoparticles like nanoscale LEGO bricks, scientists stabilized a mysterious crystal phase that had never been observed before. The material not only solves a longstanding puzzle in materials science but also exhibits promising quantum properties at room temperature.

May 29 • 8:00 PM EDT • Science • sciencedaily.com

Why the business of orbit is entering a new phase

Space is becoming a bigger part of everyday business, from communications and Earth observation to defense and predictive analytics. Voyager Technologies CEO Dylan Taylor and Muon Space President Gregory Smirin explain how cheaper launches, more satellite constellations and advances in AI are pushing the space economy into a new phase. Watch more from the CNBC CONVERGE LIVE conversation in Singapore to hear how the business of orbit is moving from exploration to infrastructure.

May 28 • 2:30 AM EDT • Business • cnbc.com

Inside Optum Health's push to make AI practical for clinicians

A phased rollout of AI-powered chart summarization is reducing administrative burdens while testing how healthcare organizations can responsibly scale artificial intelligence.

May 27 • 11:46 AM EDT • Health • healthcareitnews.com

Trump convenes rare Camp David Cabinet meeting as Iran deal pressure grows

President Trump convenes a rare Cabinet meeting at Camp David as high-stakes negotiations with Iran enter a critical phase amid a fraying ceasefire.

May 26 • 10:44 AM EDT • Politics • foxnews.com

Leading the shift in liquid dietary supplements through science and delivery

Uroš Gotar, Chief Innovation Officer at TOSLA, explains how scientific validation, flavour engineering, and liquid delivery are shaping the next phase of growth in nutraceuticals

May 26 • 5:17 AM EDT • Science • nutraceuticalbusinessreview.com

4 new pizzerias up the ante for neighborhood joints

Pittsburgh's pizza boom has entered a new phase. It’s marked by a continued upgrade in defining what modern-day neighborhood pizza joints ought to...

May 26 • 4:00 AM EDT • Technology • post-gazette.com

Jets OTAs are set to begin

The Jets will start the third and final phase of their offseason program this week. These are called organized team activities (OTAs). What is the offseason program? The NFL players and owners agreed to allow players to go to the team facility for a set number of workouts/practices over the course of the offseason. What […]

May 25 • 11:23 AM EDT • Sports • sports.yahoo.com

Fresno is one vote away from allowing alcohol consumption in ‘Entertainment Zones’

FRESNO, Calif. (KSEE/KGPE) – Change is brewing in Downtown Fresno. Fresno City Councilmembers voted Thursday to pass the first phase of an ordinance to allow people to drink alcoho…

May 23 • 2:07 AM EDT • Entertainment • yourcentralvalley.com

Santa Cruz | Seabright businesses brace for Murray Street Bridge closure

In early June, the Murray Street Bridge will completely close to allow the next phase of construction in a $50 million seismic retrofit project. The eastbound lane is set to reopen in mid-September. The looming closure has business owners…

May 22 • 7:24 PM EDT • Business • santacruzsentinel.com

Los Angeles Rams players participate in offseason workouts for Phase 2 of OTAs

Browse through photos capturing the best moments from this week's offseason workouts at the Los Angeles Rams' training facility.

May 22 • 1:05 PM EDT • Business • therams.com

Guest post: How CMIP7 will shape the next wave of climate science

Hundreds of scientists in dozens of institutions are embarking on the next phase of the world’s largest coordinated climate-modelling effort.

May 22 • 5:59 AM EDT • Science • carbonbrief.org

NASA’s AWE Completes Mission to Study Earth’s Effect on Space Weather

On May 21, ground controllers powered down NASA’s AWE (Atmospheric Waves Experiment) instrument, bringing the data collection phase of the mission to a

May 21 • 2:31 PM EDT • Science • science.nasa.gov

Scientists say this oral spray may finally cure your dog’s nasty breath

If you have a dog, you know the exact moment when the honeymoon phase is over. It often happens during a cosy morning cuddle when your furry best friend leans in for a sweet puppy kiss, and you’re hit with a wave of breath so foul it could strip paint.

May 21 • 8:16 AM EDT • Science • timesofindia.indiatimes.com

Providence Health Plan to end coverage, affecting hundreds of thousands of Oregon patients

PORTLAND, Ore. (KOIN) — Providence Health announced Wednesday they will be leaving the insurance business and starting to phase out coverage at the end of the year. The company says they will…

May 20 • 6:22 PM EDT • Health • koin.com

Valley Health Pea Ridge Medical Complex hosts open house

An open house was held on Wednesday at the Valley Health Pea Ridge Medical Complex.The complex has been open for several months and opened in multiple phases.Th

May 20 • 5:34 PM EDT • Health • wchstv.com

Chicago delays tipped wage phaseout after restaurant pushback

Chicago aldermen approved a compromise delaying the phaseout of the tipped minimum wage for restaurants, handing Mayor Brandon Johnson a setback.

May 20 • 4:45 PM EDT • Business • chicagobusiness.com

New drug approach offers hope for patients with recurrent aggressive cancers

Merck announces that sac-TMT, a new cancer drug, demonstrated strong results in phase 3 trials for advanced or recurrent endometrial cancer patients.

May 19 • 11:52 PM EDT • Health • foxnews.com

See images of Reno Neon Line entertainment district’s next phase

Jacobs Entertainment shared new renderings of the next phase of its downtown Reno Neon Line entertainment district project.

May 19 • 4:53 PM EDT • Entertainment • rgj.com

See images of Reno Neon Line entertainment district’s next phase

Jacobs Entertainment shared new renderings of the next phase of its downtown Reno Neon Line entertainment district project.

May 19 • 4:53 PM EDT • Entertainment • yahoo.com

Jacobs Entertainment celebrates the completion of Phase One in Downtown Reno

Jacob’s Entertainment is celebrating the completion of Phase One, following a $400 million investment and five years of revitalizing the historic 4th Street in Downtown Reno.

May 18 • 9:42 PM EDT • Entertainment • kolotv.com

Jacoby Brissett’s holdout is a strongly miscalculated risk

The NFL offseason has entered the OTA phase, and teams like the Arizona Cardinals will soon transition into minicamps before they know it. In just a few months, the preseason will usher in the return of professional football. The Cardinals,…

May 18 • 8:33 PM EDT • Sports • sports.yahoo.com

New Reno entertainment district to add Vegas-style showroom

May 18 • 4:47 PM EDT • Entertainment • rgj.com

Jacobs Entertainment completes Phase One of Reno’s Neon Line District

The celebration took place in the property's new 4th Street expansion.

May 18 • 3:09 PM EDT • Entertainment • 2news.com

Jacobs teases next phase of Reno Neon Line entertainment district

Jacobs Entertainment shared plans for what’s next for the Reno Neon Line district after the initial $400 million first phase.

May 18 • 1:31 PM EDT • Entertainment • rgj.com

Sara Duterte Trial to Open Next Phase of Philippine Political Turmoil

After a tumultuous week that started with a Senate power grab and descended into a terrifying night of gunfire, the impeachment saga against Philippine Vice President Sara Duterte moves Monday to the trial phase.

May 17 • 7:00 PM EDT • Politics • bloomberg.com

Belonging after disaster: How 'ibasho' may aid mental health recovery

Natural disasters drastically affect human lives—destroying homes, separating families, leading to disruption of daily routines, which affects their stability. While emergency mental health responses ...

May 17 • 2:00 PM EDT • Health • medicalxpress.com

Report: Liverpool ready to move for PSG star

Liverpool Push Hard for Barcola DealLiverpool’s long-standing admiration for Liverpool FC winger Bradley Barcola appears to be entering a decisive phase, with growing indications that the player is ...

May 17 • 10:55 AM EDT • Sports • sports.yahoo.com

WIU to add two new emphases to M.S. degree in computer science

University officials noted that prospective students frequently inquire about specialized study options in artificial intelligence and cybersecurity. The newly approved

May 17 • 8:26 AM EDT • Science • muddyrivernews.com

With high hopes, Yale continues to invest in Upper Science Hill

The University has poured hundreds of millions of dollars into the development of Upper Science Hill, which University leaders say will significantly improve research opportunities at Yale. The first phase is set to be completed this fall.

May 16 • 8:00 PM EDT • Science • yaledailynews.com

Women’s Health Services Expanded in Berkeley

Pictured above left to right: Lylia Trieu CMA, Gloria Gomez CMA, Mayte Hernandez CMA, Dr. Isabelle Cohen, Kelly Alvarez CMA, Ania Werynski CMA, Rachel Gonzalez CMA Sutter East Bay Medical Group is expanding women’s health services in Berkeley with the completion of Phase II at the Adeline Care Center, which has been operating since […]

May 14 • 8:08 PM EDT • Health • vitals.sutterhealth.org

Minnesota readies first-ever K-12 health education standards

Advocates say the new standards, set to be phased in over the next three years, introduce needed guidance on nutrition, first aid, sex and abuse prevention. Some school watchers worry the standards will burden already overwhelmed educators.

May 14 • 5:00 AM EDT • Health • mprnews.org

Paramount Sports Entertainment Makes Trio of Hires

"Their leadership will be instrumental in driving our production pipeline, expanding partnerships, and supporting our next phase of growth," says unit head Jesse Sisgold.

May 14 • 4:07 AM EDT • Entertainment • yahoo.com

YAS ISLAND TO BE HOME OF SPHERE ABU DHABI, A NEW GLOBAL ICON FOR IMMERSIVE ENTERTAINMENT

The Department of Culture and Tourism – Abu Dhabi (DCT Abu Dhabi) and Sphere Entertainment Co. (NYSE: SPHR) today announced that Yas Island has been selected as the location for Sphere Abu Dhabi, a landmark project with a construction phase cost of USD 1.7 billion. Poised to become a global icon, the venue will attract tourists from around the world, boost economic diversification, and strengthen Abu Dhabi's sense of place for residents and visitors alike. Sphere Abu Dhabi, which will be the first Sphere venue outside the United States, will be built on a plot of land between Yas Mall and SeaWorld Abu Dhabi, with lush green surroundings and proximity to other Yas Island theme parks and attractions. Construction on the venue is expected to be completed by the end of 2029. HE Mohamed Khalifa Al Mubarak, Chairman of DCT Abu Dhabi, said: "Abu Dhabi has always built for the long term, and Sphere Abu Dhabi is a powerful demonstration of that commitment. In a region where the appetite for

May 13 • 8:00 PM EDT • Entertainment • investor.sphereentertainmentco.com

The war between businesses and hackers enters a perilous new phase

AI agents present novel dangers

May 13 • 4:23 PM EDT • Business • economist.com

Exclusive: First look inside Loudoun’s new Pinstack entertainment center

A huge new entertainment venue with bowling, video games, bumper cars, laser tag and more is getting ready to open in Loudoun County and The Burn got a sneak preview tour of the facility. We're, of course, talking about Pinstack which is in the final phases of construction at the Kincora center off Russell Branch

May 13 • 11:05 AM EDT • Entertainment • theburn.com

Relmada Therapeutics Reports First Quarter 2026 Financial Results and Provides Business Update

Positive 12-Month Phase 2 data for NDV-01 demonstrated a 95% complete response (CR) rate at any time and a durable 76% CR rate at 12 months in high-risk non-muscle invasive bladder cancer (NMIBC), and a 94% CR rate at any time and a durable 80% CR rate at 12 months in the BCG-unresponsive subpopulation, reinforcing best-in-class potential in NMIBCOn track to initiate Phase 3 RESCUE registrational program in second line (2L) BCG-unresponsive and adjuvant intermediate-risk NMIBC in mid-2026Filed p

May 12 • 4:05 PM EDT • Business • finance.yahoo.com

HHS launches competition to support community care hubs working with health care providers

The Department of Health and Human Services Administration for Community Living has launched the first phase of its Health at Home Challenge, a competition to support community care networks that have partnered with health care providers supporting dually eligible Medicare and Medicaid beneficiaries.

May 12 • 11:20 AM EDT • Health • aha.org

AbCellera Reports Q1 2026 Business Results & Announces Positive Interim Phase 1 Clinical Data for ABCL635

VANCOUVER, British Columbia, May 11, 2026--AbCellera Reports Q1 2026 Business Results & Announces Positive Interim Phase 1 Clinical Data for ABCL635

May 11 • 4:05 PM EDT • Business • finance.yahoo.com

Tax break for United Center’s 1901 Project advances amid union pushback

The request for a property tax break has given a hospitality union leverage in negotiations over permanent jobs created in the $500 million first phase of the $7 billion mixed-use development.

May 11 • 3:37 PM EDT • Business • chicagobusiness.com

11 Reasons to Wait for the iPhone 18 Pro

We're only four months out from the launch of Apple's premium next-generation smartphone lineup, and while we're not expecting a sea change in terms of functionality, there are still several enhancements rumored to be coming to the iPhone 18 Pro and iPhone 18 Pro Max. One thing worth noting is that Apple is reportedly planning a major change to its iPhone release cycle this year, adopting a two-phase rollout starting with the iPhone 18 series.

May 11 • 12:01 PM EDT • Technology • macrumors.com

UWL hosts groundbreaking ceremony for phase two of the Prairie Springs Science Center

On Friday, May 8, members of the University of Wisconsin-La Crosse community and local media gathered at the south end of the Cowley Hall construction site for the ceremonial groundbreaking of the second phase of the Prairie Springs Science Center. “Today is a great day for this campus. We are here to celebrate something that...

May 9 • 11:57 AM EDT • Science • theracquet.org

UWL breaks ground on phase two of Prairie Springs Science Center project

A local university is beginning the next step of a major science facility that's been years in the making.

May 8 • 3:55 PM EDT • Science • weau.com

Official Feature Entertainment Group (OFEG) Announces Strategic Alliance with Nubian TV to Expand Digital Distribution

BEVERLY HILLS, Calif., May 08, 2026 (GLOBE NEWSWIRE) -- Official Feature Entertainment Group (“OFEG”), a next-generation entertainment and media platform focused on premium digital access and scalable content experiences, today announced a strategic alliance with Nubian TV, a Boston-based OTT distribution platform operated by Leverett Media. The collaboration is designed to support OFEG’s Phase I rollout of live-stream and on-demand content distribution, expanding audience reach through integrat

May 8 • 10:17 AM EDT • Entertainment • finance.yahoo.com

The Meadow tops Amazon's future Bellevue tower site

The company says it created the green space to activate the site during interim development phases.

May 7 • 8:00 PM EDT • Business • djc.com

Xenon Reports Q1 2026 Financial Results and Provides Business Update

Reported positive topline data from Phase 3 X-TOLE2 study of azetukalner in FOS in March and anticipate NDA submission in Q3 2026Five additional Phase 3 studies of azetukalner continue to enroll in epilepsy and depression indications with Phase 3 X-NOVA2 MDD topline data expected in H1 2027 Phase 1 studies of novel NaV1.7 (XEN1701) and KV7 (XEN1120) candidates expected to complete H2 2026 to support Phase 2 proof-of-concept studies in pain Cash, cash equivalents and marketable securities of $1.3

May 7 • 4:01 PM EDT • Business • finance.yahoo.com

FDA's New Playbook: Lots of Media Announcements but Not Much Rulemaking

WASHINGTON (AP) — In one of his first major announcements as health secretary, Robert F. Kennedy Jr. called a news conference to unveil a plan to “phase out” synthetic food dyes. Food and Drug Administration Commissioner Marty Makary opened the event by saying his agency was “removing all ...

May 7 • 9:06 AM EDT • Health • usnews.com

First phase completed of BAE Systems' expansion project in Endicott

The expansion will create up to 134 jobs onsite, officials say.

May 6 • 2:20 PM EDT • Business • spectrumlocalnews.com

CMC Sports Bowl coming along

Construction of Claremont McKenna College’s Roberts Campus Sports Bowl, the large athletics complex taking shape on the former quarry site east of Claremont Boulevard, is continuing. Phase One of the project, expected to open in the fall, encompasses 35 acres along the southern portion of the 74-acre site. Courier photo/Peter Weinberger

May 5 • 2:35 PM EDT • Sports • claremont-courier.com

Vault: Stablecoin politics exit the ‘nice’ phase

A major coalition of the bank trade associations announced Monday evening that they were dissatisfied with a compromise brokered by Sens. Thom Tillis (R-N.C.) and Angela Alsobrooks (D-Md.) to restrict stablecoin yield and rewards.

May 5 • 12:22 PM EDT • Politics • punchbowl.news

LOOK: Chicago Bears hit the practice field during offseason program

The Chicago Bears are back on the practice field as phase two of the offseason program kicks off.

May 5 • 12:10 PM EDT • Sports • sports.yahoo.com

Coinbase is laying off 14% of staff, citing AI. Read the CEO's letter.

In a Tuesday X post, CEO Brian Armstrong said the cuts were to "be leaner, faster, and more efficient for our next phase of growth."

May 5 • 7:24 AM EDT • Business • businessinsider.com

IDEAYA Biosciences Reports First Quarter 2026 Financial Results and Provides Business Update

Phase 2/3 registrational trial (OptimUM-02) of darovasertib combination met its primary endpoint; complete data will be provided in a late-breaking oral...

May 5 • 6:00 AM EDT • Business • prnewswire.com

🚨 River’s surprise squad for the Tucumán clash

River will face Atlético Tucumán this Sunday at 6:30 p.m. in the final matchday of the tournament’s regular phase. With qualification already secured, Eduardo Coudet unveiled a surprising squad ...

May 2 • 9:40 PM EDT • Sports • sports.yahoo.com

NICK STROBEL: Constellations on display this spring

On Friday, the moon was at full moon phase. Since the lunar phase cycle is 29.5 days long, May will have a "blue (full) moon" at the end of the

May 2 • 3:00 AM EDT • Entertainment • bakersfield.com

Why Sustainability In Business Is Entering A More Operational Phase

Sustainability is still embedded across many corporations, which are now grappling with extreme weather events, driven by climate change.

Apr 28 • 5:06 AM EDT • Business • forbes.com

Scientists capture electrons forming strange patchy patterns inside quantum materials

Researchers have, for the first time, directly visualized how electronic patterns known as charge density waves evolve across a phase transition. Using cutting-edge microscopy, they found these patterns form unevenly, breaking into patches influenced by tiny structural distortions. Unexpectedly, small pockets of order persist even above the transition temperature. This reveals that electronic order fades gradually rather than disappearing all at once.

Apr 27 • 8:00 PM EDT • Science • sciencedaily.com

OAK’s Restroom Renovation Program wins Airport Business News’ 2026 Project of the Year

Award recognizes innovative redesign of one of the airport’s most-used amenities Oakland, Calif. – April 27, 2026: Oakland San Francisco Bay Airport (OAK) has been named the recipient of Airport Business News’ 2026 Project of the Year for its Terminal Restroom Renovation Program, Phase 1. The award recognizes the airport’s achievement in transforming aging restroom facilities […]

Apr 27 • 12:09 PM EDT • Business • portofoakland.com

Sibel Health Awarded a $3.5 million ARPA-H Direct-to-Phase II SBIR Contract to Develop a First-In-Class Wearable Sensor for Continuous Edema Monitoring

/PRNewswire/ -- Sibel Health, an award winning medical technology company, today announced that it has been awarded a $3.5 million dollar Direct-to-Phase II...

Apr 27 • 9:00 AM EDT • Health • prnewswire.com

PENN Entertainment Weighs Alberta Online Launch Against 2026 Profit Goals

PENN Entertainment is preparing to launch regulated iCasino and online sports betting in Alberta, Canada in July. The company is reshaping its Interactive segment with a focus on achieving profitability from Q4 2026 onward. PENN has an active development pipeline, including new casino and hotel projects planned through 2026. PENN Entertainment (NasdaqGS:PENN) is shifting attention from recent earnings headlines to a new phase of online expansion in Alberta, where regulated iCasino and...

Apr 25 • 10:07 PM EDT • Entertainment • finance.yahoo.com

IKOL Introduces AI Platform Enhancements to Support Small and Medium Businesses

Boston, Massachusetts, United States, April 25, 2026 -- IKOL has announced a new development phase for its AI website building platform, introdu...

Apr 25 • 12:24 PM EDT • Business • markets.businessinsider.com

Which businesses qualify for tariff refunds, and how do you apply?

The government expects to process refunds in phases, focusing first on more recent tariff payments.

Apr 25 • 7:43 AM EDT • Business • thehill.com

AI may be approaching a new phase in healthcare, on two fronts

Artificial intelligence is becoming so user-friendly that doctors can code custom clinical workflow tools. But AI-driven vulnerability discovery is fast reshaping cybersecurity imperatives for IT leaders.

Apr 24 • 10:03 AM EDT • Health • healthcareitnews.com

Washington’s Allies? Japan, Germany and South Korea

The recent increase in defense spending by Germany, Korea and Japan also signals a new phase in this relationship of dependency with the US.

Apr 24 • 12:38 AM EDT • Politics • politicstoday.org

Cumberland takes $100M cash deal, keeps three Phase II programs

Shareholders must approve the Apotex transaction. Cumberland keeps majority ownership in CET, with top-line systemic sclerosis data next.

Apr 23 • 9:00 AM EDT • Business • stocktitan.net

World Cup last-minute ticket sales phase re-opens 50 days from kick-off

With 50 days remaining until the start of the 2026 World Cup, FIFA's last-minute sales phase re-opens on Wednesday with tickets for ​all 104 matches available on a first-come, first-served basis.

Apr 22 • 9:18 AM EDT • Sports • reuters.com

GE HealthCare touts international expansion of its partnership with RadNet

The companies say they’re entering the next phase of collaboration, offering GEHC mammography systems paired with AI offerings from DeepHealth.

Apr 21 • 11:48 PM EDT • Business • radiologybusiness.com

This “quantum” material fooled scientists and revealed something new

A mysterious magnetic material once thought to host an exotic “quantum spin liquid” has turned out to be something entirely different—and possibly just as intriguing. Scientists studying cerium magnesium hexalluminate found it showed the hallmark signs of this elusive quantum state, like a lack of magnetic order and a spread of energy states. But after closer inspection using neutron experiments, they discovered the behavior came from a delicate tug-of-war between two opposing magnetic forces.

Apr 21 • 8:00 PM EDT • Science • sciencedaily.com

5 Steps for Small Business Succession Planning

In this course on the ASI Learning Network, Jeannette Rhodunda of ASI discusses important moves small-businesses owners should make to prepare firms for their next phase.

Apr 21 • 10:45 AM EDT • Business • members.asicentral.com

Paradigm Health Launches SPIRE to Accelerate Late-Phase Clinical Evidence Generation

/PRNewswire/ -- Paradigm Health today announced SPIRE — Scalable Platform for Integrated Research & Evidence — a new model for post-approval and late-stage...

Apr 21 • 10:01 AM EDT • Health • prnewswire.com

A bizarre new state of matter may be hiding inside Uranus and Neptune

Deep inside planets like Uranus and Neptune, scientists may have uncovered a bizarre new state of matter where atoms behave in unexpected ways. Advanced simulations suggest that carbon and hydrogen, under crushing pressures and scorching temperatures, can form a strange hybrid phase—part solid, part fluid—where hydrogen atoms spiral through a rigid carbon framework. This unusual “superionic” structure could reshape how heat and electricity flow inside these distant worlds, potentially helping explain their mysterious magnetic fields.

Apr 21 • 8:00 AM EDT • Science • sciencedaily.com