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Apple Boosts AppleCare+ Monthly Prices by 50 Cents in Latest Increase
Apple Inc. slightly raised the cost of individual AppleCare+ service subscriptions, marking its latest price increase in the face of a global memory shortage and other challenges.
NextGen internship program offers a whirlwind tour of genetics
From working in a research lab to participating in hands-on group activities, high school students get an inside look at biomedical science during a five-week summer internship with the Department of Human Genetics.
Global misinformation takes center stage at Emory conference
Emory College brought together leading scholars to study propaganda and information manipulation, emphasizing feedback and collaboration over traditional presentations to better address the growing global impact of disinformation.
IBM shares plunge as AI spending boom disrupts business
Shares in IBM plunged 24 percent on Tuesday after the US tech giant released disappointing preliminary second-quarter results, blaming a shift in spending by customers due to expected higher prices for memory chips and other AI-related infrastructure.A global rush by tech companies to build out artificial intelligence infrastructure has sent demand for servers, memory chips and storage soaring, driving up prices and creating supply shortages across the industry.
Apple in talks with startup that shrinks AI models to run on an iPhone
PrismML says its compressed version of Alibaba’s Qwen model uses up to 15 times less memory, potentially advancing Apple’s AI push.
Atlanta Dream and Emory Healthcare Announce Unique Collaboration to Advance Women's Health, Both On and Off the Court
Multi-year partnership will provide world-class athlete care, expand access to women's health resources, and use the power of sport to improve health outcomes for women and girls across Georgia ATLANTA (July 14, 2026) – The Atlanta Dream today announced a multi-year partnership with Emory Healthcare, naming Emory Healthcare the Official Team Healthcare Provider and Official Sports Medicine Provider of the Atlanta Dream. Rooted in a shared commitment to advancing women's health, the collaboration will deliver elite athlete care while expanding access to trusted health education and wellness resources throughout the community. A New Model for Women's Health The Atlanta Dream and Emory Healthcare believe sports can become one […]
IBM forecasts preliminary Q2 revenue below estimates as spending shifts to AI
IBM's preliminary second-quarter revenue forecast came below Wall Street estimate on Tuesday, as customers prioritized spending on AI infrastructure, including servers, storage and memory purchases, sending its shares slumping 17% in premarket trading.
Payback politics? Wu backs challengers to state senators who blocked her tax plan
In a highly unusual move in the insular world of Massachusetts politics, Wu is the first mayor in recent memory to openly campaign against state senators who have blocked her priorities.
A heart for health
Albany High retiree Mary Kelly has a heart for health that expands beyond her professional responsibilities. Not only did she serve the City School District of Albany for over 23 years as a nurse, she also has been a faithful supporter of our food pantry here at Albany High! Since June 2022, Kelly has given a monthly donation to the Regional Food Bank of Northeastern New York specifically designated for Albany High. Thanks to Kelly and other individual donors and partner organizations, our students and their families can have access to nutritious food, free of cost at the Falcon Market. As someone who raised three boys, she knows how hard it can be to keep one’s shelves stocked at home. “I remember when they would sit down, three teenagers, eating a box of cereal a piece as a snack,” Kelly reminisced with a laugh. “Who can afford that nowadays?” Known affectionately as Nurse Kelly throughout her career in the district, she served our students at the elementary, middle and high school levels, and was stationed at Albany High from 2019 until her retirement. By caring for students day in and day out, Kelly was keenly aware of the negative impact of food insecurity on the lives of young people. This is what motivated her to take a proactive step towards improving access to nutritious food for our students and families. Kelly’s generosity is a way to carry on the memory of her youngest son, who passed away in 2019. “The kindnesses that I do are always in his memory,” Kelly shared. On behalf of our Albany High staff, students and families, we thank Nurse Kelly for her incredible support and wish her all the best during her retirement. For more information about how to support the Falcon Market with in-kind or financial donations, please contact Joey DiPiazza at jdipiazza@albany.k12.ny.us.
New MemGhost Attack Plants Persistent False Memories in AI Agents Through One Email
A single crafted email can plant a false, lasting memory in AI agents like OpenClaw, hide it from the user, and slip past the defenses built to catch
The new* Home Run Derby, plus Pulisic’s future
The Pulse Newsletter 📣 | This is The Athletic’s daily sports newsletter. Sign up here to receive The Pulse directly in your inbox. Good morning! Watch your swings today. Coming up: ⚾ Vintage HR Derby 🎾 Sinner’s silky serve 🇺🇸 Pulisic’s future The Home Run Derby returns tonight from Philadelphia, where All-Star festivities are happening this week. It will be a radically different experience than what we’ve seen in recent memory. But that doesn’t mean it’s new. Quick catch-up before we get to opinions: Instead of outs, hitters will get a limited number...
AI Is Breaking the Memory Chip Business Model
Investors who piled into SK Hynix’s $28 billion blockbuster Nasdaq debut on Friday should be aware: The business model on which the world’s leading memory chip makers are thriving is set to shift to one that requires a bit more strategic and financial gambling. So far, SK Hynix Inc. is making all the right moves but it’s unclear how well the field’s leading players will deal with that disruption.
Apple M7 Ultra Chip Planned With Up to 1.5 TB of Unified Memory
Apple has recently overhauled its entire M-Series chip plans, scrapping the launch of the M6 Pro and M6 Max processors and jumping straight to the M7 series. While the base M6 SoC is expected to launch, Apple is moving into the M7 series without the M6 Pro/Max variants, with plans to offer some...
Bob on Business: The return of a sweet Fort Worth memory
Also, burger town; aviation merger; banking a basketball.
Apple's M7 Ultra Chip Designed to Match a 2019 Mac Pro Feat
Apple's M7 Ultra chip coming in 2028 is designed to support up to 1.5TB of unified memory, according to Bloomberg's Mark Gurman. However, whether such a configuration is offered may depend on the state of the ongoing memory chip shortage. However, whether such a configuration is offered may depend on the state of the ongoing memory chip shortage.
Alzheimer's tau protein has a surprising secret role in memory
Researchers found that tau is essential for turning new experiences into lasting memories by helping organize the brain's memory-storing cells. The mouse study also revealed how abnormal tau may contribute to Alzheimer's by disrupting both the formation of new memories and the recall of existing ones.
Ryse: Son of Rome Is Now Just an Xbox One Memory, but in 2013 It Was Planned To Be an Era-Hopping Franchise To Rival Assassin’s Creed’s Global Ambition
Ryse: Son of Rome was originally planned to explore multiple eras, Assassin's Creed style, before critical and commercial failure sank Crytek and Xbox's ambition.
Young Cuban Americans’ political shift is real. It just hasn’t hit the ballot box yet
Young Cubans in Miami who never experienced Castro’s oppression have inherited only the memory and not the wound. | Opinion
Katie Couric shares health scare
Journalist Katie Couric describes the terrifying moments when she lost her memory just a few weeks ago. She was diagnosed with transient global amnesia - a sudden episode of memory loss that’s rare. NBC News’ Kate Snow has the story.
We remember little to nothing of early childhood — and a recent mouse study may help explain why
Early in life, neural networks in the brain's memory center are highly connected, and they are only later refined into precise systems, a mouse study finds.
Niecey Shaw on entertainment headlines
Jermaine Dupri is said to be suing Sony, and Katie Couric recalls having memory loss after a medical episode.
New Science Says Training Your Nose Can Slow Brain Aging (Yes, Really)
Smell training is an easy but overlooked way to leverage your nose to improve your memory and cognitive function.
Saby Mitra named next dean of Goizueta Business School
Read Saby Mitra named next dean of Goizueta Business School by Emory University for SaportaReport here.
Katie Couric reveals amnesia caused 'black hole' in her memory
For most of one day in June, Katie Couric couldn't recall who was president or some of her family members.
Incredible new material makes heat programmable
A newly developed material can control and "program" heat, allowing it to direct thermal radiation, switch modes, and remember its settings without continuous power. The innovation could lead to smarter infrared sensors, better energy technologies, and memory devices that use light and heat instead of electrical charges.
Scientists discover how astrocytes help memories last
Some memories remain with us for years, shaping how we learn from experience and adapt to the world around us. Others disappear quickly, even when they once seemed important. Although scientists have long studied how memories are formed in the brain, far less is known about what allows certain memories to persist over time. A research team led by Dr. KOH Wuhyun at the Center for Memory and Glioscience within the Institute for Basic Science (IBS), together with researchers at the Korea Brain Research Institute (KBRI), has now discovered that astrocytes play a critical role in this process. Astrocytes are star-shaped cells in the brain that have traditionally been considered support cells for neurons. The study shows that these cells actively help determine whether memories can be maintained over long periods of time, revealing a previously unknown mechanism that supports long-term memory persistence.
Capitol Hill Programming: The Power and Peril of Food: The Latest Science on Your Mood, Memory, Metabolism, Fertility, and Longevity
On Wednesday, July 29th, join Food Tank and Tufts University Food is Medicine Institute for the U.S. Capitol Hill Programming, “The Power and Peril of Food: The Latest Science on Your Mood, Memory, Metabolism, Fertility, and Longevity.”
Support well-being with these tools for connection and mental health
Emory University and Emory Healthcare employees have access to a variety of resources to support stronger connections and improve mental health and overall well-being. Summer is a great time to see what’s available.
No to Taylor Ham, Bruce ticket. NJ adds 'inspiration' to time capsule
Every state, U.S. territories and the District of Columbia submitted mementos for a memory trove to be opened in 2276
Apple’s Strategy To Minimize iPhone 18 Pro Price Rise
As memory costs push the iPhone 18 Pro retail price upward, Apple can rely on services such as online backups and connected accessories to prevent premium users from moving to Android.
Roob's Eagles Observations: Bryce Huff's hilariously misguided memory of 2024
Why Jeff Lurie is the best owner in Philadelphia sports history, Bryce blaming everyone but himself and more in Roob's Eagles Observations.
iPhone 18 Pro Strategy Tests Premium Brand Loyalty
As memory costs push the iPhone 18 Pro retail price upward, Apple can rely on services such as online backups and connected accessories to prevent premium users from moving to Android.
I took my 3 kids to a Mets Sunday family game. It's a core memory.
Watching my three children experience their first Major League Baseball game reminded me why family traditions are worth starting.
AYANEO NEXT 2 Strix Halo handheld starts global shipping in late July, top SKU hits $5,299
AYANEO is preparing global NEXT 2 shipments for late July after months of delays. The top Ryzen AI Max+ 395 configuration now reaches $5,299 as memory and storage costs continue to affect availability.
Chinese team’s brain-mimicking chip ‘up to 478 times faster than Nvidia GPU’
New chip performs data storage and computation in a single memory array, enabling real-time modelling of complex brain structures, team says.
Amazon's Fire HD 10 Tablet Just Got A Refresh With A Bit More RAM
A RAM upgrade? In this memory economy?!
Could your gut bacteria really slow Alzheimer’s? Scientists reveal a surprising link - Futura-Sciences
European researchers previously demonstrated that transferring stool samples from human Alzheimer’s patients into healthy rats triggered symptoms like spatial memory issues. Other models show that altering gut microbes changes the buildup of amyloid plaques and tau proteins, the two main hallmarks of the disease. Scientists have even found that certain...
Intel Expected To Restart Supply Of 10th, 12th, 13th, And 14th Gen Processors In Mainland China
Intel will reportedly focus more on the previous-gen processors to fulfill the current demand in the PC market. Intel is Reportedly Restarting Supply of Last Four Generation of Processors as Motherboard Vendors Ramp Up DDR4 Platform Production Roughly a month ago, we reported that some vendors are now restarting the production of DDR4 platforms, i.e., DDR4-compatible motherboards. This is to ensure the market gets DDR4 motherboards in sufficient quantity, as expensive DDR5 memory has made it unfeasible to build DDR5 systems on a budget. More reports are surfacing confirming the same report, and Intel appears to have prepared accordingly. Related […]
The Iran MOU is a mess. It still might work
The 14-point “Memorandum of Understanding” is among the oddest international agreements in recent memory. Short on detail, its two pages purport to grant significant up-front American concessions to Iran in exchange for opening the Strait of Hormuz, which was already open before the war President Donald Trump started in February and now hopes to end.
Apple plans five new iPhones through 2027, eyes Chinese-made chips amid foldable push, reports say
Apple is planning five new iPhones by 2027 and is considering Chinese memory suppliers as it expands foldable production, reports say.
Apple to launch 5 new iPhone models to gain market share amid memory crunch
Company raises production target for first foldable phone to about 10 million units
Cinder City asks for 64GB RAM in recommended PC specs
Cinder City now lists 64GB RAM as recommended on Steam. The open-world shooter also asks for 32GB RAM as the minimum PC spec.
CitrixBleed To Infinity And Beyond (Citrix NetScaler Pre-Auth Memory Overread CVE-2026-8451)
Well, well, well - once again, the cat has dragged us in, and spat us out. Today, we find ourselves questioning the reality we sit within. Must it be so predictable, and why us? “But watchTowr, what do you mean?” Well, if you’re here, you likely fit into one of
Proton launches Lumo 2.0 with image generation, memory, more
Today, Proton is introducing Lumo 2.0, in what the company says is the largest upgrade to its privacy-first AI assistant to date.
Xbox Expects The 'Component Crisis' To Get Worse For Consoles In 2027
Specifically for console storage and memory prices
Millions take omega-3 fish oil for brain health but a new study found no benefit
Fish oil supplements successfully delivered omega-3s to the brain, but a two-year study found no meaningful benefits for memory, cognition, or Alzheimer’s-related brain changes. The results challenge the idea that fish oil pills can help prevent Alzheimer’s and shift attention toward overall diet and lifestyle instead.
Millions take omega-3 fish oil for brain health but a new study found no benefit
Fish oil supplements successfully delivered omega-3s to the brain, but a two-year study found no meaningful benefits for memory, cognition, or Alzheimer’s-related brain changes. The results challenge the idea that fish oil pills can help prevent Alzheimer’s and shift attention toward overall diet and lifestyle instead.
Texas Mental Health Program Reveals 103% Increase in Veteran Enrollment
Emory University treatment is expanding throughout the state at no cost, but many veterans remain unaware of their services.
What watching a sunset can do for your brain
Humans appear to see sunrises and sunsets "almost like bookends". Here's what a daily dose of golden hour can do for our memory, sleep and mood.
The Simplest Focus Booster Is Sitting in Your Drawer Right Now
Science shows that writing by hand strengthens the brain by improving memory, focus, and deep thinking compared to typing.
30 Day Challenge: Most Painful Bears Memory
What is the most painful Bears memory of yours? @BryanOrenchuk shares his!
Apple A20 Pro motherboard leak hints at notable memory and packaging upgrades
A leaked package layout of Apple's A20 Pro hints at several notable upgrades for the iPhone 18 Pro series. The next-gen SoC is said to feature a wider 96-bit memory interface, a redesigned packaging approach for improved thermals, and a larger Neural Processing Unit (NPU).
Healthcare AI Leaders Are Rapidly Trying To Outmaneuver Skyrocketing Memory And GPU Costs
Compute power has become one of the most crucial components of the healthcare delivery cycle.
New Linux pedit COW Exploit Enables Root Access by Poisoning Cached Binaries
CVE-2026-46331 lets local users gain root on affected Linux systems by corrupting page-cache memory through act_pedit.
Valve Would "Love to Make the Steam Machine More Affordable" - Just Don't Expect It "Any Time Soon"
If memory prices go down - and that's a big if.
Smart voices in business react to Apple and Xbox price hikes
After Apple and Microsoft's Xbox raised prices due to a shortage of memory chips, tech observers are not optimistic about future prices.
It's Xbox's turn (again), as console prices keep going up
Microsoft announced a price hike for the Xbox Series consoles today, the third in little over a year. Effective August 1, the Xbox Series S, which launched in 2020 for $300, will cost $500 in the U.S. The Xbox Series X, which launched in 2020 at $500, will go for $800. This follows a round of PlayStation 5 price increases from Sony this spring, and a slow-motion increase for Nintendo’s Switch 2, which will kick in in the U.S. in September. (Mind you, there were also eight video game industry price hikes in six months of 2025). The chart up top shows the sudden ascent of console prices over the past year, a sudden surge in an already unusual hardware generation. Prices had been flat for years, now “up” is the new “flat.” Game console prices used to go down across the length of a console generation, but not this time around. Microsoft’s explanation for the new price hike today: We hoped another price increase would not be necessary, and we have spent the last several months working with suppliers on options. Unfortunately, console storage and memory prices have increased by more than 2.5x and we expect another doubling by the fall of 2027. The entire consumer electronics industry is struggling with the current components crisis, but the effects are particularly hard on consoles. Unlike phones, computers, speakers, and other consumer devices, consoles are typically not sold at a profit, but instead for less than they cost to make. This is an issue well beyond game consoles. Apple announced price hikes on its computers and tablets today as well. Game File is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Item 2: Brutal Bungie cuts Bungie laid off “most” of its Destiny development team and some developers who worked on Marathon, the newest game from the struggling Sony-owned studio. A WARN notice issued by Sony to Washington State, where Bungie is based, tallied cuts impacting 292 workers, effective next month. That’s strictly for Bungie/Sony jobs in Washington and wouldn’t account for any elsewhere. The video I clipped below shows the redacted list of Bungie cuts filed to Washington State officials. As you’ll see, I had to scroll for a while… In a note emailed to PlayStation workers and published online, PlayStation game studios chief Hermen Hulst offered the following explanation for these latest cuts at Bungie: This is painful news, especially for talented colleagues whose roles have been eliminated. This decision was made only after extensive discussion and careful consideration, and I want to provide some context on how we arrived here. Over the past several months, together with Bungie leadership, we reviewed the studio’s long-term direction, development priorities, resource needs, and role within our broader portfolio strategy. We explored multiple alternatives before concluding that a reduction was necessary to align the studio’s resources with its current priorities and long-term goals. In 2022, Sony bought Bungie for $3.7 billion. The studio’s marquee game, the multiplayer live service shooter Destiny 2 was losing popularity at the time. Its next game Marathon, released earlier this year, has been well-reviewed but had a slow start. Bungie is renowned for making great shooter games, and Destiny fans have mourned the wind-down of Destiny 2. They’ve also expressed bewilderment over reports that Destiny 3 is not, per Bloomberg, immediately in the cards.
Microsoft is raising Xbox prices yet again — this time by up to $150
Microsoft said memory and storage prices have increased by "more than 2.5x" and it expects "another doubling by the fall of 2027."
Xbox prices spike another $100 or more
Xbox blames the memory shortage for the price hike.
Apple raises Mac and iPad prices by as much as 25%
Apple CEO Tim Cook had earlier warned of price increases due to the memory chip shortage.
Grading every move from the Steelers’ 2026 offseason
Did the Steelers hit the mark in one of their most pivotal offseasons in recent memory?
Framework Laptop 13 Pro Intel mainboard now starts at $449 with optional LPCAMM2 memory from $439
Framework is now selling Intel Core Ultra Series 3 mainboard kits for the Framework Laptop 13 Pro with optional LPCAMM2 memory bundles.
2026 NBA Draft grades: Updating pick-by-pick analysis from AJ Dybantsa, Cameron Boozer through Round 2
Adam Finkelstein has the breakdown of each pick in one of the best drafts in recent memory
Microsoft introduces cheaper Surface devices with half the memory
The 12-inch Surface Pro now starts at $849, while the 13-inch Surface Laptop costs $949 and up. Both start with 8GB of RAM instead of 16GB.
Highlights of Aspen Ideas: Health, day two
On June 23, Aspen Ideas: Health ushered in the actual first full day — and evening — of programming. Here are some highlights from different tracks, or themes. NextGen Health Track: On the Frontiers of Brain Health “As belly size gets larger, the memory center in the brain gets smaller,” said Richard Isaacson, director...
Micron forecasts quarterly revenue above estimates
Micron Technology forecast quarterly revenue above Wall Street estimates on Wednesday, signaling that insatiable demand for AI-related infrastructure will continue to drive strong demand for its memory chips.
'The Bear' Season 4 recap – What to remember before Season 5
Before your upcoming reservation at “The Bear” allow us to refresh your memory about the previous course, Season 4.
Microsoft relaunches 2025 Surface Pro and Laptop with half the memory, but at higher prices than original 16GB models
Microsoft is now selling cheaper Surface Pro 12-inch and Surface Laptop 13-inch configurations with 8GB of RAM.
2026 NBA Draft Grades: Analysis for AJ Dybantsa, Darryn Peterson, Cameron Boozer, rest of first-round picks
Adam Finkelstein has the breakdown of each pick in one of the best drafts in recent memory
Australia politics live: ‘Keep the flame of memory burning’, PM tells opening of new Australian War Memorial gallery
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Emory Healthcare Named Founding Partner and Official Healthcare Provider of the Arthur M. Blank U.S. Soccer National Training Center
Emory Healthcare becomes a Founding Partner of the Arthur M. Blank U.S. Soccer National Training Center, bringing nationally recognized research, innovation, and sports medicine to the new home for soccer in America.
Samsung Unveils Industry’s Fastest UFS 5.0 Solution for Next-Gen On-Device AI Applications
Samsung’s UFS 5.0 solution achieves the industry's highest data transfer speed of 10.8GB/s, enabling faster storage and processing in mobile memory Enhanced power efficiency and smaller package to provide optimal mobile AI experiences
Following user outcry, AMD reinstates memory encryption in consumer CPUs
Critics saw the move as an underhanded way to steer them toward more costly chips.
DOJ may be able to release potentially embarrassing Biden audio recordings unless courts step in
Former President Joe Biden is in an uphill battle to try to stop the Justice Department from sharing recordings it collected of him speaking to his ghostwriter in 2016 and 2017, during which his speech and memory faltered.
Opinion: Grievance, Bewilderment and Ethnic Amnesia: Poland, Ukraine and the Politics of Historical Memory
An explainer from a Ukrainian perspective to warn against a black-and-white approach to historical issues that serves politicians’ purposes but divides neighbors.
Childhood popcorn memories become successful business that's popping on Cape Cod
What started as a fond childhood memory for two brothers has now turned into a full-fledged, successful business on Cape Cod. That memory and now business is, of all things, popcorn.
I Finally Realized How I Know 'Sweet Magnolias' Star Brooke Elliott & It Hit Me Like a Truck
I finally realized where I knew Sweet Magnolias star Brooke Elliott from, and the answer unlocked a whole TV memory. Here's the iconic role I completely forgot about.
Nothing CMF Phone is a RAMageddon casualty, memory now the most expensive component
Nothing’s CMF Phone series has released two models thus far and, at least for now, won’t be getting a third,...
Scientists reprogram brain immune cells to fight Alzheimer’s
A newly identified molecule called OLE helped restore the brain’s immune cells to a more protective state in Alzheimer’s models. The treatment reduced toxic plaque buildup and improved memory, raising hopes for a new therapeutic approach.
Taking an omega-3 supplement may not boost memory or cognition
Taking an omega-3 fatty acid supplement did not improve memory, cognitive function or brain cell loss for many people, a surprising new study finds.
Souls and songs take flight in circus musical 'Water for Elephants'
A national tour of the 2023 musical tours to Madison this week, combining a memory play, circus acts and a bluegrass-style score.
Gemini Live can now access your past chats Memory, Connected Apps info
Following the big Neural Expressive redesign and new voices last month, Google has updated Gemini Live with Memory access.
Are Counterfeit, Scam SD Memory Cards Really a Problem?
A recent video claims fake, scam SD cards are so prevalent, everyone probably owns one. But is that really true?
YouTube is testing another Android redesign, and your muscle memory might hate it
YouTube is testing new changes to its player UI on the Android app, less than a year after its last redesign.
Apple CEO says price hikes are ‘unavoidable’ as rising chip costs squeeze tech giant: report
Tim Cook says Apple price increases are “unavoidable" as AI demand drives up memory chip costs, calling the supply crunch a “hundred-year flood."
A Wild Rumor Linked To Sundar Pichai Suggests Google Is “Evaluating” The Procurement Of Memory Chips From China’s CXMT
Google's move might upend the monopolistic dynamics in the memory sphere by opening a floodgate of similar DRAM deals with CXMT.
Want a new iPhone? You may want to buy it before Apple hikes prices.
Apple CEO Tim Cook warns of rising prices for iPhones, MacBooks, and iPads due to a global memory chip shortage.
Exclusive | Apple Price Increases ‘Unavoidable,’ Tim Cook Says in WSJ Exclusive
The CEO tells the Journal that Apple plans to raise prices on its products to offset the surging costs of both memory and storage.
OnePlus defies RAM crisis, offers the 15R with more memory
And the price hasn't skyrocketed compared to the options with less. There's been a lot of talk recently about RAM prices going through the roof because of...
June 18 Vallejo/Vacaville Arts-Entertainment Source: Faces and Places
Sem Yeto High School Principal John McMorris announced plans to establish the Jamario Baker Legacy Award Fund to honor Jamario’s memory and support future students who demonstrate resilience, personal growth, perseverance, and…
Users cry foul after AMD stripped memory crypto from its consumer CPUs
AMD's stripping of TSME from consumer CPUs appears to be a deliberate, covert move.
Vance’s new book puts his Catholic faith at the center of his story
The book arrives as Catholicism is, by some measures, experiencing a resurgence in the United States unlike anything in recent memory.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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