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Treasury Secretary: The US could sanction Chinese AI companies
Treasury Secretary Scott Bessent said the Trump administration is looking into whether Chinese open source AI models were built on stolen IP.
Apple Testing 7-Inch Display for Largest 20th Anniversary iPhone Model
Apple is reportedly prototyping a larger iPhone display measuring roughly 6.96 inches, which would likely be marketed as a 7-inch panel if it reaches production. According to Chinese leaker Digital Chat Station, Apple is testing the display internally in preparation for the 20th anniversary iPhone, which is expected to launch next year.
Photos show Chinese companies showcasing AI technology and robots at science forum
BEIJING (AP) — China's leading technology companies showcased hundreds of cutting-edge products at the World AI Conference in Shanghai — from advanced robotics to artificial intelligence systems.
Stocks to Watch: Alibaba, Ryanair, AMC Entertainment, Micron
↗️ Alibaba (BABA, HK:9988): Shares in the Chinese internet giant rose after it previewed its new AI model, which it said is second onl
Moonshot just gated new users from its new Kimi model
The Chinese AI startup said it saw massive demand over the last two days and had to pause new subscriptions to reduce strain on its GPUs.
Chinese company demands compensation from U.K. over British Steel nationalization
Jingye Group, the former owner of British Steel, has demanded compensation from the U.K. government for investment losses after the company's nationalization last week.
As Beijing ramps up exports, the world feels ‘China Shock’ 2.0
Trump’s tariffs have helped stem the flow of inexpensive Chinese goods to the U.S., but European factories are suffering under a flood of imported cars and tech.
Chinese fossil find shows birds shed their dinosaur tails step by step
A Jurassic fossil dating back 150 million years fills in a vital part of the evolutionary puzzle of how birds took to the skies.
‘Everyone’s health has improved’: how tai chi energises these Chinese retirees
Tai chi practitioners at Beijing’s Temple of Heaven talk about learning the ancient Chinese practice and how it benefits health and spirit.
China warns of reciprocal countermeasures after U.S. shortens foreign journalist visas
The Trump administration announced Thursday it will drastically shorten visas for foreign journalists in the U.S. to 240 days, down from years, and cut those for Chinese journalists to only 90 days, raising concerns over press freedom in the United States and prompting China to warn of possible reciprocal countermeasures.
Chinese scientists have bad news on having babies in space
Researchers use China’s Tianzhou spacecraft missions since 2017 to study how microgravity and space radiation can affect biology.
How Sport Will Change on a Hotter Planet (We Might Have to Move the Olympics) | Climate & Energy for July 16
Plus: The Strait of Hormuz isn’t going back to normal, and the Chinese EV wave threatens Volkswagen’s vast, well-paid workforce
‘Escaping Beijing’: Why some young Chinese are quitting the capital
A slowing economy and rising prices are making it harder for young Chinese to thrive in the city.
As US AI costs soar, global firms pivot to China’s cheap, open-weight models
A sharp narrowing of the performance gap is prompting some developers to shift from costly American giants to budget-friendly Chinese alternatives.
ZeniMax Online Studios leadership to exit as part of Xbox cuts
There are major changes happening atop Maryland-based ZeniMax Online Studios, developer of the Elder Scrolls Online, Game File has learned. Joe Burba, a 14-year veteran of the studio who was appointed to run it last July, is departing, along with ESO executive producer Susan Kath, studio game director Rich Lambert and production director Ala Diaz. Their roles were listed among hundreds of others cut last week from the Maryland offices of ZeniMax, in a WARN letter sent to the state by ZeniMax and obtained today by Game File. Tonight, BUrbam Kath, Lambert and Diaz notified Zenimax Online Studios workers of plans to “transition” to a new leadership team consisting of promoted ZOS veterans. That transition will occur “over the next few months,” they told workers, according to a copy of the notice reviewed by Game File. “We will remain in place during the transition period to help ensure a smooth handoff.” Last week, Microsoft laid off of 1,600 workers across its vast gaming teams in locations around the U.S. and abroad. Just who has been impacted and how hard various studios have been hit has been emerging day by day. Game File reported last week that Microsoft/ZeniMax notified officials in Maryland that 379 gaming jobs were being cut across the state. They tallied cuts in two locations: one for ZeniMax Media Inc. (covering Elder Scrolls/Starfield/Fallout-maker Bethesda Game Studios and central Bethesda game publishing) and one for ZeniMax Online Studios (Elder Scrolls Online). More than 200 jobs were cut at the latter. Last week’s totals did not reveal job titles, nor did Microsoft announce any leadership changes in the ZeniMax group. That has now happened. Earlier today, Game File obtained from Maryland officials a breakdown of the 379 impacted roles, which, extraordinarily, included “studio head.” Microsoft later confirmed to Game File which studio head that referred to: ZeniMax Online Studios’. Microsoft has since has notified studio employees and internally announced new leadership. ZOS will now be run by Josh Henderson, previously head of business operations at the studio, and Nick Giacomini, who was promoted to game director for ESO last August. Game File is a reader-supported publication. To receive new posts and support my journalism, please consider becoming a free or paid subscriber. Subscribe Last week’s news of 200+ cuts at ZeniMax Online Studios generated public sympathy for those workers and questions about the long-term viability of the Elder Scrolls Online. ESO is a massively multiplayer online game that inherently persists on the strength of new content being developed for it. Earlier today, fans and workers in Maryland protested the cuts at the ZeniMax teams in a rally organized by the Communication Workers of America, the union that represents many of the impacted employees. Regarding concerns around the game, a community manager stated on Saturday: “The plan is still to deliver great content, and we will hopefully have an update soon.” In their note to the studio today, the outgoing leaders of ZeniMax Online Studios predicted “growth” for the game: We have tremendous confidence in Josh and Nick, the future of this studio, and the continued growth of ESO. With exciting experiences still ahead for our players as we wrap up work for Update 51 and beyond, we believe that your passion, creativity, and commitment to each other and the community will continue serving as the heartbeat of ESO. The list of jobs cut in the ZeniMax WARN notice in Maryland includes several very senior roles, including: Studio Head Studio Operations Director Studio Game Director Studio Audio Director Studio Art Manager Vice President and Controller VP, Global Sales & Business Development While some of those job descriptions match the exiting ZOS leadership team, Game File couldn’t verify if all were from that studio. The full list of cut roles shared by Maryland officials also covers workers at Bethesda Game Studios and its central publishing office. The following is an excerpt: The list of 379 eliminated ZeniMax jobs in Maryland also includes: four animators three bilingual CS (community service) leads for Chinese, Italian, and Japanese a creative director for the Elder Scrolls Online Player Life Cycle two food service workers seven producers more than 60 senior QA testers. and many others The WARN notice states that almost all of the 379 workers were notified of their layoff on July 6. In fine print, it states: “Approximately 9 employees were notified of the elimination of their position prior to July 6, 2026.” A 2021 mega-merger scaled back Microsoft announced in 2020 that it intended to buy ZeniMax and its network of game studios in 2020, and closed the $7.5 billion deal in March 2021. The purchase, which preceded Microsoft’s acquisition of Activision Blizzard, added several award-winning studios to Microsoft’s portfolio, including Bethesda (Elder Scrolls, Fallout), Arkane (Dishonored), and id Software (Doom). The studios’ output since then included a 2024 Game of the Year contented from MachineGames in the form of Indiana Jones and the Great Circle along with Starfield from Bethesda and the poorly-received Redfall from Arkane Austin. In recent years, a Microsoft repeatedly in cutback mode closed ZeniMax’s Tango Gameworks (which was reconstituted by Krafton) and closed Arkane Austin. The Xbox cuts last week have hit the ZeniMax group hard, with 158 jobs eliminated in Texas, many of them at id, and 379 from the ZeniMax teams in Maryland. Xbox also said last week that it would be entering a consultation process around Arkane Lyon, a process expected to end in a sale, shutdown or other form of divestment. The Lyon team has been working on a game tied to Marvel’s Blade vampire-hunting super-hero.
Imax to Develop Entertainment System for Self-Driving Cars in China
The big-screen innovator and Goer Dynamics, an arm of the Chinese manufacturing giant behind Meta's headsets and Apple's AirPods, aim to start production by the end of 2026.
China's Sinopec establishes four business units in major overhaul, officials say
Sinopec is launching a major internal restructuring, setting up new business units and relocating hundreds of staff, as the world's biggest refiner seeks to lift profits amid flagging Chinese oil and petrochemicals demand, company officials said.
Even more Central Florida restaurants shut down over health problems
One of the eateries — a Chinese restaurant in Orlando — suffered its fourth closure this year, according to state records.
American AI is expensive. Some startups are turning to cheap Chinese models
AI is a fast-growing business expense. Some companies are cutting costs by switching to cheaper Chinese AI models.
7 Baton Rouge area restaurants cited for multiple critical health violations in July
One Chinese restaurant had “putrid” or “decomposing” food present. Here’s the latest.
NSF Won’t Fund Research Involving Chinese Scientists
The National Science Foundation will bar U.S. colleges and universities from collaborating with many Chinese scientists and other entities on the federal government’s restricted parties lists.
US National Science Foundation to ban projects with flagged Chinese institutions
Raising security fears, NSF moves from case-by-case approval to full ban on working with restricted entities and their employees.
MAGA's attack on science is even worse than it looks
In my post on America’s 250-year anniversary, I argued that respect for the individual was the “secret sauce” in the U.S.’ long-lasting preeminence among nations. But it was certainly not the only factor. There were plenty of institutional innovations that helped the U.S. stay on top — economically, militarily, and in terms of the attractiveness of its society. One of these was American science. Today we take things like the modern research university, government grants for science, public-to-private research spinoffs, etc. for granted, but a lot of that infrastructure wasn’t there before World War 2. It was either invented or scaled up massively by the U.S. government in the postwar period, led by far-sighted scientist-bureaucrats like Vannevar Bush (pictured above). If you want to read about this history, a good place to start would be Jonathan Gruber and Simon Johnson’s excellent book Jump-Starting America. Those scientific institutions didn’t exist in a vacuum, however. They were backed by the U.S. government’s abiding faith in the power of science — and, even more fundamentally, by deep popular trust in the scientific enterprise. Science gave us radar and the atom bomb in wartime, and in peacetime it gave us plastics, vaccines, cheap food, and a thousand other things that made our lives easier. Science was also the driver behind American industry — chemicals, aerospace, telecommunications, computers, electronics, and so on. We owed science our jobs, our livelihoods, our comfortable living standards, and our greatness and power as a nation. It’s little wonder that both political parties, even as they fought viciously over other issues, were steadfast in their support of science. For a long time, the only people who distrusted science were a hippie fringe on the left who disliked modernity (or thought they did, anyway), who also disliked American industry and American power, and who subscribed to an early version of degrowth environmentalism. America’s scientific enterprise is still strong, especially compared to the systems in Europe, Japan, Korea, and other developed countries. It has lost a lot of ground to China in a relative sense, but a lot of that is because of China’s incredible growth; as China has poured untold amounts of money and talent into its research labs, spending and output have overtaken the U.S. by some measures. There are a few ways in which China’s rise creates problems for American science — for example, top scientists can choose to work in China instead of in the U.S. — and of course there’s the concern that China’s technological strength will help its military to reign supreme. But overall, China’s rise in science should be good for American science, since American scientists can use Chinese discoveries for free and build on them. The much bigger problem is that the scientific enterprise America built during and after World War 2 is now being threatened with absolute decline. The biggest problem, of course, is that much of the country — the Republican half — has basically lost faith in the scientific enterprise. To what degree this loss of faith is justified is an open question, and deserves to be discussed openly. But the larger point — that the system that powered American dominance is under threat — is true either way. Most Americans still trust science, but MAGA Republicans don’t There’s a myth, popular in right-wing circles, that scientists have lost the trust of regular Americans — either due to the increasingly left-wing composition of academic departments, or to misbehavior during Covid, or to DEI-related research taking over science, etc. This also fits with a wider narrative that Americans are losing trust in all of our institutions. But it just isn’t true. Poll after poll shows that on the whole, Americans still trust scientists and want to spend more on science. For example, here’s a Pew poll from late 2025 showing that although about a fifth of Republicans did lose confidence in science in 2020, two thirds still have at least “a fair amount” of confidence: That same poll found that scientists are among America’s most trusted groups — even better trusted than the military! In fact, Americans trust scientists more than people in most other countries do. Other polls show that although Republican trust in science has dropped somewhat, Republican support for spending more on science remains very strong: A Pew poll in 2023 found the exact same thing: So when MAGA types tell you about scientists losing their credibility, or a drop in trust in science, they’re only talking about themselves. Whatever left-wing politicization of science happened during the Biden administration — and there was definitely some of that — it was not enough to make most Republicans lose faith in the scientific enterprise, or favor research cuts in order to purge unwanted ideology from the system. That doesn’t mean I think progressives should continue down the path of politicizing scientific research. They should not, and Biden made real missteps in this area. Objectivity clearly matters for public trust of science in the long term. But as of right now, there’s no crisis of trust in science, except among the smallish minority of people who are running around screaming that there’s a crisis of trust in science. But despite science’s overwhelming popularity and public trust, Trump and his administration are launching an unprecedented and devastating attack on American science — cutting funding, and forcing science projects to undergo ideological review by government commissars. Trump’s comprehensive attack on science
US scientists use Chinese humanoid robot to carry out keyhole surgery
The robot, nicknamed Surgie, was remotely controlled by human surgeons as it carried out the procedure on a pig.
New sodium metal battery design charges in just 4 minutes and retains its capacity for years
Chinese researchers say they have overcome one of the trickiest problems of battery chemistry by developing a special gel.
Foldable iPhone Ultra Battery Capacity Allegedly Registered by Supplier
Apple's battery supplier has registered two new battery cells believed to be destined for the company's rumored foldable iPhone, according to a prolific Chinese leaker. In a post on Weibo, the leaker known as Digital Chat Station said that the two cells have rated capacities of 1,921mAh and 2,962mAh, for a combined minimum rated capacity of 4,883mAh.
Samsung said to discontinue its Galaxy Z Flip lineup after the Flip8
It might be for real this time. According to a Chinese tipster with a solid track record, especially when it comes to Samsung-related leaks, the company...
Cannes Drama ‘A Girl Unknown’ Gets Domestic Deal With Greenwich Entertainment
EXCLUSIVE: Greenwich Entertainment has acquired U.S. distribution rights to A Girl Unknown, the debut feature by Chinese filmmaker Zou Jing. The movie premiered in the Critics Weeks section of the 202...
China bets on AI to speed up science despite chip limits
Driven by aggressive state policies and a national supercomputing network, Chinese labs are rapidly embedding AI into daily research
SKF eyes role in humanoid robotics business
SKF is looking to work its way into the expanding Chinese robotics market with a recently announced agreement with Leaderdrive (LD), a global manufacturer specializing in precision robotic components. The companies are working together on a venture in China focused on high-precision transmission components for robot joints. SKF officials said the investment is a step […]
Secretive Chinese probe snaps first photo of Earth's mysterious 'quasi-moon' — and it may pose a big problem
China's Tianwen-2 spacecraft has captured the first close-up photo of one of Earth's "quasi-moons," Kamo'oalewa. However, the image and the timing of its release suggest that it may be harder for the probe to collect samples from the space rock than originally planned.
iPhone Ultra Reportedly in Mass Production, No Delay Envisaged
Apple's foldable iPhone is on track to ship in September despite rumors of a delayed launch, reports Chinese financial outlet Cailian Press. The outlet says it spoke with several people within Apple's supply chain, who indicated that the device's design was locked in some time ago and that the foldable is now in mass production.
Chinese Artist WINWIN Parts Ways With SM Entertainment And NCT
Chinese artist WINWIN has parted ways with SM Entertainment, terminating his exclusive contract after 10 years. He's currently focused on his acting activities in China.
Forestry scientists stay upbeat in face of federal turmoil
The Chinese word for crisis isn’t a combination of the symbols for “danger” and “opportunity” as some business strategy books once claimed. But if it did, it could be the
Alibaba’s A.I. Is a Hit, but Hard to Turn Into a Moneymaker
The Chinese company’s models have won over developers worldwide, but they are open source — so they can be used and modified freely.
Here's How the iPhone 18 Pro Max Will Compare to the iPhone 18 Pro
Apple is expected to unveil the iPhone 18 Pro and iPhone 18 Pro Max in September. The devices will have a lot in common, but the latest leak suggests that the Pro Max model will take an even bigger step forward in regards to battery life. According to new filings in a Chinese regulatory database, it appears that the iPhone 18 Pro Max will be equipped with a 5,567mAh battery in the U.S., while the iPhone 18 Pro will seemingly have a 4,288mAh battery.
iPhone 18 Pro Battery Capacities Revealed by Regulatory Filings
New Chinese regulatory certification filings appear to confirm the battery capacities of Apple's upcoming iPhone 18 Pro and iPhone 18 Pro Max models. According to new filings in China's C3 database, spotted by the leaker known as "Digital Chat Station" on Weibo, the iPhone 18 Pro is seemingly rated for 4,056mAh in China and 4,288mAh in the U.S., up modestly from the iPhone 17 Pro's 3,988mAh and 4,252mAh.
Party action game Hatsune Miku Starry Party announced for Switch 2, PC
Good Smile Company has announced party action game Hatsune Miku Starry Party. It will launch for Switch 2 and PC via Steam in 2027 with English, Japanese, Traditional Chinese, and Simplified Chines…
Chinese FM urges Swedish business community to deepen cooperation with China
The Wallenberg family and the Swedish business community should continue to play an active role in encouraging the Swedish government to pursue a rational and pragmatic policy towards China, helping the Swedish public gain a true understanding of China and fostering stronger public support for improving bilateral relations, Chinese Foreign Minister Wang Yi said on Saturday.
Chinese team’s brain-mimicking chip ‘up to 478 times faster than Nvidia GPU’
New chip performs data storage and computation in a single memory array, enabling real-time modelling of complex brain structures, team says.
From bamboo sticks to modern chemistry: A history of fireworks on display at the Science History Institute in Old City
“Flash! Bang! Boom! A History of Fireworks” tells the story of fireworks from the earliest Chinese inventions to today’s choreographed pyrotechnic displays.
Supreme Court declines to halt daily $800 fine for ex-Fox News reporter refusing to divulge sources
The Supreme Court on Thursday declined to intervene after a judge ordered an $800-a-day fine for Catherine Herridge, a former Fox News reporter, if she refuses to reveal her confidential source for stories about a Chinese American scientist who was investigated by the FBI but never charged.
Steam Machine alternative with Ryzen 9 available for under $850
Positioned as an alternative to the Steam Machine, the Aoostar GODY is a compact gaming PC now available outside its domestic Chinese market. The system pairs a powerful AMD processor with a dedicated graphics card.
Apple plans five new iPhones through 2027, eyes Chinese-made chips amid foldable push, reports say
Apple is planning five new iPhones by 2027 and is considering Chinese memory suppliers as it expands foldable production, reports say.
Bayer shifts US glyphosate business to Ruveon after seeking tariffs on Chinese imports
Bayer said on Wednesday it is consolidating its U.S. glyphosate business into its Ruveon unit, a day after it asked Washington to impose duties on Chinese imports of the chemical used in the company's weedkiller Roundup.
Great-grandson of Wong Kim Ark praises Supreme Court ruling affirming birthright citizenship
The great-grandson of Wong Kim Ark, the Chinese American at the center of the U.S. Supreme Court case that established the constitutional guarantee of birthright citizenship, called Tuesday’s ruling a victory for all Americans, saying it reaffirmed that precedent.
Fish named after Blackpink’s Jennie; China’s 6G smart city: 7 science highlights
From two Chinese scientists leaving the US to a desalination prototype, here are some highlights from SCMP’s recent science reporting.
Leaders of powerful S.F. Chinatown business group threaten to quit
Some leaders of San Francisco’s Chinese Chamber of Commerce are demanding that former president Donald Luu be permanently removed from the organization’s board.
Alleged iPhone 18 Pro Sim Tray Again Shows Dark Cherry Color
Apple's upcoming iPhone 18 Pro models are expected to introduce new color options, including a dark cherry color, and today we may have been given another peek at the rumored finish, courtesy of the Chinese leaker known as Ice Universe. Image shared by leaker Ice Universe In an image posted on Weibo, a SIM tray allegedly from the unreleased iPhone is shown in a dark cherry colour, which could also be described in this grainy example as burgundy, brownish, or purple.
Evidence points to potential new LCD screen for Nintendo Switch 2
The Nintendo Switch 2 screen could be getting a revision, based on the latest evidence. On a Chinese resale site, a listing recently appeared for a a new model of the system’s LCD panel. Sharp would apparently behind the updated screen. The current Nintendo Switch 2 features a panel from Innolux. This new screen has a different circuit, connector, and...
iPhone 18e Won't Get ProMotion Display, Says Leaker
Apple's upcoming iPhone 18e will have the same display refresh rate as the existing iPhone 17e, according to a prominent Chinese leaker. Discussing Apple's product plans for 2027 in a Weibo post, Digital Chat Station claimed that the next generation of Apple's low-cost iPhone will feature the same 60Hz low-temperature polycrystalline silicon (LTPS) TFT panel as the current model.
Coinbase's CEO outlined 5 strategies to keep AI spend low
One of his strategies was experimenting with using cheaper Chinese LLMs as default models.
Brookline party store, Chinese restaurant both close after decades in business
Golden Temple was open to Brookline residents for 66 years, while Party Favors was in business for 35 years.
Suspicious Steam Machine clone from China costs just $688, has a Ryzen 5 5500 with an RX 6750 GRE GPU
A Chinese listing shows a Steam Machine clone with an RX 6750 GRE for $688, but spec errors and pricing math make this listing look very suspicious.
New hollow-core fiber test pushes internet speeds to 1.2Tb/s
Chinese researchers achieved a new milestone in fiber-optic technology, achieving ultra-fast data transmission over long distances without signal repeaters.
iPhone 18 Pro and Foldable iPhone Tipped to Get Price Hikes Too
Apple's iPhone 18 Pro lineup and its first foldable iPhone will launch at higher prices than originally predicted this September, according to several known Chinese leakers.
Smile spacecraft reaches science orbit
The European-Chinese Smile mission reached its designated science orbit on June 20, 2026. The team is now embarking on a two-month campaign to commission the spacecraft, which involves switching on and ...
How should European scientists respond to the US AI kill switch?
Earlier in June, Europe’s worst fears of technological dependence were confirmed when the White House ordered the AI firm Anthropic to stop non-US citizens using its leading models. This kill-switch moment crystalised anxieties in Brussels that the continent, lagging the US on the creation of leading-edge AI models, is now a technological of vassal of Washington. The shock has specific implications for European scientists and universities. Some governments are now worried that with AI being integrated into labs, Donald Trump now has his finger hovering over an off switch for European science. “Having restrictions on this tool, it can have an impact on our own research,” said France’s research minister, Philippe Baptiste, at the VivaTech conference in Paris on June 18.Baptiste, himself a former academic, said that colleagues in mathematics had recently warned him they were now cut off from leading-edge US models, risking their work. “This model is not available anymore now because of the US restriction, and for the first time this had an impact on mathematics,” a field where large language models (LLMs) are making a significant contribution, said Baptiste. So, should European scientists avoid relying on US models in the future? Or would this be a self-harming overreaction? And how is AI being used in science, anyway? What happened?On June 12, it emerged that Washington, citing cybersecurity concerns, had ordered Anthropic to stop non-US citizens using two models: Claude Mythos 5, and Claude Fable 5, a version of Mythos but with guardrails to prevent abuse. Anthropic said Washington’s concerns were overblown. But forced to follow the order, yet with no way to check who was using the models, the company suddenly shut down access for everyone, US citizens included. There’s still no agreement on how to restore broad access. But last week, Bloomberg reported that select US companies, and the US government, still had access to Mythos despite the ban, but the EU’s cybersecurity agency Enisa had been shut out. Class division of researchersIn the longer term, access outside the US should be restored, said Marcel Salathé, co-director of the AI centre at the Federal Polytechnic School of Lausanne (EPFL), because a permanent restriction would be financially ruinous to US AI firms. “Even Trump will eventually budge to economic pressure,” he said.However, US AI firms might end up operating rather like banks, doing due diligence on users of their leading-edge AI models, he went on.European scientists are unlikely to fall foul of such checks, he said. But having a Chinese postgraduate in their lab, or doing a type of research the US disapproved of, could potentially result in access being denied. “It will create a sort of class division of researchers,” he said. More than frontier modelsHowever, successfully deploying AI in science is about far more than just having access to leading LLMs such as Mythos.Instead, many science-specific tools, most famously Alphafold, which predicts protein folding structures, require “far less” computing power to train than frontier models, well within the capabilities of European supercomputers, according to a recent analysis by the Arq Foundation, a Brussel-based AI think tank. Instead, tools such as Alphafold are possible because certain fields, like protein folding, weather prediction or astronomy, have large, clean, standardised datasets that can be used to train predictive models. Rather than compute, “data is the central constraint for AI for science,” the report says. For example, a less powerful physics model trained on CERN’s data “will be more valuable than the best model without certain data,” said Bengüsu Özcan, author of the report. European advantage?Europe could therefore steal a march by using its scientific data and infrastructure to create models US digital giants cannot. “They might actually match or go even beyond what these big [US] companies are doing,” said Özcan.Indeed, some European start-ups hope to create automated testing labs to create the kind of standardised data that could speed up the discovery of new materials. Materials scientists say there’s currently too little data to train models. AI scientistsHowever, even if the bottleneck for AI in science is often data, rather than compute, being at the mercy of the US for LLM access could still become a problem for European scientists. A new class of “AI scientists” based on leading LLMs is also emerging, Özcan’s report says.Unlike domain-specific tools like Alphafold, these try to automate day-to-day scientific work, by providing an overarching tool that coordinates specific models to synthesise existing literature, generate hypotheses or run analysis of data. The problem for Europe, however, is that these tools are sometimes based on US leading models. Google Deepmind’s AI Co-Scientist, for example, is built on Google’s Gemini LLM. Systematic failureThese scientific automation tools are still in their early stages, and still exhibit “systematic failures on scientific tasks,” Özcan’s report says. One of the problems is that the messy, day-to-day process of scientific discovery is largely not documented, meaning LLMs don’t have a good source of data to learn how scientists actually work. Meanwhile, some tasks, such as literature synthesis, don’t typically require access to leading edge models.However, the performance of AI scientific assistants could improve as companies such as Google pour resources into developing them. Rely on US“Unfortunately, for scientific assistants, there is not much we can do right now except rely on US frontier AI,” said Antoine Bosselut, a natural language processing expert based at EPFL. Chinese-built open models, which can run on local computers, lessening the risk of a shutdown, are touted as one alternative to US dependence. There’s also Mistral, once seen as Europe’s main AI hope, but the Paris-based company has seen its recent models fall behind in performance. But the Chinese alternatives are generally not as capable as US frontier AI models, said Bosselut, unless paired with fiddly, custom tools that allows them to act as independent agents. “Most scientists do not have the time,” he said. Don’t jump ship yetAlthough the kill switch moment is seen a warning shot for European scientists, it doesn’t mean labs should abandon US AI tools immediately. “I do not think the right response is simply to abandon US-based models and systems under the banner of sovereignty or independence,” said Mattias Björnmalm, secretary general of the Cesaer university association. “That would be an overreaction.”Related articlesEuropean sovereignty in AI requires ‘ugly trade-offs,’ say experts Robotic lab start-up makes case for €500M EU-funded materials testing facilityAI in science: is it useful? Instead, European researchers need to ask themselves whether they’re becoming dependent on technology that could be turned off in Washington, said Özcan. “They might not see this today, but they should really start asking this question,” she said. European researchers need a plan B, said Salathé. “I would recommend to every researcher, very proactively explore alternatives.”Own toolsIn addition, Björnmalm and others want European research institutions to develop their own scientific AI tools.Instead of signing AI deals with US digital giants, European universities should be using this money to create their own models, which may end up being superior for research, said Sabine Leonelli, an expert on the use of AI in science at the Technical University of Munich. “Universities in Europe seem to be happy to sign commercial contracts with US companies on the assumption [their AI tools] are better,” she said. But US frontier LLMs are typically opaque, and have been developed without independent scientific input, she said. “This is not good enough for science.”Last year, Swiss researchers released Apertus, an LLM designed to be completely transparent, from its development methods to its training data. The idea is that this makes scientific tools built on top of the model far more reproducible than with closed, commercial alternatives.“Europe needs more of this: serious capacity-building that gives researchers, universities and companies credible options,” said Björnmalm.
iPhone Ultra 2 Gets Green Light for Development, Says Leaker
Apple's second-generation foldable iPhone has officially been given the go-ahead for development, a prominent Chinese leaker claimed today. In a post on Weibo, the account known as Digital Chat Station said that the "iPhone Ultra 2 project" has been formally approved, and that the second book-style device will likely use the same display as the first-generation model expected later this year.
Anthropic accused Alibaba of exploiting its AI models
Anthropic said the Chinese company interacted with Claude millions of times through 25,000 fraudulent accounts in recent months.
Chinese scientists love Blackpink’s Jennie so much they named a fish after her
At less than 9mm, Jennie’s bumblebee goby is the smallest of its genus and the first to be found in China.
Science Decoupling Hurts Human Progress
Science magazine has reported that in May, several members of the U.S. Congress introduced the Securing Innovation and Research from Adversaries (SIRA) Act, a bill that would prohibit U.S. researchers from using federal funds to collaborate with 'blacklisted' Chinese entities. These include Chinese institutions and individuals. Joint research projects, co-authored papers, data sharing, personnel exchanges, and even the co-supervision of students would all be prohibited.
Chinese scientists create battery that works comfortably way above boiling point
The tiny ceramic-based lithium-ion battery can withstand heat and still operate at up to 150 degrees Celsius, making it a safer power source.
Opinion | The I Ching, Leibniz and AI: how old China-West links shaped modern science
The connection between Chinese civilisation and Western scientific thinking is far deeper and more intricate than commonly understood.
Chinese spaceplane releases object into orbit, according to commercial space surveillance
Chinese spaceplane releases object into orbit, according to commercial space surveillance China’s secretive spaceplane has released an object into orbit during its ongoing fourth mission, according to space surveillance firm LeoLabs.
China imposes trade curbs on dozens of U.S. firms in retaliation for Pentagon blacklist
The Pentagon earlier this month updated its so-called 1260H list by adding a slew of Chinese technology companies to a roster of entities it believes have aided Beijing's military.
The Long Arm of the Chinese Academy of Sciences
Far more than just a research institution, the Chinese Academy of Sciences is a key investor behind many of China’s leading technology companies.
Chinese sodium battery surprised scientists by matching key Tesla benchmarks
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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28 May 2026 | Embassy of the People’s Republic of China in ThailandA skilled and coordinated public health workforce is essential for protecting population health and responding to public health emergencies. Strengthening these capacities was the focus of a meeting held on 28 May 2026 at the Embassy of the People’s Republic of China in Thailand.Dr Ailan Li, WHO Representative to Thailand, together with Dr Watcharanan Tinnaitorn, Deputy Director of the Division of Public Health Emergency Management, Ministry of Public Health, and officials from WHO and the Ministry of Public Health, met with Counselor Zhang Xiaoxiao from the Economic & Commercial Counsellor's Office, Embassy of the People’s Republic of China in the Kingdom of Thailand to mark the launch of collaboration under the WHO Roadmap to strengthen the public health workforce.The initiative supports Thailand in strengthening its public health workforce across both health and non-health sectors. Public health emergencies require coordinated action across a wide range of professions and institutions, including health workers, border control officers, water safety specialists, communication professionals and local government authorities. Through the project, partners will work together to assess workforce capacities, strengthen competencies and promote coordination across sectors to support preparedness and response efforts.The discussion highlighted opportunities to enhance cross-country collaboration through knowledge exchange, communication activities and engagement at key project milestones, supporting workforce development and emergency preparedness efforts.Beyond its immediate objectives, the initiative also reflects Thailand’s contributions to public health at regional and global levels. The exchange highlighted the importance of sharing experiences, lessons learned and good practices through international cooperation to strengthen public health capacity and preparedness.WHO expressed appreciation to the Embassy of the People’s Republic of China in Thailand for supporting the project and recognizing the importance of investing in public health workforce development, preparedness and health security through partnership and multilateral cooperation. WHO also commended Thailand’s continued leadership and commitment to strengthening public health systems and emergency preparedness, including through cross-sector collaboration and workforce development.WHO remains committed to supporting Thailand and partners in advancing resilient and people-centred public health systems and strengthening preparedness for future health challengesAbout the EPHF Roadmap ProjectThailand is one of four countries selected in 2026 to initiate implementation of the Essential Public Health Functions (EPHF) Roadmap, alongside Maldives, Papua New Guinea and Timor-Leste. The initiative is funded by the China International Development Cooperation Agency (CIDCA). The project is led by Thailand’s Ministry of Public Health, with WHO Thailand serving as a co-implementing partner. Other partners include the Chinese Center for Disease Control and Prevention (China CDC), the International Association of National Public Health Institutes (IANPHI), the Global Network for Academic Public Health/Public Health Interprofessional Leadership Alliance (GNAPH/PHILA) and the World Federation of Public Health Associations (WFPHA).