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Yes, 'War's shocking episode 1 ending was inspired by Olivia Wilde's custody serving
Dominic West, Sienna Miller, and series creator George Kay weigh in on "War"s red carpet gone wrong.
Ten bucks says you’ll love this community science project
Today marks the first day of Rut Watch 2026 With another season of Deer Spy in the books thanks to community scientists like you, biologists are now on a mission to pinpoint the peak of the white-tailed deer breeding season in Maine. Every observation of deer breeding behavior and sign helps define the timing of the rut, and this project uses the power of community science to collect deer data all fall long. Hunters, hikers, and wildlife watchers - Rut Watch pairs well with any outdoor adventure you have planned this season. It’s a perfect excuse to slow down and connect with nature as you look for clues. So get outside, rack up that deer data and submit rut reports from now through December 1. The online form is science made simple: Location Date and time Breeding behavior observed Submit a Rut Report What to watch for Active Breeding The most obvious breeding behavior to observe is a buck mounting a doe, but that is a rare sight as it only lasts a moment. You are more likely to witness a buck “tending” a doe, following closely, chasing, nuzzling, or pawing at her rump until she is receptive. Sparring After bucks shed their velvet, sparring helps sort out who is who in the dominance hierarchy. Early season matches are often less intense than later season matches between similar sized bucks. Most sparring is complete by the time breeding begins. Rubs Don’t just look for deer, pay attention to the trees. Rubs are marks made by bucks when they rub their antlers on trees, removing bark and leaving their scent calling card in the process. Scrapes Look to the forest floor for this sign of breeding season behavior. Scrapes consist of two parts - a licking branch, and a patch of cleared earth. Bucks break a low branch around head height, then paw at the leaves below to expose the dirt. Covered in scent, a scrape tells does and other bucks, “I’m here!” Learn More More information What’s next for deer community science: Northern Maine Wintering Deer Survey Other active community science projects: Fish Tag Reporting Maine Golden Eagle Study Maine Amphibian & Reptile Atlas Project Maine Deer Management: Maine’s Big Game Management Plan Game Species Conservation & Management Report The Benefits of Hunting: Supporting Wildlife, Conservation, and Community Subscribe Share Leave a comment
Using comic books to get serious about science
Nuclear engineer-turned-librarian Jim Ottaviani found his niche as a writer of nonfiction comic books about scientific superheroes. Move over, Marvel. Step aside, DC Comics: Einstein, Pasteur, and more, have muscled their way into the best-seller stratosphere.
Arkansas, Kentucky each awarded $10M grants for maternal health efforts
A nonprofit founded by philanthropist Olivia Walton announced Thursday it is awarding $10 million grants to Arkansas and Kentucky to improve maternal health in rural communities.
GA Sec. State Nominee, NJ-7 & Aviation Politics
GA Sec. State GOP nominee Tim Fleming, the battle for NJ-7 and how aviation is shaping politics—and could be impacted by the midterms.
GA Sec. State Nominee, NJ-7 & Aviation Politics
GA Sec. State GOP nominee Tim Fleming, the battle for NJ-7 and how aviation is shaping politics—and could be impacted by the midterms.
GA Sec. State Nominee, NJ-7 & Aviation Politics
GA Sec. State GOP nominee Tim Fleming, the battle for NJ-7 and how aviation is shaping politics—and could be impacted by the midterms.
Committee led by Rep. James Comer seeks brain health study of naval aviators
The House Oversight Committee says the Navy isn’t doing enough to ensure it's protecting the long-term wellbeing of naval aviators.
Midtown Costco set to close, reopen as business center
Costco has committed to keeping the Midtown pharmacy open during the conversion.
Elta: Defy All Gods launches February 2, 2027, demo now available
“Adrenaline-fueled action platformer” Elta: Defy All Gods will launch for PlayStation 5, Xbox Series, and PC via Steam on February 2, 2027, publisher Focus Entertainment and developer A…
How Washington Funded the Politicization of Science
Over the last half-decade, the National Science Foundation (NSF) has spent hundreds of millions of dollars on projects designed to influence academic policies, both in the sciences and other disciplines. The aim was to foster a progressive conception of social justice in these fields. In pursuit of this end, the foundation earmarked nearly a million dollars for a project titled “Creating Inclusive Scientific Societies through Policies and Practices,” over a million for a project on “Faculty Online Learning Communities for Gender Equity,” and over $2 million to foster “racial equity focused departmental change.” Through a public records request, I’ve obtained the proposals and progress reports for dozens of NSF grants designed to promote social justice. Although funding for these grants was eventually halted by the Trump administration, the projects illustrate an important facet of recent higher-education policy. Many of the university policies that promised “social transformation” didn’t arise in a vacuum. They were actively encouraged by outside funders—often by the federal government itself. Subscribe Accreditation—the peer-review process which enables universities to receive federal grants and student loans—has recently become a policy battleground, with accreditors wielding significant power over both universities and academic disciplines. In 2020, when Oregon Health and Science University’s medical school issued an extensive diversity action plan—which promised “consequences” for employees who failed to support “DEI, anti-racism and social justice”—it specifically pointed to the Liaison Committee on Medical Education (LCME), the medical-school accrediting body, to justify the overhaul. The NSF actively promoted DEI-focused accreditation policies. The proposal for a $1.2 million program on promoting “community engagement” in STEM, which I obtained through a records request, notes that the Accreditation Board for Engineering and Technology was exploring changes to its criteria “that would incorporate JEDI [justice, equity, diversity, and inclusion].” The proposal promised to “support broader JEDI efforts in the general criteria for engineering.” Another grant funded a conference designed to “identify and share best practices and strategies to integrate IDEA principles in accreditation criteria”—referring to an acronym that stands for “inclusion, diversity, equity, and accessibility.” Scholarly societies have become another flashpoint in debates over higher education. Critics argue that many of these societies, which have the power to shape entire disciplines, have become increasingly politicized. Again, through its giving, the NSF played a role in promoting this politicization. In one million-dollar grant that received funding in 2024, a group of psychologists proposed a series of social-justice reforms to the Society for the Psychological Study of Social Issues. The proposal, which I obtained via a records request, asserts that “[r]edistributing resources (such as moving different people into leadership roles) is not enough” and that the society’s “governance structures do not yet reflect its stated values of diversity, equity, and inclusion.” Its solution: review and rework the society’s criteria for leadership development, academic awards, conferences, and publications. Adjusting review criteria informed by “intersectionality” designed to fight “epistemic exclusion” is an easy way to introduce de facto ideological litmus tests into the peer-review process. For many of the grants I obtained, such litmus tests seem to be the point. “Academic departments are racialized social systems that produce and sustain the byproducts of systemic racism,” a proposal for a $2.7 million project funded in 2024 asserts, promising to develop “departmentally-focused change efforts that cultivate values, assumptions, and behaviors that advance racial equity.” The University of Illinois Urbana Champaign’s million-dollar “I-ADVANCE” project, which effectively created a small DEI bureaucracy on campus, promised to Embed 28 ADVANCE faculty fellows in STEM departments” to amplify its equity goals. Another $1.2 million project promised to create “faculty online learning communities,” made up of scientists at universities around the country, that would eventually build department-level diversity action plans. “Ultimately,” the proposal asserts, perhaps more perceptively than its authors realized, “both organizational change and intersectionality frameworks deal with power.” Indeed, such grants confer a great deal of power to administrators and scholar-activists, who can even use the mere availability of funding as a tool to advance their causes. That history is worth remembering amid today’s debate over federal involvement in higher education: Washington has been shaping university priorities for years, including by financing efforts to instill progressive ideas about race, gender, and equity into academic institutions—and many of the policies those grants encouraged remain embedded within universities long after the federal money has stopped flowing. John D. Sailer is the director of higher education policy and a senior fellow at Manhattan Institute. Share
The Intangible Return: Rethinking the Value of Business Aviation
An aviation leader, student probes how to determine the value of business aviation
This Week in Sports Trivia: Oct. 1, 2026
How closely were you following the sports news this week? Find out and test your knowledge by taking The Athletic's weekly quiz.
Paducah Chamber to host Judge Executive forum; Baptist Health blood drive continues
The Paducah Chamber will host its Judge Executive Forum Thursday. The forum will be available to view on WPSD at Midday, or via stream. And Baptist Health will enter day
Three fixes to correctly price small-business debt in developing economies
Small businesses in developing economies pay far more to borrow than risk justifies. Three fixes could cut a Kenyan firm's cost of debt by over 8 points.
Gunvor publicly condemned Russia’s war but continued to do business with Russian energy firms, records show
Even as the trading giant publicly claimed to be winding down its Russia business, Gunvor privately acknowledged the deals to its bank, the Industrial and Commercial Bank of China, saying they complied with sanctions laws.
September Monthly Review: Health MCP Guy?
For all the time I spend talking about APIs and data exchange, this newsletter has had embarrassingly little interoperability of its own. It’s old-school SaaS, baby - UI or bust. Not all of that is my fault! Substack, for all its popularity, is (as mentioned before) really frustrating as my system of record. The primary user it optimizes towards is the reader, whose attention feeds the app, the Notes feed, and the recommendation network that Substack is actually selling. Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe They’re falling into the same trap that Medium once sprinted into, albeit at a much more glacial speed. Younger generations may not remember (or never knew) it, but Medium once lured publications like The Ringer and Signal v. Noise onto its platform, only to lose them as it rebuilt itself around a paywall and an algorithmic feed. Substack’s original pitch circa 2020 was the antidote (you own your list), but every new feed feature chips away at it. I get it: writers are generic supply in the eyes of the Substack product team. Generic supply follows demand, so the consistent pressure on the PMs is to generate demand, which leads to every product cycle going toward discovery (Notes, recommendations, the app, live video). The end result lackluster author tools (laggy and broken analytics are truly crippling) all despite the premium price point. The archive is where it crosses from authorial gripes to actual reader impact, though. Across Substack and LinkedIn, I’ve published 1,218 posts and nearly 900,000 words since 2018. Substack’s native search can see only the 464 posts that live on Substack, and even there it’s woefully inadequate at surfacing relevant content (even for the guy who wrote it)! Readers have the same problem, writ large. Ask the Archive Fixing search (for both my readers and my own use) turned out to be extremely non-trivial, unfortunately: There’s no public API for readers to access content RSS exists for new content notification, but it only carries the 20 most recent posts and cuts paid ones off at the preview The only Substack MCP is an admin tool for analytics The export exists for authors, but it’s painfully awkward and slow. So I built something to work around that: the Health API Guy MCP. It’s a private MCP server holding the full text of everything I’ve written across Substack and LinkedIn. Add it to Claude or ChatGPT as a connector and you can ask things like: It pairs keyword search (for acronyms and case names, of which we have many) with semantic search. Every post is also labeled by topic, form, and court case, so you can pull a lawsuit’s (or multiple cases’) entire docket across Substack and LinkedIn in one query: Hail, Healthapiguyhydra This is also a bit of me eating my own cooking. I’ve spent the year arguing that headless healthcare is arriving and that developers want primitives over abstractions. Last week in Hail, Benihydra, I watched Salesforce plug its platform into Claude and bet that the records underneath outlive whatever interface sits on top: Salesforce must believe that the Hydra’s immortal head is the records, permissions, and business logic (in that they will survive whatever happens to the interface). It felt a bit hypocritical to keep my own archive behind a Substack search bar. The archive is the body. Substack is one head, and now whatever tool you might use is another. Will the EHRs follow my lead? Probably not imminently, but one can hope! Why Founding Members Only The MCP is available to Founding Member subscribers. A few reasons: It costs money and time to run. Hosting, the database, Clerk usage and AI compute for search and labeling are significant operational costs (that increase with usage). Substack gives me no way to automate access. There’s no API to check whether someone is a paid subscriber, so every user is manual operations for now. It’s a beta. We’ll need to improve things and parts will break. I’d rather they break for a small group of dedicated readers who will tell me about it. The Founding tier deserved a real benefit. Until now it was mostly a generous tip. Now it comes with something. If you’re already a Founding Member, reply to this email with the address you’d like provisioned. If you’re not and want in, upgrade here. Larger teams (such as companies) can get access too: group subscriptions at the Founding tier come with the group discount. The admin for the subscription can reply with the list of addresses to provision. Get 20% off a group subscription Pricing Founding membership is now a flat $200 a year, replacing the old suggested $150 that readers could adjust. Existing Founding Members will have access grandfathered in at their previous rate. Month in Review Articles Published Make Networks Dumb Again (Sep 11): AI is making old analog networks cheaper to use and flooding them with machine traffic in the process. A plea for agent-native rails with the intelligence at the endpoints, and for Washington to drag them to ubiquity. Interoperability, Unbuttoned (Sep 29): Interoperability is a series of workflows in a trenchcoat, and this post finally takes the trenchcoat off. A color-coded map shows which provider workflows went digital, which are fragmented, and which still run on fax. Video Content Antitrust’s System of Record Problem (Sep 3): The FTC’s investigation into Epic prompted a ninety-minute webinar, now posted with chapters and a smoothed transcript. We get into why market definition, missing B2B share data, and the SSNIP test leave antitrust poorly suited to systems of record, plus why information blocking may be doing more than any pending lawsuit. The Information Exchange: Cerner Milking Edition (Sep 18): This was so fucking fun. Ryan Tucker, Ryan Brickner, Brad Thorson, and I try an Around the Horn format, complete with points, penalties, and a mute button. We debate whether Oracle Health is dead, who would actually buy Cerner (IBM enters the chat), p(Doom), and why the front desk still hands you a clipboard. Regulatory Ask Not What Your Network Can Do (Sep 23): CDC’s RFI on public health data intermediaries lists use cases already served, unevenly, by eCR, lab reporting, IZ Gateway, and syndromic surveillance. The real opportunity sits in one question about AI: a network that can handle the next emergency without another interface project. Court cases Particle v. Epic: The Naughty Schoolteacher (Sep 4): After a summer-long vigil, the answer on Epic’s early summary judgment bid is two paragraphs and a remedial assignment. Particle advances to the next grade, and market definition gets another year of discovery. The Epic Discovery Files (Sep 8): Texas’s motions to compel arrive with a 251-page appendix of requests, objections, and meet-and-confer letters with Cravath. Inside: Epic using generative AI for document review, denied interoperability requests in scope, and Noerr-Pennington raised against lobbying discovery. Epic v. Health Gorilla: “Working as Designed” (Sep 9): Epic wants nothing to do with the data breach MDL, and explaining why puts fresh discovery on the public docket. The spiciest allegation: Health Gorilla told GuardDog to scrub its law firm business from its website instead of cutting off access. Veeva v. Epic: Legal Bypass Surgery (Sep 15): Veeva asks the Wisconsin Supreme Court to skip the Court of Appeals, while law professors and three policy groups line up as amici. Meanwhile, Epic’s lawyers apologize for another round of citation errors, including a quote that never existed. Texas v. Epic: Behind the Black Bars (Sep 17): The court portal served up Epic’s unredacted filings, revealing a $5 million document review budget and the AI workflow behind it. Also inside: the 200-plus company names Texas wants searched, and one very expensive Zoom invitation. OpenEvidence v. Doximity: Consequences Will Follow (Sep 25): OpenEvidence tells the court it will not comply with a discovery order, and its own lawyers at Quinn Emanuel say they won’t defend the choice. Add years of Slack reported unrecoverable, and Rule 37 sanctions come into view. Health Tech Keeps Choosing Violence (Sep 28): Doximity moves to end OpenEvidence’s case, Epic asks Texas to show its work, and a sleepy Audacious Inquiry patent fight sprouts antitrust and information blocking counterclaims. The main event is a long-sealed Cognizant v. Infosys ruling that hints where system of record antitrust claims can survive. EHRs One Verb for Oracle Health (Sep 14): Oracle’s earnings call quantifies every data center to the decimal point, while Oracle Health gets a single verb: “accelerate.” Panning the few healthcare mentions turns up an agentic care management system, a research-to-care ledger play, and the question of whether healthcare gets Larry’s patience. Epic’s Forretress Under Siege (Sep 30): Judy Faulkner tells a panel Epic paused hundreds of projects to harden its software and calls it a “shame,” while a spokesperson insists the roadmap hasn’t changed. Project Glasswing, a Pokémon-branded QAN sprint, and a trove of Jodel grievances reconcile the two Epics and preview the Jevons paradox coming for all software. Industry Analysis Scanning for a Network (Sep 1): Scan.com raises $220M to build the imaging network labs never got, speedrunning Zocdoc’s consumer-to-B2B pivot. Its wedge to network density may be the most American one available: personal injury litigation. The Front Desk Wants the Damn Whole Building (Sep 16): Hello Patient buys Converse Health, pushing its AI front desk into referrals, chart work, and prior auth. The copilot categories keep blurring, and your distribution partner is still your final boss. Cross-industry Comparisons A Different Patchwork Quilt (Sep 10): Healthcare loves to envy open banking, but the US version has no mandate, a toll booth at Chase, and data quality problems of its own. The grass isn’t greener; it’s another American patchwork quilt, and perhaps a worse one. Hail, Benihydra (Sep 21): Salesforce brings its platform into Claude, Slack, and its own agent, inviting the interfaces that might replace it. Cut off one head and more grow back, so long as the records underneath stay put. Living on A Trade Secret Prayer (Sep 22): Six credit unions are suing Fiserv, the Epic of core banking, by claiming their own member records as trade secrets. Banking has no Cures Act, so its lawyers reach for legal alchemy that healthcare has already tried. Other News None this month External Media Nabla Accelerate NYC: I kicked off fall conference season at Nabla’s Accelerate event in New York, where Delphine Groll opened by asking the room to picture the company it wants to become and the one it doesn’t. I liked her framework of bureaucracy, fear, and ego as the blockers. I also love vendor conferences/events in general - different vibe than industry biggies. Healthcare 101 with Nikhil Krishnan: I briefly guest lectured Out-Of-Pocket’s Healthcare 101 class. Appreciated Nikhil’s takeaways cover whether AI doctors can query HIEs, why healthcare’s data-liberation rules beat most industries’, and the hi-res graphic is in the comments. HCN: Epic Probed by the FTC: I joined the HCN guys to talk through the FTC’s investigation into Epic. Cedric’s new hairdo was an unexpected plot twist. The episode also covers MFN drug pricing, healthcare M&A and Eli Lilly’s acquisition streak. Fall Conferences: At eHealth Exchange’s Annual Meeting in Austin on Oct 27, I’ll moderate a panel on the tensions between AI, HIEs, and timely patient access with Jean Ross (Primary Record), Therasa Bell (Kno2), Byron Crowe (Doctronic), and Michael Marchant (Freenome). Here’s the rest of my schedule if you want to meet up: CommonWell (Redwood Shores, CA): Oct 13-14 Will be participating in a fun Jeopardy event Open@Epic (Madison, WI): Oct 20-23 Will be enjoying Verona, Willy Street, and other local adventures eHealth Exchange and Sequoia Project (Austin, TX): Oct 27-29 Yeehaw HLTH (Vegas): Nov 15-18 Groundhog Day, Venetian Edition RSNA (Chicago): Nov 30-Dec 2 See me at “Governing AI in Breast Imaging: What Health Systems Are Actually Doing” Digital Health Counsel 2026 AI Summit (Seattle): December 2-3 Will likely be speaking to a bunch of lawyers about information blocking Posts I Liked ChatGPT’s Epic integration: game changer or nothing burger?: Joshua Liu, MD offers five thoughts on OpenAI’s Epic launch, starting from the point that it rides the same open APIs available to anyone. He argues read-only access leaves ordering to Art and the ambient startups, and asks why HCA is piloting it alongside Commure. He’s sorta a must-follow at this point - consistently excellent, thought-provoking takes. Epic, Lilly, and the Discovery pass: Seth Chaney reads Epic’s first major Discovery deal (with Eli Lilly), as well as its revised developer terms on commercial displays, as the pipe finally opening between EHRs and pharma. Life sciences and health continue to collide. Scott Rossignol on EHR payer platforms and ePA fees: Scott argues the top ambulatory EHR vendors are turning the prior auth mandate into a per-member-per-year toll on payers, for an API whose operating cost has nothing to do with covered lives. His fix is two lines of regulatory text: put the CRD/DTR/PAS certification criteria in the Base EHR definition, and bring payer-facing ePA connectivity under § 170.404’s cost-based fee rules. It’s a good solution. Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Unmasked: Guess the NBA player to quiz your sports trivia knowledge (September 30)
60 seconds. 5 clues. 1 player. Test your ball knowledge with today's Unmasked quiz.
A Lifelong Journey of Health, Perseverance, and Purpose: Shadia’s Story
Every year, Family Health and Fitness Day is celebrated on the last Saturday in September. It’s a day that encourages families to come together and build lifelong healthy habits. Ahead of Family Health and Fitness Day, I met with Special Olympics Bolivia athlete and Health Messenger Shadia Dueri to hear about her health journey, the lessons she has learned through Special Olympics Health programming, and how she’s using those experiences to support her community and fellow athletes today.
With $20M gift, Dartmouth Health to launch institute and at-home primary care program
Richard Levy donated $20 million to Dartmouth Health and the Geisel School of Medicine at Dartmouth for the establishment of at-home primary care and palliative services and a Family Caregiver Institute to offer resources and train new members of the caregiver force.
Capitalizing on the 'magic pill for health': Bernardston Senior Center distributes 45 Fitbits to encourage activity
The Bernardston Senior Center distributed 45 Fitbits to local seniors via a Mass COA grant to encourage fitness and healthy aging.
J.W. Simpson Library Slates Fall Programming
CRAFTSBURY — J.W. Simpson Memorial Library has new creative programs every other Thursday afternoon for all ages, a Charity and Sylvia book discussion at the Care Center, and an author
The best airlines for flying business class, ranked by passengers
The aviation rating company Skytrax surveyed travelers to determine the best business-class airlines.
PS5 Pro Shortage Hits Japan As Sony Limits Console Purchases To Active Playstation Users Ahead Of GTA 6
A lottery system has been introduced in an effort to counter shortages while alleviating scalper concerns ahead of GTA 6
Caviar launches ultra-luxury Black Edition iPhone 18 Pro and iPhone Duo with no cameras
Caviar launches camera-free custom iPhone 18 Pro and iPhone Duo models with aerospace-grade titanium bodies, luxury finishes, and limited production runs.
Silage science
Silage can be created from nearly any forage crop, but corn is often used because it is so energy-dense. Putting up silage can preserve forage quality via fermentation if it
The Streamers Tried To Conquer Labor Day…and Whiffed
(Welcome to my weekly streaming ratings report, the single best guide to what’s popular in streaming TV and what isn’t. I’m the Entertainment Strategy Guy, a former streaming executive who now analyzes business strategy in the entertainment industry. If you were forwarded this email, please subscribe to get these insights each week.) What? Another Streaming Ratings Report already? You betcha. Nielsen has moved up the release of their Streaming Ratings data by two weeks, which means I’ve got two extra issues to get out. But I love this change because it will make this report more timely and easier to publish regularly. This week—with the viewership data for the week of 31-Aug—we’ve got some huge, huge topics to discuss. On the film side, two theatrical films (The Mandalorian and Grogu on Disney+ and Scary Movie on Paramount+) contend with two non-Netflix straight-to-streaming films (Mayday on Apple TV and The Runner on Prime Video). The streamers went all in to win Labor Day weekend in America. And we have a bunch of TV shows to analyze, both new shows (Netflix’s The Gentleman, Hulu’s Chad Powers, and an Alix Earle reality show) and weekly shows like Reacher, Ted Lasso, House of the Dragon and Lioness. All that, plus nepotism in Hollywood, some eye-popping fantasy football stats, all the flops, bombs and misses, and a whole lot more. Let’s dive right in! (Reminder: The streaming ratings report focuses on the U.S. market and compiles data from Nielsen’s weekly top ten viewership ranks, Luminate’s Top Ten Data, JustWatch and Reelgood interest data, Samba TV household viewership, company datecdotes, Netflix hours viewed data, Google Trends, and IMDb to determine the most popular content. While most data points are current, Nielsen’s data covers the weeks of August 31st to September 6th, 2026. You can find a link to my terminology here.) Subscribe Film - A Slew of Labor Day Disappointments? A lot of streamers released big new films this week, why? My theory is that the streamers know that four-day weekends can propel streaming films to glory. But if you’ve been reading more over the last two years, you know that big holiday weekends aren’t driving big viewership numbers the way they did post-Covid. And interestingly enough, Netflix didn’t put out a big new film this week. But four other streamers did, trying to take advantage of the holiday with some (not cheap) swings, including… The Mandalorian and Grogu on Disney+ (a Star Wars film that cost $165 million and made $177 million at the US domestic box office) Mayday on Apple TV (rumored $100 million budget, no theatrical release) The Runner on Prime Video (at least a $40 million budget, but likely $50 to $80 million, no theatrical release). Scary Movie on Paramount+ ($30 million budget, made $108 million domestically). (Paramount+ also released a made-for-streaming film based on the Thundermans IP, and I’ll discuss that later.) So…how’d they do? The Mandalorian and Grogu Leads The Way (But That Isn’t Enough) Let’s start with The Mandalorian and Grogu (which I’ll abbreviate to Mando for most of this article). We’re just getting started with this issue, but the rest is for paid subscribers of the Entertainment Strategy Guy, so if you’d like to find out… How Mando, Mayday, The Runner and Scary Movie performed on streaming... How the powerhouse weekly released shows (Reacher, Ted Lasso and Lioness) have accumulate a LOT of viewership… How House of the Dragon finished its run… The latest Netflix show to have a sophomore slump… Whether top creators can drive viewers to their shows… Nepotism in Hollywood and the music business... All the flops, bombs and misses for the week… And more… ...please subscribe! We can only keep doing this great work with your support. Coming Soon! Since Nielsen has accelerated their streaming data release schedule, I’ve got a lot of Streaming Ratings Reports coming your way! Next issue, I’ll be looking at the second season of Peacock’s The Paper, the latest season of Hulu’s The Secret Lives of Mormon Wives, and a very, very expensive Daily Wire fantasy series that’s now on Prime Video. Plus Crew Girl and Dang! on Netflix, a new Tyler Perry film, and one of the biggest bombs of the summer, Supergirl. In the next two issues, I’ll take a look at the return of the NFL to streaming, Toy Story 5 on Disney+, Backrooms on HBO Max, and The Breadwinner on Netflix. On the TV side, we’ve got Netflix’s Monster: The Lizzie Borden Story, Dancing with the Stars on Disney+, Apple TV’s Slow Horses, a Reacher spinoff on Prime Video, and Paramount+’s MobLand, a Woody Harrelson and Matthew McConaughey comedy on Apple TV, a sequel to a Cosby Show spinoff on Netflix, The Great British Baking Show, and the Unabomber film. And while doing all that, I want to take a look at adult animated shows, Ride or Die’s cancellation, and Netflix’s summer films. So much great stuff! Long term, two bits of comic book news. The X-Men cast has been announced, and go ahead and color me bull-ish, if not very, very bull-ish on this bit of comic book IP. In weirder news, HBO Max ordered a “true crime” show by Jimmy Olsen about Gorilla Grodd being falsely convicted of murder. I mean, what? I don’t know, let’s see what happens.
Exercise helps Via Christi cancer patients take charge of their health
The American Cancer Society says regular exercise can improve a patient’s quality of life, give them more energy, and help them better deal with the side effects of treatment.
Oil prices fall on signs Middle East crude flows recovering
Oil prices declined as Saudi Arabia resumed crude exports via the East-West pipeline, easing concerns over supply disruptions amid the US-Israeli war on Iran.
Halo's Former Franchise Creative Director Sees 3 Possible Paths for Activision's Halo
Frank O'Connor, Halo's Franchise Creative Director for nearly 20 years at 343 Industries/Halo Studios, has weighed in on Halo's future at Activision, suggesting three viable paths forward for Xbox's former biggest franchise.
Tom Cruise Bloviates His Way Through the Aggressively Unfunny Digger
Alejandro G. Iñárritu's latest film has a million moving parks and nothing to say
Innovative country experiences show how primary health care can accelerate health system transformation in the Americas
Barbados, Bolivia, the Dominican Republic and Guyana shared experiences on strengthening Primary Health Care through targeted actions in health workforce, services organization and system’s planning during the 63rd PAHO Directing Council.Washington, D.C., 29 September, 2026 (PAHO) – Innovative approaches to transform health systems based on primary health care (PHC) were highlighted today during a briefing session at the 63rd Directing Council of the Pan American Health Organization (PAHO).
ABC News' Will Reeve reveals testicular cancer diagnosis, chemotherapy treatment
ABC News' Will Reeve is seen on the set of 'Good Morning America' on June 9, 2026, on ABC. (Paula Lobo/ABC via Getty Images)
How corporate services help small businesses stay secure
Discover how corporate services help Ozark small businesses manage cash cycles, improve security, and save time via Table Rock Community Bank.
Jalen Green Reveals Offseason Guidance Given via Phoenix Suns Legend
Tasked with a new playmaking role, the former second-overall pick refined his pacing and court vision under two-time MVP Steve Nash to spark a potential All-Star leap.
The Value Of Basic Science Celebrated With The 2026 “Golden Goose” Awards
The 2026 Golden Goose Awards, an honor spotlighting obscure, often trivial sounding basic research that ultimately yields significant social benefits have been announced.
BVB players continue to shine on the international stage
Daniel Svensson has long since established himself as a full-back in the Swedish national team. On Monday evening, he once again played the full 90 minutes for the Scandinavians in their second UEFA N...
Monster Hunter Outlanders launches October 29
Free-to-play open-world survival game Monster Hunter Outlanders will launch for iOS via App Store and Android via Google Play on October 29, TiMi Studio Group and Capcom announced. In mainland Chin…
Former Five Year Yankees Utility Player Announces Retirement
Former Yankees utility player Tyler Wade announced his retirement from professional baseball this afternoon in a post on social media via his Instagram. Wade (age 32) spent nine years in the big leagues, making his Major League debut in 2017 for the New York Yankees and appearing in 30 games. Wade was drafted by the […] The post Former Five Year Yankees Utility Player Announces Retirement appeared first on HEAVY.
Ranking Member Markey: SBA Administrator Loeffler, Trump Administration are Refusing to Answer to America’s 36+ Million Small Businesses and Workers, Leaving Main Street Behind
Loeffler canceled her scheduled Sept. 30 appearance before the Senate Small Business Committee, has not appeared before SBC in more than a year (Washington, September 28) – Ranking Member Edward J. Markey (D-Mass.) today released the following statement after Small Business Administration (SBA) Administrator Kelly Loeffler canceled her scheduled Wednesday appearance before the Small Business and Entrepreneurship Committee. Administrator Loeffler has not appeared before the committee in more than a year and has consistently refused to provide substantial answers to committee members in person, in writing, or via requested briefings. In June, Ranking Member Markey led every Democratic member of the committee in calling on Administrator Loeffler to appear before the committee to answer for the Trump administration’s cruel attacks on American small businesses, entrepreneurs, and workers. The Democratic lawmakers still have not received a response from Administrator Loeffler. “It is unacceptable that Administrator Loeffler chose to cancel her appearance before the Senate Small Business and Entrepreneurship Committee. The Trump administration is once again ignoring the more than 36 million American small businesses, entrepreneurs, and workers who drive our economy and enrich our communities by refusing to answer questions about this administration’s reckless economic policies. It has been more than a year since Administrator Loeffler has appeared before our committee and answered questions from both Democrats and Republicans. Since then, the Trump administration’s attacks on Main Street have only worsened. “Small businesses are facing record high gas and diesel prices, skyrocketing healthcare costs, and never-ending uncertainty from Trump’s trade war with the world. Trump has terrorized Main Streets across the country with violent ICE raids, destroying families, communities, and local economies. Meanwhile, Administrator Loeffler and the Trump SBA have been in a Witness Protection Program, ignoring the Pain on Main Street that they have created. They have chosen to make drastic cuts to SBA funding and essential, bipartisan programs, including the closure of the SBA office in Springfield and removal of the SBA office from Boston; directly attacked immigrant small business owners and destroyed the promise of the American Dream; and proposed shortsighted small business size rules that would benefit billion-dollar businesses over actual small businesses. “It’s clear that Administrator Loeffler, President Trump, and their CEO billionaire buddies want to turn the Small Business Administration into the Big Business Administration, tear down our economy, and abandon Main Street. If that is indeed this administration’s goal, Administrator Loeffler must answer to the millions of small businesses, workers, and families in Massachusetts and across the country that this administration is leaving behind.” ###
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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AI Actress Tilly Norwood Marks One Year Since Zurich Debut With Talk of Tom Holland, Olivia Colman
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Olivia Rodrigo, Charlie Puth, Sombr, Raye and Katseye set for 2026 iHeartRadio Jingle Ball tour
iHeartRadio is loading its 2026 holiday tour with some starry acts, including Olivia Rodrigo, Charlie Puth and the Jonas Brothers.
Olivia Rodrigo, Charlie Puth, Sombr, Raye and Katseye set for 2026 iHeartRadio Jingle Ball tour
iHeartRadio is loading its 2026 holiday tour with some starry acts, including Olivia Rodrigo, Charlie Puth and the Jonas Brothers | WBBM Newsradio 780 AM & 105.9 FM
Olivia Rodrigo, Charlie Puth, Sombr, Raye and Katseye set for 2026 iHeartRadio Jingle Ball tour
iHeartRadio is loading its 2026 holiday tour with some starry acts, including Olivia Rodrigo, Charlie Puth and the Jonas Brothers | WBEN
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UFC Champion Justin Gaethje Provides Latest Health Update
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St. Louis Cardinals vs Pittsburgh Pirates Game Discussion Wednesday
The St. Louis Cardinals will do battle with the Bucs again at PNC Park Wednesday night. Matthew Liberatore is the scheduled starter for the Cardinals Wednesday night while the Pirates have announced RHP Lake Bachar as their starter. First pitch is scheduled for 5:40pm central time and the game broadcast will be available via Cardinals.tv.