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Coastal forces shape building sciences practice
When Built Environments relocated to Wilmington, the firm’s partners weren’t looking for the lazy tranquility one hopes for when on vacation. Instead, they sought sultry heat. They wanted to understand whipping coastal winds and punishing precipitation – the kind that tropical storms produce. That’s because how materials degrade can reveal a lot about how they can be improved. “We specifically chose the Wilmington market because it does fall within Climate Zone 3A, which is a coastal warm-humid climate,” said Jarrett Davis, who joined Built Environments in 2023 to lead the company’s building science practice. “There’s not a lot of product research in that climate zone, but there are a lot of structures here that get weatherized pretty severely.” Built Environments has provided building science, material testing and code compliance consulting for 25 years, ever since principal materials scientist Steve Doggett founded the company in Minnesota. “There are very few manufacturers that understand fully how their own materials and products work, whereas we know their shortfalls and their benefits out in the real world on jobsites,” Doggett said. “That’s why the original Built Environments was formed, to make buildings better.” He said the 15-employee company is just as comfortable on a jobsite, retrofitting a high-end beachside property, for example, as it is recreating some of the coast’s most intense weather conditions in the great indoors. The company operates an A2LA-accredited ISO/IEC 17025 mechanical testing laboratory on Wright Street. The year-old facility has expanded Built Environments’ in-house capabilities, Doggett said. “We’re able to simulate that hurricane wind (and) rain and perform structural and impact testing on wall assemblies, roof assemblies and glazing assemblies,” he said. “There are certain requirements that those windows and doors need to meet as far as wind ratings and pressure ratings and things of that nature.” Standard Glass Co.-Glass Depots, of Wilmington, is currently testing a new glazing system using Built Environments’ stress testing, the partners said. One method involves what’s called a “large missile cannon.” “We take 8-foot two-by-fours, and we shoot them at assemblies, so they have to withstand that impact,” Davis said. “It’s pretty cool to see, I’m not going to lie.” In many cases, the lab can run a full, wall-scale test of a product in a matter of weeks or months, whereas “it might take midrange manufacturers years,” Doggett said. “We’re nimble. We can cut that time in half.” The lab also develops intellectual property. Doggett, for example, shares a patent with Sustant LLC, of Minnesota, on a fastener patch to increase the air and water tightness within building envelopes. “We have too many ideas and not enough time,” he said. But the partners noted that they or their fellow principals – of which the company has four total, including a principal engineer and a principal codes and standards expert – could be anywhere on a given day, including in the courtroom providing expert testimony in contentious insurance cases. “Let’s say there is a fire on a structure,” Davis said. “We can analyze all the specific materials within that assembly – an exterior wall or something like that – because there are loads that require certain heat release. And so, we can measure each one of those materials, if need be, to say if this was likely or not a code-approved assembly.” Despite what can be inferred in a lab, the partners said nothing beats learning from how materials change over time under real-world strain. Take, for instance, the curious case of the creaking condo. “We recently had a customer that came to us trying to assess a sound issue of a roof. It was making noises that no one could explain or account for. How do you tackle something like that?” Doggett asked rhetorically. “There’s really no generally agreed-upon methodologies.” The problem turned out to be a faulty installation of a commercial roof system. “The building in this particular case was not local,” he said. “In the initial installation, the commercial roofing contractor installed the wrong fasteners in the wrong locations into the deck, and essentially the solar radiation was causing the building to move quite substantially early in the morning when the sun initially hit that assembly after a quite cool evening, causing the threads on the fasteners to kind of jump within the material, within the metal.” Built Environments designed an effective repair methodology that was within budget, the partners said. “We get the bizarre,” Doggett said. “I will say that’s something that has stayed the same over 25 years.” The partners said they are hiring, and that Cape Fear Community College is one of their main recruiting grounds. Davis and Doggett look for talented people who can understand traditional methodologies yet are open to on-the-job training and new understandings, they said. After all, it’s not just weather that can ruin a building. “My favorite saying is,” Davis said, “‘What are the eight most expensive words in construction? That’s how my daddy used to do it.’”
Coastal forces shape building sciences practice
When Built Environments relocated to Wilmington, the firm’s partners weren’t looking for the lazy tranquility one hopes for when on vacation. Instead, they sought sultry heat. They wanted to understand whipping coastal winds and punishing precipitation – the kind that tropical storms produce. That’s because how materials degrade can reveal a lot about how they can be improved. “We specifically chose the Wilmington market because it does fall within Climate Zone 3A, which is a coastal warm-humid climate,” said Jarrett Davis, who joined Built Environments in 2023 to lead the company’s building science practice. “There’s not a lot of product research in that climate zone, but there are a lot of structures here that get weatherized pretty severely.” Built Environments has provided building science, material testing and code compliance consulting for 25 years, ever since principal materials scientist Steve Doggett founded the company in Minnesota. “There are very few manufacturers that understand fully how their own materials and products work, whereas we know their shortfalls and their benefits out in the real world on jobsites,” Doggett said. “That’s why the original Built Environments was formed, to make buildings better.” He said the 15-employee company is just as comfortable on a jobsite, retrofitting a high-end beachside property, for example, as it is recreating some of the coast’s most intense weather conditions in the great indoors. The company operates an A2LA-accredited ISO/IEC 17025 mechanical testing laboratory on Wright Street. The year-old facility has expanded Built Environments’ in-house capabilities, Doggett said. “We’re able to simulate that hurricane wind (and) rain and perform structural and impact testing on wall assemblies, roof assemblies and glazing assemblies,” he said. “There are certain requirements that those windows and doors need to meet as far as wind ratings and pressure ratings and things of that nature.” Standard Glass Co.-Glass Depots, of Wilmington, is currently testing a new glazing system using Built Environments’ stress testing, the partners said. One method involves what’s called a “large missile cannon.” “We take 8-foot two-by-fours, and we shoot them at assemblies, so they have to withstand that impact,” Davis said. “It’s pretty cool to see, I’m not going to lie.” In many cases, the lab can run a full, wall-scale test of a product in a matter of weeks or months, whereas “it might take midrange manufacturers years,” Doggett said. “We’re nimble. We can cut that time in half.” The lab also develops intellectual property. Doggett, for example, shares a patent with Sustant LLC, of Minnesota, on a fastener patch to increase the air and water tightness within building envelopes. “We have too many ideas and not enough time,” he said. But the partners noted that they or their fellow principals – of which the company has four total, including a principal engineer and a principal codes and standards expert – could be anywhere on a given day, including in the courtroom providing expert testimony in contentious insurance cases. “Let’s say there is a fire on a structure,” Davis said. “We can analyze all the specific materials within that assembly – an exterior wall or something like that – because there are loads that require certain heat release. And so, we can measure each one of those materials, if need be, to say if this was likely or not a code-approved assembly.” Despite what can be inferred in a lab, the partners said nothing beats learning from how materials change over time under real-world strain. Take, for instance, the curious case of the creaking condo. “We recently had a customer that came to us trying to assess a sound issue of a roof. It was making noises that no one could explain or account for. How do you tackle something like that?” Doggett asked rhetorically. “There’s really no generally agreed-upon methodologies.” The problem turned out to be a faulty installation of a commercial roof system. “The building in this particular case was not local,” he said. “In the initial installation, the commercial roofing contractor installed the wrong fasteners in the wrong locations into the deck, and essentially the solar radiation was causing the building to move quite substantially early in the morning when the sun initially hit that assembly after a quite cool evening, causing the threads on the fasteners to kind of jump within the material, within the metal.” Built Environments designed an effective repair methodology that was within budget, the partners said. “We get the bizarre,” Doggett said. “I will say that’s something that has stayed the same over 25 years.” The partners said they are hiring, and that Cape Fear Community College is one of their main recruiting grounds. Davis and Doggett look for talented people who can understand traditional methodologies yet are open to on-the-job training and new understandings, they said. After all, it’s not just weather that can ruin a building. “My favorite saying is,” Davis said, “‘What are the eight most expensive words in construction? That’s how my daddy used to do it.’”
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Good science requires much more than evidence
Empiricists believe that scientific theories are true only if they make correct empirical predictions: if we can't verify these predictions, then there is no reason to expect that they tell us anything about reality. However, Professor of Philosophy at King's College David Kyle Johnson argues that this is mistaken. In response to Bas van Fraassen, who has written on this subject for the IAI, he argues that we have many reasons for believing a theory to be true, such as it being parsimonious and having large scope — qualities which have been used throughout the history of science as criteria for judging theories. In 2024, Princeton philosopher Bas van Fraassen wrote a short article for IAI News entitled “Science Does not Describe Reality: The Limits and Benefits of Explanation.” At the time, I was working on two projects (a science book and a Great Course) that, when completed, would (among other things) defend science’s ability to describe reality. I wanted to write a response to van Fraassen, but the projects demanded too much of my attention. But now that those projects are complete, I am in a position to explain the objections to van Fraassen’s thesis. Summarizing van Fraassen’s argumentIn a nutshell, his argument is this: What scientists do is make predictions based on theories and then invite others to test to see whether those predictions are borne out. “If theory T is right, result R should happen in experimental condition C.” Many think that running an experiment that shows that R happens in condition C is proof that theory T is true (and should be believed). But, van Fraassen argues, that R happened in condition C is only a reason to think that R happens in condition C. That’s the only observable, or empirical, result we can actually see, so that is all that we are really justified in believing. (The underlying theory that made that prediction still may or may not be true.) That is why he calls those who accept his position “empiricists.”Before I explain what is wrong with this position, let me explain what it gets right. What van Fraassen Gets RightFirst, a theory correctly predicting the results of an experiment is not, strictly speaking, “proof” that the theory is correct. The basic line of reasoning is this:If the theory T is true, result R should happen. Result R did happen. Thus, theory T is true.In other words:“If T then R. R. Thus, T.”This is a deductively invalid, fallacious mode of reasoning, called “affirming the consequent.” Those premises do not guarantee that the conclusion follows. “If I am in Pennsylvania, then I am in the USA. I am in the USA. Thus, I am in Pennsylvania.” Clearly that argument doesn’t guarantee its conclusion; neither does the above argument.However, science is not a deductive method of reasoning; it is an inductive one. And inductive arguments merely try to raise the probability of their conclusion, not “prove” them for certain. Thus, the fact that an experimental result doesn’t prove a theory is true is irrelevant; it’s not supposed to. That is not what scientific reasoning is about.___If the hypothesis that something exists clearly provides the best explanation for what we can observe, then the belief that it exists is what is rational.___Second, it’s also true that a single experimental result doesn’t provide enough justification to believe that a theory is true. Scientists do not come to a consensus about whether a theory is true by looking at a single experiment; they look at all the evidence to determine where the preponderance of evidence points. The mere fact that I am in the USA raises the probability that I am in Pennsylvania, but not nearly enough to conclude that I am in Pennsylvania. However, if I am also regularly encountering people wearing Eagles and Phillies hats and seeing advertisements for Founding Father tours, I probably am. In the same way, a theory successfully predicting the outcome of one experiment is not enough to conclude that it is true; but if a theory makes a wide variety of predictions that are all vindicated by multiple experiments, performed by many different groups and people, all actively trying to prove the theory false (which is what good scientific experiments are designed to do)—that is a good reason to conclude that the theory is true. In other words, if you repeatedly try to prove something false but can’t, that is a very good indication that it isn’t. The problem of underdeterminationIn reply, those whom van Fraassen calls “empiricists” often point to the “problem of underdetermination.” For any given theory that makes successful predictions about what happens in experimental conditions, there are countless other possible theories that make exactly the same predictions—and since they do, the experimental evidence in question is just as much reason to accept any of those theories as it is to accept our original one. Thus, the argument goes, we have no way of knowing whether our original theory is true, or one of the other “predictively equivalent” theories is true. SUGGESTED VIEWING How Occam's Razor changed the world With Johnjoe McFadden As an example of underdetermination, philosophers often offer this example. The evidence of fossils seems to provide reason to conclude that the universe is quite old; ancient fossils are what the “ancient universe” hypothesis predicts. But it’s also possible that God created an ancient-looking universe 200 years ago, complete with a “fake” fossil record for us to find, to make it look old. The existence of fossils is what that theory predicts too. So, the argument goes, the fossil record can’t be used as evidence that the universe is ancient; the fossil record supports the “200-year-old ancient-looking universe” theory just as much. The problem of underdetermination points out that, for any theory with supporting evidence, we could invent another completely different theory that predicts exactly the same evidence, and thus undermine that evidence’s ability to support the original theory.But this “argument from underdetermination” betrays a fundamental misunderstanding of what scientific reasoning is and how it works. To explain, let me use another rather strange (but very real and commonly discussed) philosophical thought experiment called “The Grue Problem.” The “Grue” ProblemSuppose I want to know what color emeralds are, so I observe a few, see that they all appear green, and form the theory that “all emeralds are green.” I thus predict that the next 100 emeralds I find will also appear to be green. And let’s say that happens, and so I thus conclude that my theory that all emeralds are green is true. Now, one might rightly point out that I don’t know for sure that all emeralds are green—I have not seen them all. Maybe some I haven’t found yet are blue. Fair enough. After all, we used to think that all swans were white, until we found some black ones. But let’s say that I go on a quest and collect every emerald in the universe—and, for the sake of the argument, let’s say I can do this, and can even know that I have every one of them. So, I collect them all, look at them all, and verify that they all appear green. Can’t I now rightly conclude that all emeralds are green?Inspired by the problem of underdetermination, a friend might argue that I cannot.Sure, they all appear green now—but there could be another kind of color called “grue.” Something is grue if it is green up to a certain point in time, but then spontaneously turns blue. And there could be an infinite number of “shades” of grue. Something that is one shade of grue will turn blue at noon today, but something that is another shade of grue will turn blue at noon tomorrow, etc. So yes, the emeralds appear green now; and since they haven’t turned blue yet, they are not some “past” shade of grue. But they might be some “future” shade of grue (e.g., they may turn blue at noon tomorrow). And since all future shades of grue are consistent with “being green up to this point in time,” the evidence you have is completely consistent with the notion that all emeralds are some future shade of grue, rather than green. Indeed, that they would appear green until now is what the “some future shade of grue” hypothesis predicts. So, we have just as much reason to conclude that all emeralds are some shade of grue as we do to conclude that they are green.You’re probably thinking “It’s not equally possible that the emeralds are grue; they are obviously green.” You are right! But explaining why your instinctive reaction to my friend’s argument is correct will help inform why van Fraassen’s “empiricist” is wrong and science actually does describe reality.The main mistake my friend makes is in thinking that the “empirical evidence” (of all the emeralds appearing green) is (or even should be) all I am using to draw the conclusion that all emeralds are green. It is not. I am also considering known facts about how colors typically work; things don’t usually change color, and when they do, they don’t do so suddenly, without cause, and all at once. So, even though the simple evidence of the emeralds all appearing green up to this point is consistent with them being some future shade of grue—that is even what the grue hypothesis “predicts”—it is still exceedingly unlikely that they are. The hypothesis that they are green is much more likely. Understanding science refutes the problem of underdetermination The misunderstanding about science that the “empiricist” pointing to “the problem of underdetermination” makes is similar to the one that my friend made. Science is not just about considering experimental evidence; in fact, it’s not even just about considering empirical evidence. As Ernan McMullin and many other philosophers of science have pointed out, the inference that makes science is “inference to the best explanation” (sometimes called “abduction” or “retroduction” by McMullin). While, depending on the circumstances, scientists use many different kinds of reasoning, science as a whole is, simply put, the process of considering multiple competing explanations and comparing them to certain criteria—explanatory criteria (the kinds of things explanations must be and do, by definition, to be a good explanation)—to see which explanation is the best.And these criteria do not deal only with empirical results. Yes, successful predictions raise the probability of a hypothesis, but it’s also the case that the more new assumptions a theory makes, the less likely it is to be true; every new assumption presents an opportunity for the theory to be false. (The fewer assumptions a theory makes, the simpler or “more parsimonious” it is said to be.) Likewise, the more existing evidence a theory contradicts, the less likely it is, because in order for a theory to be true, every piece of evidence it contradicts has to be somehow faulty. (The fewer established theories a new theory contradicts, the more “conservative” it is said to be.) And, obviously, the more something explains, the better explanation it is. (This is called having “scope.”) If a theory raises unanswerable questions, it’s not expanding our understanding, and thus is not wide-scoping. Scientists consider all these things when deciding which theory to accept, because the theory that adheres best to these explanatory criteria is most likely to be true.___the mere fact that a theory’s predictive success is why it “sticks around” or “becomes accepted” in the scientific community is not a reason to be skeptical about its truth.___The reason the grue hypothesis is no good is because it invents an entirely new kind of color—not just a new shade, but an entirely different category of color (a different way colors work)—and thus is not parsimonious. It raises unanswerable questions about how and why emeralds would just spontaneously change from green to blue (and thus does not have wide scope). And it contradicts what is already well established about how color works (and thus is unconservative).The theories that the problem of underdetermination points to do the same thing. Yes, the theory that God created an “ancient-looking universe” (complete with an ancient-looking fossil record) two hundred years ago is also consistent with the empirical evidence (of a fossil record) that presently exists; but that theory is monumentally unparsimonious (it requires many extra assumptions about infinite entities) and not wide-scoping (it raises unanswerable questions about why God would do such a thing). So, I can rationally conclude that it is false.Indeed, the history of science includes many examples of theories that were rejected because they lacked parsimony and/or scope, even before their falsity (and the truth of their competing theory) was confirmed by observation. As I point out in my book, geocentrism was rejected by the scientific community because it lacked parsimony, almost 200 years before the observation of parallax confirmed that the Earth moves around the sun. And the continuum theory of matter was completely rejected by 1860, because it couldn’t explain chemical reactions or organize matter into a periodic table, even though the experiments that eventually confirmed atomic theory weren’t even proposed until the 1870s. Solving the best of a bad lot problemIn response, the “empiricists” are likely to object, this time pointing to the “best of a bad lot” problem. “We have no reason to conclude that an explanation that has been shown to be better than others is true because we have no guarantee that the true theory was among those that we were considering.” If you have a “lot” (a collection) of poor explanations, even the best one is not true.The responses to this problem, however, are numerous. Peter Lipton argues that the set of hypotheses that scientists consider are not just randomly selected and thus unlikely to contain a theory that is true; they use existing knowledge to home in on what is most likely to be true. A doctor trying to explain abdominal pain is not going to bother wondering whether demons are causing it; they are going to stick with things like appendicitis and kidney stones, because they are most likely. Further, despite its name, inference to the best explanation is not just the process of comparing hypotheses and accepting the best one; we also want one that is a good explanation in its own right. If it’s not, we are going to keep looking until we find an explanation that is. And while that process does not guarantee that we will come across the exact truth, it’s very likely that the theory that emerges as the best will be at least approximately true, and thus we will be justified in believing it. And lastly, as I point out in my book, although many theories not based in scientific evidence (like geocentrism and continuum theory) have been completely overturned, science almost always progresses by the refinement of scientifically established theories—not their replacement. (Although our sun is not the center of the universe, heliocentrism was our first step in understanding the Earth’s true place in the universe.) So even if a theory we accept today may not be completely right, accepting it is a step on the journey toward the complete truth. The example of atomic theoryNow, it’s worth pointing out that most empiricists are not skeptical of all scientific theories; they are only skeptical of the ones that hypothesize the existence of “unobservables.” It’s not like they think that round Earth, heliocentrism, and germ theory are just useful (but untrue) “instruments” for making predictions about how to most efficiently navigate the seas, predict planetary motion, and treat diseases. They admit that the Earth actually is round, that the planets revolve around the sun, and that germs exist and cause disease. These facts and entities can be observed; the theories that suggest they exist are true. It’s only when theories start hypothesizing the existence of unobservables—like electrons, or quantum fields—that can’t be observed directly, that we should start doubting the theories’ truth. And to be fair to van Fraassen, in this published work, he doesn’t really say that we should doubt the truth of such theories. Only that scientific reasoning does not rationally force us to accept them as true. Skepticism, or agnosticism, he argues, is warranted. SUGGESTED READING Science is based in metaphor By Andrew Reynolds But the history of atomic theory throws a monkey wrench into that argument. Atoms used to be unobservable; again, scientists first accepted the theory that they exist because it had such grandiose explanatory power. But then atoms were seen with electron microscopes. They thus moved into the category of the observable. But this didn’t substantially change anything about what scientists were justified in believing; it certainly didn’t change any “atomic skeptics’” minds. It just confirmed what everyone already knew! If the hypothesis that something exists clearly provides the best explanation for what we can observe, then the belief that it exists is what is rational. The fact that the thing itself is not technically observable does not make doubting its existence rational.What’s more, the atoms were seen with an electron microscope. But electrons are themselves unobservable. How can an electron microscope reveal an atom if electrons are not real? This leads us to what is famously known as Hilary Putnam’s “miracle argument.” It’s (not) a miraclePhilosopher Hilary Putnam’s miracle argument is somewhat famous. Basically, he argued that a scientific theory being able to repeatedly make successful predictions—even about unobservables—without being at least approximately true would require a “miracle.” In other words, it would be such an improbable occurrence that it could not rationally be believed—the better explanation for why scientific theories about unobservables make the right predictions is because the unobservable entities and structures they hypothesize exist.Van Fraassen has addressed this argument. Indeed, in his original article, where he references Alison Gopnik’s point about orgasms not being “necessary for procreation” even though the desire for orgasm “drives the creation of progeny,” he is pointing to his own argument about how organisms are not naturally selected by evolution to get true beliefs; to the extent that belief-forming processes are selected for, the ones that are selected are the ones that are useful for survival—not the ones that produce true beliefs. In the same way, van Fraassen argues, scientific theories are accepted, not because they are true, but because they aren’t falsified; they make successful predictions; that’s what makes them “stick around.” So, the fact that they make successful predictions (and thus became accepted) is not a reason to think they are true.This argument is similar to C. S. Lewis’s “argument from reason,” which he used to argue against evolution: “The truth of evolution undercuts our ability to know that it is true.” Lewis’ argument famously failed; Elizabeth Anscombe, by Lewis’s own admission, demolished Lewis in a debate on the topic, and I have explained elsewhere why modified versions of the argument fail as well. In short, it’s because it fails to recognize that a belief-forming process can make an organism more likely to survive because it reliably produces true beliefs. It is therefore not the case that beliefs generated by naturally selected belief-forming processes are automatically false or unjustified.In the same way, the reason a theory “sticks around” could be because it’s not falsified, because it “makes correct predictions.” But the reason it makes correct predictions is most likely because it is true. (In pointing this out, I am echoing the arguments of Musgrave, Lipton, Psillos, and Kitcher, who refuted van Fraassen’s argument and analogy long before his 2024 article.) It would be a huge coincidence that it could do so without being true. And that is the point of Putnam’s miracle argument. Thus, contrary to van Fraassen’s suggestion, the mere fact that a theory’s predictive success is why it “sticks around” or “becomes accepted” in the scientific community is not a reason to be skeptical about its truth. ConclusionLet me close by saying something about the fact that empiricists don’t doubt the truth of all scientific theories, just the ones that hypothesize unobservables. In today’s society, this theory is dangerous to espouse publicly. The nuance between being skeptical about all of science, and just the highly technical theories about unobservables, is guaranteed to be lost to the average reader. And there is so much unjustified skepticism and doubt about the findings of science and experts that a headline like “Science Does Not Describe Reality” could easily fuel the anti-science movement, worsen climate change denial and cause the next pandemic.This is why I believe it was important to still respond to van Fraassen’s article, a full two years after he wrote it. Not only, as I have argued, does it represent a philosophically inaccurate view of how scientific reasoning works and what scientific reasoning can do, but it is a dangerous view to boot. It should thus be rejected.
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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The ill-fated partnership officially kicked off in December 2024, when Lepu tapped CoDevCo as its “exclusive business development mechanism” to identify collaborators for the company’s drug candidates. According to Lepu’s complaint, Zhang personally negotiated and signed the agreement as managing director for CoDevCo, which used her home address. Before the Lepu deal, Zhang made a name following a short stint as the global head of business development for Hengrui Pharmaceuticals. It was during her tenure that Hengrui signed a landmark deal granting exclusive rights for a portfolio of GLP-1 assets to Hercules, which was at that time newly established by a group of private equity and venture capital firms. In addition to the regular upfront and milestone payments, Hengrui also gained an equity stake in Hercules, which later became Kailera Therapeutics. The Hengrui-Hercules deal opened a new paradigm, where a Chinese biopharma company spins off certain early-stage assets to investors for further development through the creation of a new company abroad. The “NewCo” model quickly came into vogue as it allows Western investors to access high-potential assets originating from China at an early stage while giving the Chinese licensors an opportunity to reap long-term benefits through equity stakes in the new firms. The NewCo model proved its value when Kailera staged a record-breaking $625 million IPO on Nasdaq this April, merely two years into the Hengrui deal. Related Kailera CEO 'knew we were in a good spot' before obesity biotech's record-breaking $625M IPO On her LinkedIn page, Zhang described her work at Hengrui as “[b]uilding team and capability from the ground up,” forming NewCo and major pharma partnerships worth billions of dollars. Lepu clearly wanted that kind of track record to help boost its own cardiometabolic portfolio, which includes a range of assets for obesity, Type 2 diabetes, fatty liver disease and muscle preservation during weight loss treatment. “Lepu’s pipeline is very valuable, but only if Lepu could secure the right international partner to expand into the overseas market during the available commercial window,” the company argued in its complaint. The Chinese biotech said it had little knowledge of U.S. laws, customs or business practices in the business development field, and therefore “needed to rely entirely” on the expertise of Zhang and her team as the firm’s first engagement of a U.S.-based BD consultant. “Zhang’s dominating influence on the business development strategy is further evidenced by the fact that she personally controlled the business-development communications on behalf of Lepu with potential partners,” Lepu said in its complaint. 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It seems likely that Zhang facilitated the Minwei deal given that Lepu is on record as having used CoDevCo as its “exclusive business development mechanism.” The big shock for Lepu came in the form of a news article on June 25, 2025. The article, reporting on phase 2 data for BrightGene’s GLP-1/GIP receptor agonist BGM0504, identified Zhang as acting chief business officer of the Lepu rival. Blindsided by her association with BrightGene, Lepu confronted Zhang in July 2025. “Lepu was given assurances that there was nothing to be concerned about and told that Zhang would explain the matter to Lepu,” Lepu alleged in its complaint. “Zhang never did.” Lepu claimed that Zhang had the motive and opportunity to steer potential prospective partners toward BrightGene or other competitors. Later, in February 2026, one of Zhang’s associates joined BrightGene as the vice president for global business development, according to the complaint. Around the same time, Lepu sent written demand letters asking Zhang to account for her BrightGene role, identify what confidential data were shared with the rival firm, and provide any conflict-of-interest or firewall policies during the engagement. According to Lepu, neither CoDevCo nor Zhang answered the questions in their responses. Related Novo vs. KBP: How a $1.3B deal turned into a fraud accusation and an international legal fight In a motion to dismiss filed with the U.S. District Court in the Eastern District of New York on Sept. 4, Zhang’s legal team argued that Lepu’s agreement was signed with CoDevCo, and that an employee of the contractor does not owe fiduciary duties to the client. In its complaint, Lepu said: “That CoDevCo was the contracting entity does not insulate Zhang from personal liability for duties she personally undertook and personally breached.” Taking the argument one step further, the defending party argued that the consulting agreement “does not create a fiduciary relationship even between CoDevCo and Lepu; instead, it identifies CoDevCo as an independent contractor retained to market Lepu’s business to potential western partners.” Although CoDevCo was Lepu’s exclusive business-development contractor, there were no terms stipulating that the consulting firm should serve only Lepu, Zhang’s lawyer noted. As to Lepu’s claims that Zhang misappropriated trade secrets, the defendant argued that Lepu authorized the use of the information so Zhang’s team could perform their service per the agreement. In a rebuttal filed on Sept. 11, Lepu’s lawyer set out why they believe the Chinese biotech satisfied New York law’s misappropriation definition by alleging that the defendant used a trade secret “in breach of a duty or through improper means.” As an alternative to dismissing the suit, the defendant suggested the action should be stayed pending outcomes from the arbitration of a separate case in Singapore. While NewCo pioneer Zhang is defending her business arrangements, momentum behind the NewCo trend has continued unabated into 2026. Through August, Chinese biotech assets have spurred 15 NewCo deals this year, according to local trade publication PharmaDJ.
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