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Analysis | Trump says he has an off-ramp to his biggest political problem. He refuses to take it.

There is nothing holding back Republican political fortunes this year more than the war that President Donald Trump started with Iran.

Sep 28 • 5:23 AM EDT • Politics • washingtonpost.com

Malik Nabers totals five receptions

New York Giants wide receiver Malik Nabers posted five receptions for 26 yards on six targets in Week 3

Sep 27 • 7:41 PM EDT • Sports • sports.yahoo.com

Malik Washington targeted 10 times in Week 3

Miami Dolphins wide receiver Malik Washington posted five receptions for 56 yards on a game-high 10 targets in Week 3

Sep 27 • 5:16 PM EDT • Sports • sports.yahoo.com

Malik Willis throws for 210 yards

Miami Dolphins quarterback Malik Willis completed 20 of 36 passes for 210 yards, no touchdowns and one interception in Week 3

Sep 27 • 4:52 PM EDT • Sports • sports.yahoo.com

Maryland football destroyed by UCLA, 54-3, in 9th straight Big Ten loss

COLLEGE PARK, Md. — Maryland was outclassed from the start. In a game that was scoreless after one quarter but quickly devolved into another lopsided loss, nothing went the Terps’ way. Maryland couldn’t establish a running game despite a questionable insistence on doing so; quarterback Malik Washington never got going in the one-dimensional offense and threw four interceptions; and the Terps’ ...

Sep 26 • 8:22 PM EDT • Sports • sports.yahoo.com

Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL

Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Sep 21 • 3:38 PM EDT • Politics • washingtonpost.com

Hayden Panettiere remembered at Malibu memorial service

Hayden Panettiere attends the Los Angeles premiere of Netflix's new film 'Blonde' at TCL Chinese Theatre on Sept. 13, 2022, in Hollywood, California. (Jon Kopaloff/Getty Images)Hayden Panettiere was celebrated over the weekend at a memorial service held in California, her representative confirmed to ABC News.Around 80 friends of the late Nashville star, who died on Aug. 16 at the age of 36, gathered in Malibu on Saturday to share "an evening of music, memories, laughter and tears."“We wanted to honor Hayden in the best way we knew how—with as much love as possible," Panettiere's representative, Kasey Kitchen, said in a statement with a group of the actress's friends, who jointly organized the memorial.The statement continued, "It was a beautiful and intimate ceremony where friends came together to celebrate her life and honor the beautiful, magnetic light and love she infused into the world.”Panettiere's Nashville co-star Connie Britton and other celebrities, including Evan Ross and Ruby Rose, were photographed attending the memorial.Panettiere died after she was found unresponsive and in cardiac arrest at a Greenville, South Carolina, apartment.The actress's official cause and manner of death have not yet been announced.An investigation into her death has expanded from South Carolina to Los Angeles, and investigators are focusing on the role drugs may have played in her death, sources told ABC News last week.Kitchen, Panettiere's representative, said in a statement on Sept. 15 that her death "remains under investigation pending toxicology results.""As we await the answers we are all seeking, may we also remember Hayden for the incredible legacy she leaves behind — the light she shined on mental health and postpartum depression, and the voice she gave to those who felt unseen and unheard," Kitchen said. "The answers we are all seeking will come."Copyright © 2026, ABC Audio. All rights reserved.

Sep 21 • 2:16 PM EDT • Entertainment • willmarradio.com

Hayden Panettiere memorialized in Malibu celebration of life

Friends, family and close Hollywood colleagues honored Hayden Panettiere during a poignant celebration of life at a Malibu church this weekend, a month after the actress’s death from a possible

Sep 21 • 11:19 AM EDT • Entertainment • recorderonline.com

GOP lawmakers sound alarm on diesel fuel costs

Iowa Sen. Chuck Grassley joined the chorus of concerns over the weekend.

Sep 21 • 9:50 AM EDT • Politics • washingtonpost.com

Inside Late Hayden Panettiere's Intimate Malibu Celebration of Life

New details have emerged from the private Malibu ceremony honoring the life and legacy of Hayden Panettiere.

Sep 21 • 8:04 AM EDT • Entertainment • star-telegram.com

Trump and Mamdani to meet in New York

The president of the United States and the mayor have met three times so far.

Sep 21 • 7:55 AM EDT • Politics • washingtonpost.com

A true independent could shake Congress from its slumber

Americans should consider voting independent in November. Here’s why.

Sep 21 • 7:15 AM EDT • Politics • washingtonpost.com

Trump heads into a week of diplomacy, hampered by a lack of allies

At the United Nations on Tuesday and in meetings with China's Xi Jinping on Thursday, the president will largely stand alone.

Sep 21 • 5:00 AM EDT • Politics • washingtonpost.com

Four grabs for Malik Washington

Malik Washington led the Dolphins with four receptions against the 49ers in Week 2, turning those catches into 43 yards in the loss.

Sep 21 • 3:46 AM EDT • Sports • sports.yahoo.com

If you really hate it when music and film stars do politics, here’s the answer: give us politics that works

The problem is not famous people speaking out, as they always have. It is the feeling that leaders have failed, obliging celebrities to fill the vacuum, says Guardian columnist Nesrine Malik

Sep 21 • 1:00 AM EDT • Politics • theguardian.com

Even medical professionals are skipping health insurance because of high prices

A larger share of health care workers have health insurance than those in other fields. But they are feeling the pinch as health insurance costs rise.

Sep 20 • 8:16 AM EDT • Health • washingtonpost.com

Hideo Kojima explains the surprise split with Sony

Celebrated game director Hideo Kojima wrestled with Sony’s surprise cancellation months before it went public, he said in an interview, fearing “our studio could collapse.”

Sep 20 • 7:00 AM EDT • Technology • washingtonpost.com

I’m a pulmonologist. Here’s why new wellness claims about nicotine worry me.

Some wellness influencers are saying nicotine promotes cognition and longevity. Scientific studies, however, paint a more complicated picture.

Sep 20 • 6:00 AM EDT • Health • washingtonpost.com

Trump used to slam China. Here's why he's now rolling out the red carpet for Xi

When Donald Trump ran for office a decade ago, he called China a menace to the U.S. economy

Sep 20 • 12:07 AM EDT • Politics • washingtonpost.com

Game 155: Twins at Angels

First Pitch: 8:38 pm CDTTV: Twins.TVRadio: TIBN / WCCO 830 / The Wolf 102.9 FM / Audacy The kids have been showing out a bit in Anaheim, providing one of the only remaining reasons to watch 2026 Twins baseball as this underwhelming season has normalized itself to fall back in line with preseason projections. Now, […]

Sep 19 • 8:38 PM EDT • Sports • sports.yahoo.com

Cardinal Health Sees Growth Normalize as Specialty, At-Home Investments Expand

Cardinal Health (NYSE:CAH) CEO Jason Hollar said the company’s fiscal 2026 performance was supported by double-digit earnings growth across each of its five operating segments, while fiscal 2027 guidance reflects continued growth from a more normalized base. Speaking at a Baird event, Hollar said t

Sep 19 • 12:02 PM EDT • Health • finance.yahoo.com

MS NOW says journalists blocked from White House after Trump announces ban

The network said it “intends to take any and all steps necessary to defend our First Amendment rights” after Trump said he would block MS NOW, CNN and Politico.

Sep 19 • 10:12 AM EDT • Politics • washingtonpost.com

Retire Your Old Towel Rack: The Modern Alternative From Amazon

The Wita semi-oval towel rack is shaped like a large horseshoe with a bottom bar. This metal towel holder features a minimalist design and comes in a pair.

Sep 19 • 7:30 AM EDT • Technology • housedigest.com

The nation’s premier business group is hitting the road to stamp out socialism

In a six-week trip, the U.S. Chamber of Commerce hopes to convince midterm voters that free markets still offer the best hope for solving the nation’s economic woes.

Sep 19 • 6:00 AM EDT • Business • washingtonpost.com

How a fun night out got to be so expensive

With the cost of concerts, sports games and restaurants far outpacing inflation, more people are staying home.

Sep 19 • 6:00 AM EDT • Business • washingtonpost.com

Trump is sober about the midterm prospects for Republicans, advisers say

In private, President Trump has been hearing blunt news from advisers about the GOP's poor chances in the midterms and has accepted that some of the problem is of his making.

Sep 19 • 5:00 AM EDT • Politics • washingtonpost.com

Vought pushes for scrutiny of NIH grants in Oval Office clash

A heated debate took place in the Oval Office on Friday, with some Trump officials accusing the National Institutes of Health of funding grants that conflict with the president’s agenda.

Sep 18 • 11:19 PM EDT • Politics • washingtonpost.com

Trump announces ‘forever’ deal to defend Greenland as Denmark says signing ‘expected’ next week

President Trump announced an agreement with Denmark that he said gives the United States "permanent" sway over Greenland's security.

Sep 18 • 6:00 PM EDT • Politics • washingtonpost.com

Sally Field says Paul Newman complained about not being offered roles

The Hollywood legend “always talked about being dissatisfied with it,” recalls Field, his costar in “Absence of Malice.”

Sep 18 • 5:37 PM EDT • Entertainment • yahoo.com

Black congressional leaders endorse James Talarico in Texas Senate race

Talarico has strong support among Black voters in public polls, but he has recently stepped up his efforts to reach them.

Sep 18 • 5:30 PM EDT • Politics • washingtonpost.com

Iran war’s cost grows to $43.6 billion in new US military estimate

The U.S. military’s price tag for the Iran war has grown to $43.6 billion as of Sept. 3

Sep 18 • 4:49 PM EDT • Politics • washingtonpost.com

Heavy caffeine users and deeper sleep; wonders of microscopic life; preparing for life after an Alzheimer’s diagnosis; plus other stories with Vanderbilt Health sources

Beth Malow, MD, Professor of Neurology and Pediatrics in the Vanderbilt Sleep Division, was quoted in Women’s Health about a surprising study from the Journal of Psychopharmacology indicating that heavy caffeine users get deeper non-rapid-eye-movement sleep, even while sleeping less time. The New York Times quoted Dylan Burnette, PhD, Associate Professor of Cell and Developmental Biology, in a story (with videos) about the wonders of the microscopic life all around us. William Schaffner, MD, Professor of Preventive Medicine, was quoted by several news outlets about public health issues, including: Prevention (rabies vaccinations); Healthline (update on the Cyclospora outbreak); Prevention again (hundreds now sickened in measles outbreak); and AARP (“How do we know vaccines are safe?” video interview and transcript). Science posted a story about a new NIH research center on vaccine harms. The piece quotes Kathryn Edwards, MD, Professor of Pediatrics, Emerita. Lealani Mae Acosta, MD, MPH, Associate Professor of Neurology, was quoted in an Everyday Health story about how a person, after a diagnosis of Alzheimer’s disease, can enrich their life and prepare for the future. Amalia Peterson, MD, Assistant Professor of Neurology, was quoted by Everyday Health in a piece about common medications linked to lower dementia risk.

Sep 18 • 4:38 PM EDT • Health • news.vumc.org

California governor signs order pushing for an AI ‘kill switch’

California Gov. Gavin Newsom, a likely 2028 presidential contender, said he had to act because the federal government hasn’t done enough to regulate AI.

Sep 18 • 2:49 PM EDT • Politics • washingtonpost.com

These midterm polls caught our attention this week. They’re good for Democrats.

Political strategists and pollsters say surveys are usually more reliable after Labor Day.

Sep 18 • 2:20 PM EDT • Politics • washingtonpost.com

‘Rusty’ Malik Nabers ‘left some yards out there’ vs. Cowboys

Nabers got through his return healthy.

Sep 18 • 12:00 PM EDT • Sports • sports.yahoo.com

Build columns, not Trump’s arch, D.C. official tells administration

Local officials, preservationists and historians are pushing to scale back Trump's planned arch, advocating the slender columns originally envisioned by architects and lawmakers a century ago.

Sep 18 • 11:58 AM EDT • Politics • washingtonpost.com

Engrams Embedding Entendre: Codesign for Efficient DRAM/SSD Offloading

Engram extends standard token embeddings with learned multi-token lookups. Recurring local patterns retrieve vectors directly, reducing the need to reconstruct them through attention and feed-forward layers. With Engram model architecture optimization, it allows for lower HBM capacity to be needed for models at the same quality. This does not mean there won’t be an insane demand for HBM but it just means that model architecture will continue to innovate around constraints. This model architecture design is naturally codesigned for parameter offloading: each token accesses a few embedding rows whose addresses depend on token IDs, not hidden states. The runtime can prefetch those rows from host DRAM while earlier layers compute, keeping the table outside HBM without transferring entire weight matrices. Our Memory model contains our latest estimates of quarter by quarter HBM, DRAM, & NAND supply and demand. Offloading frees HBM for model weights and KV cache, potentially supporting larger batches or more concurrent sessions. When DRAM becomes the next constraint, NVMe offers another tier. Recommendation systems already cache frequently or recently accessed embedding rows in faster memory while backing colder rows with SSDs. After NVIDIA roadmap had to change due to massively despec’ing Rubin Ultra from 1024GB to now ~200GB of HBM per chip, model architecture optimizations like emgram maybe helpful. Our DeepSeek-V4.1-Flash configuration uses roughly 189 GiB of memory for Engram. We replace it with a memory-mapped (mmap) file and measure serving performance with offload to SSD. Later on in our report, we will show our Engram offloading experiments along with the official InferenceX agentic inference serving results on Engram models like DeepSeekv4.1 Flash across all 6 NVIDIA GPU SKUs along with MI355X. Unsurprisingly, the CUDA Moat is still mogging MI355X on the ultra popular DeepSeekV4.1 Flash model. We also show how even on high capacity HBM SKUs, offloading emgrams to DRAM could result in even better performance for most of the pareto than keeping the emgram in HBM. Our benchmark has been widely reproduced, validated and/or supported by almost every major buyer of compute from Google Cloud to Microsoft Azure to Oracle, to Meta and many more. Furthermore, it has the support of the ML community including from vLLM, LMCache, SGLang, PyTorch, Huggingface and the support of major labs like OpenAI, MiniMax, ZAI, Qwen, Moonshot Kimi, etc. Star the InferenceX GitHub repository if you find the open-source benchmark and data useful!. InferenceX is the only inference benchmark in the world to have TPUv7, Jalapeño, Nvidia Rubin NVL72, AMD, and soon, SambaNova and Trainium. Due to how realistic AgentX scenario is to real world agentic inference workloads, AMD has committed to collaborating on MI455X UALoE72 too. DeepSeek did not release the original paper’s two trained Engram models. We replicated its setup on fineweb-edu using the released code and training hyperparameters, at an estimated 6E18 FLOPs per run. We observed the same U-shape scaling: Engram improved performance over pure MoE baselines. We also reproduced DeepSeek’s results, where earlier-layer representations with Engram resembled those of later layers. Like the original Engram paper, it is possible to probe Engram’s gate scores to see what n-grams DeepSeek-V4.1-Flash makes the most use of. Our gate scan finds names, code fragments, relational phrasing, and boilerplate. These examples prioritize interesting-ness over gate strength. One unexpected result was Wright : Ace Attorney. These examples suggest learned memory optimizes the training objective, not a judgment of which facts deserve storage. Licenses, bibliography fragments, API scaffolding, and website furniture can provide prediction shortcuts, so the value of additional Engram capacity may depend on what survives data preparation. This does not show that table capacity is “wasted”: the evaluation-corpus scan establishes neither training exposure nor the capacity occupied by each category. For offloading, strong gates do not identify cache-hot rows. Low gates do not automatically save reads either: computing the gate requires the retrieved key and undoes the performance gain of a fused kernel. Skipping reads would require a separate usefulness predictor before retrieval. In the original paper’s inference-time ablation, factual-knowledge benchmarks retained just 29–44% of their original performance, while reading comprehension retained 81–93%. This is due to the training–inference mismatch. The resulting degradation therefore measures this trained model’s dependence on Engram, not the performance difference between models trained with and without it. In our ablations, suppressing Engram worsens token likelihood across all evaluated domains, especially encyclopedia text and several code corpora. Surprisingly, GSM8K accuracy stays within measured run-to-run variation and removing Engram has no effect. Engram is not a detachable dictionary beside an unchanged MoE. Removing it changes downstream features and expert selection. We tested whether rerouting hurts or compensates by holding tokens fixed in a teacher-forced experiment on CRUXEval, a code-reasoning benchmark of small Python functions where the model predicts a function’s output from its code and an input, and scoring the reference answer. Removing Engram raised answer loss from 0.2848 to 0.3093 bits/token. Forcing the ablated model to use the original Engram-on expert choices made it worse still, at 0.3375 bits/token. Rerouting partially compensates for the missing memory. Memory features and expert selection work together, rather than following a clean “memory stores facts; experts reason” division. On the same CRUXeval, removing Engram during either phase reduced accuracy and increased generated tokens; removing it throughout produced the largest changes. Keeping Engram for prefill leads to more correct answers than keeping for decode likely due to semantically richer KV cache transferred to decode workers, allowing it to mitigate some of the performance loss. Engram’s table is large, but each lookup is small. DeepSeek-V4.1-Flash requests 24 rows at each of two Engram layers, about 12.4 KiB per processed token position across the model, or 3.1 KiB per GPU when split across four GPUs. Currently as of Day 7 since Model Release, MI355X is still 2-4x worse performance per dollar compared to B200 even when normalized by Mi355X’s lower TCO. Our full total cost of ownership breakdown comes from our AI Cloud TCO Model along with monthly market surveys of over 100+ gpu clouds & gpu cloud customers. On the Day 0 release of DeepSeekv4.1 Flash, NVIDIA vLLM works out of the box with zero issues across all 6 SKUs: H100, H200, B200, B300, GB200, GB300! This was thanks to the amazing work by the NVIDIA & Interact teams! In comparison, AMD vLLM did not work on day 0 for DeepSeekv4.1 Flash.Source: SemiAnalysis InferenceX AMD’s vLLM documentation points to using vllm/vllm-openai-rocm:deepseekv41-flash-0909, but from hour 0 of the model release to hour 23, AMD has not publicly released the image. AMD claims, “SPEED IS THE MOAT,” yet it has still not released it by the 23rd hour. We wish that, going forward, the AMD team has a better process for hour 0 model releases. Eventually when they did publicly release for “day 0” image support, performance-wise, it is currently up to 14.8x worse perf per dollar than H200 and up to 42x worse perf per dollar than B200/B300. The power of the CUDA MOAT is NVIDIA’s collaboration with its massive 6 million-developer community ecosystem including most of the vLLM & SGLang & Tokenspeed maintainers which means that CUDA is optimized on day 0. Overall, AMD did make significant improvements but the performance per dollar is still currently 2-4x worse than B200. AgentX Engram DRAM Offloading Improving Performance The HBM and DRAM offload use the same GPU kernel to select and dequantize rows. With HBM, it reads GPU memory; with Unified Virtual Addressing (UVA), it reads pinned host memory directly. Both support full decode graphs. Moving the table into HBM accelerates only the sparse lookup, leaving decoder computation and communication unchanged, resulting in little overall benefit while consuming memory otherwise available to KV cache. Another benefit of Engram offloaded to DRAM which means you can reduce the communication overhead by using less HBM GPUs per replica. For example, when enabling Engram offloading on B300, we are able to switch from TP4 to now TP2 which improves the pareto curve by up to 1.6x. When iso-model quality, less HBM is required as the engrams could be offloaded to host DRAM. Thus HBM bandwidth matters way more than HBM capacity. For inference workloads where memory bandwidth matters the most, 4-hi HBM provides the best $/bandwidth and therefore lowest cost per token. If China continues to make more and more revolutionary model architecture innovations, soon it could potentially 0Hi HBM stacks. [ ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) [ Long Live the Short King: Why 4-hi HBM Wins ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Myron Xie, Bryan Shan, and 3 others · Sep 13 [ Read full story ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Moreover, on B300 and week-0 stack, moving the Engram table back to HBM did not improve results and stay within run-to-run variance. This is a result of the work optimizing DRAM offload, such as async, and overlap. SSD Offloading On B200, we created a unoptimized vLLM fork and stored the Engram tables in memory-mapped files on local SSDs. File backing lets the OS reclaim table pages when other applications need RAM. Pages already cached in memory can be served without reading the SSD again. Furthermore, note that we were unable to turn on GDS The unoptimized SSD implementation changes how rows reach the GPU. It copies row IDs to the CPU, deduplicates them, gathers the requested rows into pinned buffers, copies those rows back to the GPU and dequantizes them. This work runs between segments of the GPU execution graph. Native UVA performs row selection and dequantization directly on the GPU, avoiding the CPU round trip. A warm filesystem cache removes physical SSD reads, but leaves the coordination, row gathering and transfers. This is why a file already cached in RAM can still perform worse than a pinned DRAM table. The comparison measures the whole serving path; it does not separate the time spent on each of these operations. B200 DRAM dominates both measured SSD serving curves in total tokens per dollar and P90 interactivity. Near 125 tokens/s/user, DRAM delivers 121 million total tokens per dollar versus 52 million for SSD. For production serving, SSD offloading is likely not worth the tradeoff. On the B200 configurations we measured, SSD offloading loses on both measures: every observed SSD point has a DRAM alternative that delivers higher P90 interactivity and more total tokens per dollar. The only points where Cheaper storage does not automatically produce a cheaper inference service. Moving Engram to SSD leaves the same four expensive GPUs and the rest of the server in place. Reclaiming RAM only creates an economic benefit if it enables a cheaper server configuration or additional useful capacity. The current unoptimized path provides neither benefit, and the filesystem cache still consumes RAM when table pages are resident. Next we will look at the mechanisms and specific implementation of ngrams from DeepSeekv4.1 Flash, LongCat, Qwen3.8 Flash Next.

Sep 18 • 10:35 AM EDT • Technology • newsletter.semianalysis.com

Global health reform and last-mile integration: the missing link in pandemic preparedness

As the UN General Assembly's High-Level Week kicks off, global health reform is back on the agenda, but the real test will not be in New York conference rooms. It will be in whether reform reaches the last mile.

Sep 18 • 8:00 AM EDT • Health • gavi.org

JD Vance returns to Iowa as Senate and governor races heat up

Vice President JD Vance is heading to Iowa for the second time this year to campaign for Republican majorities in Congress

Sep 18 • 7:07 AM EDT • Politics • washingtonpost.com

Trump refers to Black man from racially offensive 1988 campaign ad while stumping in North Carolina

President Donald Trump is using a controversial campaign ad from 1988 to criticize Democrats on crime

Sep 18 • 12:10 AM EDT • Politics • washingtonpost.com

Health Brief: The latest task force shake-up

Plus: More on RFK Jr.’s keynote at the Children’s Health Defense conference

Sep 17 • 6:34 PM EDT • Health • washingtonpost.com

Senator blocks bill meant to lower electricity prices linked to data centers

Sen. Martin Heinrich (D-New Mexico) halted passage of a proposal that had passed the House by an overwhelming margin.

Sep 17 • 5:00 PM EDT • Politics • washingtonpost.com

From Science to Signals, Part II: What the SEC-FDA Cooperation Agreement Means for Life Sciences Companies

The SEC and FDA have formalized an emerging enforcement trend. We recently described the SEC’s evolving approach to insider trading,...

Sep 17 • 4:39 PM EDT • Science • freshfields.com

Democrats seize on House GOP’s decision to leave town early

The Republican-led chamber has no more workdays scheduled in Washington before the November midterms.

Sep 17 • 3:21 PM EDT • Politics • washingtonpost.com

After gaining acclaim in Los Angeles, conductor Gustavo Dudamel takes on New York

Gustavo Dudamel has taken over as music director of the New York Philharmonic

Sep 17 • 12:34 PM EDT • Entertainment • washingtonpost.com

The Latest: Trump says EU allowing Canada as associate member could be a ‘hostile act’

President Donald Trump suggested that the European Union allowing Canada to become an associate member could be a “hostile act” and threatened to respond to the proposed move by imposing more tariffs on the bloc

Sep 17 • 8:19 AM EDT • Politics • washingtonpost.com

RFK Jr. to give keynote speech at conference for anti-vaccine group he founded

Since Robert F. Kennedy Jr. was confirmed as health secretary, he has made clear he wants to overhaul the nation’s immunization system.

Sep 17 • 5:00 AM EDT • Health • washingtonpost.com

Trump emphasizes crime in midterm push in North Carolina

The president made violent crime the central issue in his first large-scale outdoor rally this year and cites the GOP’s 1988 “Willie Horton” attack ad on Democratic nominee Michael S. Dukakis.

Sep 16 • 10:44 PM EDT • Politics • washingtonpost.com

Trump’s arch will harm historic sites but must proceed, federal officials say

National Park Service officials acknowledge that President Donald Trump’s planned arch would harm dozens of historic sites but say it must move forward anyway.

Sep 16 • 2:43 PM EDT • Politics • washingtonpost.com

IATSE Joins Special Ambassador, Lawmakers, and Coalition for Press Conference Unveiling Film & TV Incentive Study

At a September 15 press conference hosted by the newly formalized U.S. Film & TV Production Coalition, IATSE joined a broad alliance of labor organizations, studios, guilds, industry advocates, and […]

Sep 16 • 2:36 PM EDT • Entertainment • iatse.net

Why Allison launched Allison Worldwide Health Group

The Stagwell subsidiary is launching an integrated health communications offering to formalize Allison’s commitment to the medical marketing space.

Sep 16 • 1:34 PM EDT • Health • mmm-online.com

How vibe coding is impacting business in the long term

Utilizing AI to help software development is swiftly becoming normalized across organizations, leaving IT pros to manage any potential problems. Companies need to consider their level of liability when choosing to deploy vibe coding, Mike Wehrs, TieTechnology COO, told IT Brew. Issues can vary, and depend on the relative newness of vibe coding to the tech stack, as well as the talent of those using it.

Sep 16 • 12:50 PM EDT • Business • itbrew.com

Truth and Politics in the Age of Post-Truth

Get E-International Relations delivered to your inbox, free of charge. As you sign up, consider becoming a paid subscriber, or make a donation, to support our work. Subscribe This is an excerpt from Global Politics in a Post-Truth Era. You can download the book free of charge from E-International Relations. The term post-truth is by now so ubiquitous in describing the state of politics in the Western world and even beyond that the most pressing issue of the day appears to be about making democracy work in the era of post-truth rather than questioning the normalisation of the term itself in the first place. The critical turning point appeared to have occurred in 2016 when the term was chosen by the Oxford English Dictionary as ‘The Word of the Year.’ On its website, the Dictionary notes the transformation of post-truth from ‘being a peripheral term to being a mainstay in political commentary and connects ‘the spike in frequency’ directly with the Brexit referendum in the United Kingdom and the election of Donald J. Trump in the United States – both occurring in 2016. Paired with the noun ‘politics,’ post-truth is defined as an adjective ‘relating to or denoting circumstances in which objective facts are less influential in shaping public opinion than appeals to emotion and personal belief.’ The Oxford English Dictionary traces the first use of the term to a 1992 essay in The Nation by the playwright Steve Tesich as he reflected on the 1980s Iran-Contra scandal and the 1990–91 Gulf War: We are rapidly becoming prototypes of a people that totalitarian monsters could only drool about in their dreams. All the dictators up to now have had to work hard at suppressing the truth. We, by our actions, are saying that this is no longer necessary, that we have acquired a spiritual mechanism that can denude truth of any significance. In a very fundamental way we, as a free people, have freely decided that we want to live in some post-truth world (Tesich 1992, 13; emphasis added). He then continued, The Gulf War is over but the war at home goes on. The gulf between rich and destitute widens – between those of us who live in a modern post-industrial nation and those of us who live in the Third World countries of our inner cities. The present administration’s response to this internal crisis has shifted from benign to malignant neglect. The current levels of misery and decomposition of our cities and the economic gulags of our ghettos are acceptable. Since there is only so much hope to go around, there is a freeze on hope. The have-nots have now been reclassified as never-will-haves (Tesich 1992, 13). In the context of Tesich’s essay, truth includes both facts, as in what happens, and ‘moral absolutes,’ as in the ‘self-evident truths mentioned in our Constitution’ (Tesich 1992, 14). Together, these two notions of truth entail the obligation to both act and react. The two passages cited above show that even in the early post-Cold War years, Tesich was already deeply concerned that the American people are neither prepared to act on truth nor react to truth that is disconcerting, or what he calls ‘bad news’ (Tesich 1992, 12). Accordingly, Tesich’s insight as captured by the term post-truth is not that truth is irrelevant to what we know, but rather it is irrelevant to how we act. In contrast, ‘post-truth politics,’ as defined by Oxford as a term that pitches ‘objective facts’ against ‘emotion and personal belief’ such that the latter appears to have overtaken the former in shaping ‘public opinion’ and thereby, democratic politics. When Tesich’s post-truth politics and its current usage are juxtaposed, the two are in fact not identical in terms of what truth is and how it relates to politics. Against such consideration, this chapter provides a critical survey of selected historical events and theoretical considerations for the purpose of gaining a more nuanced understanding of the relation between truth and politics. Truth and Language One notable impact of post-truth politics is that language is being overtly deployed as a political weapon not only by politicians and those in power, but among the general population. It seems that once facts are irrelevant to the validity of what is being said, language becomes the platform for an all-out political contest in which what is said is no more than an act of will expressed as an assertion of power and/or an exercise in defiance. As early as in the writings of Thucydides (460–400 BCE), the vulnerability of logos – which is the human capacity for rational discourse in tumultuous times – was already noted. Thucydides belonged to a school of Greek thought which maintained that language is conventional and that the association between name and things is a result of ‘human use and habit’ rather than ‘nature or divine dispensation’ (Connor 1984, 99). The conventional nature of language means that it is incapable of providing its users with any independent criteria for judgement. In Thucydides’ study of the Peloponnesian War (431–405 BCE), the subversion of logos as seen in the manipulation of language was introduced through his account of the civil war in Corcyra (Thucydides 1972, 236-245). The war first broke out in 427 BCE between the pro-Athenian democratic faction and the pro-Spartan oligarchic faction before it spread to the rest of the Greek world. There was a general breakdown of law and order, resulting in extreme violence and death. Language underwent changes that were reflective of the events of the time. The English philosopher Thomas Hobbes (1588–1679) translated Thucydides’ description of the situation as follows: The received value of names imposed for signification of things, was changed into arbitrary. For inconsiderate boldness, was counted true-hearted manliness: provident deliberation, a handsome fear: modesty, the cloak of cowardice: to be wise in everything, to be lazy in everything... he that had been so provident as not to need to do the one or the other, was said to be a dissolver of society, and one that stood in fear of his adversary. In brief, he that could outstrip another in the doing of an evil act, or that could persuade another thereto that never meant it, was commended (Hobbes 1839–1845, 8: 348; Thucydides 1972, 242-243). What concerned Thucydides most was that the meanings of words are no more than linguistic conventions that require logos to support them. The Corcyrean civil war was a reminder that such capacity cannot be assumed. This is why history understood as an authentic account of what happens matters. Guided by logos, the historian’s task is ‘the search after truth’, which is established through ‘the absence of the fabulous,’ including ‘the rejection of myth and unverifiable stories’ (de Jonge 2017, 2). Thus, history plays an important role in facilitating the stability of language – without which distinctions and judgements cannot be rendered communicable. Just like Thucydides, Hobbes was a nominalist who subscribed to the view that there is no inherent meaning to words. Hobbes’ state of nature, where there is no common authority, is precisely one in which distinctions cannot be made. As Hobbes put it, there is ‘no Mine and Thine distinct’ nor is there distinction between ‘the notions of Right and Wrong, Justice and Injustice’ (1968, 188; emphasis in original). This is clearly an unsustainable condition for everyone. Behind Hobbes’ famous words that life in the state of nature is ‘solitary, poor, nasty, brutish, and short’ is his uncompromising argument for the ‘Leviathan’, which is described by the late American political theorist, Sheldon Wolin (1922–2015), as the ‘sovereign definer’ (Hobbes 1968, 186; Wolin 2004, 238–243). Accordingly, the social contract is importantly a ‘linguistic contract’ that binds all parties to ‘general names agreed upon’ (Peters 1979, 125; Hobbes 1968, 111). Through Thucydides and Hobbes, we can identify a line of thinking that sees politics as a contestation over the use of language, which is based on shared conventions and norms. Thus understood, politics is not a collective quest for the true nature of our being or an epistemological exercise in pursuit of true knowledge. Rather, politics is about humans living with one another by finding a shared language to communicate with one another on matters that affect them all. Truth is in that sense contingent on what is being said as opposed to setting the standard for it. In other words, truth is the embodiment of shareability among us. While truth as such ensures the viability of a political entity, truth by no means represents a normative standard to adjudicate among contesting actors in what they say, let alone in what they do. During Thucydides’ times, ancient China was also experiencing a tumultuous time as the ruling Zhou dynasty deteriorated into the period of the Warring States (481–221 BCE). This was when the rulers of Zhou no longer presided over the territories brought under its control through conquest. Instead of professing allegiance to the Zhou royalty, the lords of these territories became kings themselves to rule over their own land. The period was one marked by endless military campaigns as each of the seven major states aimed to conquer the rest (Lewis 1999). Yet, the period was also known for its intellectual vibrancy as different thinkers challenged the restoring of order among these warring states – including offering ideas and advice to rulers on good governance. Among these thinkers was Confucius (551–479 BCE). His thought, which came to be known as Confucianism, went on to become the state ideology of China from the Han dynasty (206 BCE–222 CE) until the end of the Qing dynasty in 1911 when China became a republic. The founding text of Confucianism was the Analects, which is a collection of dialogues between Confucius and his students as recorded by them. One key concept Confucius advanced is the ‘rectification of names’. Though the term only appears in one exchange in the Analects, it is considered a major aspect of Confucius’ thought. Generations of Confucian scholars from past and present, including Western academics, have debated over its interpretation (Makeham 2003). The passage in question reads as follows: Zi Lu said: ‘The monarch of the state of Wei wants you to govern the country, what is the first thing you plan on doing?’ Confucius said: ‘First it is necessary to rectify the names.’Zi Lu said: ‘Is that really what has to be done? You are being too pedantic, aren’t you now? How will you rectify these names?’Confucius said: ‘Zhong You, you are too unrefined. A gentleman, faced with a matter that he does not understand, takes a skeptical attitude. If names are not correct, one cannot speak smoothly and reasonably, and if one cannot speak smoothly and reasonably, affairs cannot be managed successfully. If affairs cannot be managed successfully, rites and music will not be conducted. If rites and music are not conducted, punishments will not be suitable. And if punishments are not suitable, the common people will not know what to do. So, when the gentleman uses names, it is necessary to be able to speak so that people understand. If one can say it, one can definitely do it. A gentleman should not be careless with words’ (Analects 13:3 in Cao 2016, 148). This translation is offered by the contemporary philosopher Cao Feng. As Cao notes, the passage is what started the whole debate over ‘exactly what kind of names did Confucius... wish to rectify’ (Cao 2016, 148). Of the three major groups of interpretation examined by Cao, beginning with classical Confucian scholarship, one is arguably the most influential and certainly most pertinent to the issue of language and politics. This is the interpretation that was first associated with the Neo-Confucian master, Zhu Xi (1130–1200), who argued that the ‘rectification of names is simply the rectification of politics’ (Cao 2016, 149). Within this interpretive framework, rectification has the dual functions of correction and prescription by ensuring that predetermined hierarchical roles are strictly adhered to through following ‘the system of rites and propriety’ (Cao 2016, 151). In addition, the rectification of names entails ‘using names to rectify actuality’ (Cao 2016, 151). Yet Cao rejects this whole body of interpretive works by arguing that these were ideas developed later. Instead, Cao suggests the following: The original meaning of Confucius’ rectification of names may, then, be quite simple. Confucius did not mean to establish a concrete, normative system of “names”; rather, Confucius was simply the first person in history to realize or remark upon the importance of language in politics. As a politician, he noticed and foresaw the impact that the indeterminacy, ambiguity, and arbitrariness of names would have on politics. Confucius recognized the political consequences of language’s not accurately expressing meaning or not being accurately received by people. He realized the great role that names, as a means of distinguishing right and wrong and establishing norms, could play in society and politics (Cao 2016, 168). Scholarly debates aside, Cao’s view has the advantage of identifying an interpretation of this controversial exchange in the Analects that enables its readers to extrapolate from it the observation that the meaning of words depends as much on their users as on their interpreters; neither of which can be predetermined. Accordingly, a good ruler is someone who can speak without ambiguity to his subjects and make good his words through actions. Stated differently, Cao’s view on what concerned Confucius then, who was living through times of protracted political upheaval, is that language is an indispensable political tool for those in power and can be deployed by both good and bad rulers alike. To sum up, this historical survey shows that politics as a war of words is by no means a distinctive marker of contemporary politics nor the Western world. Be it ancient or current, east or west, language is subject to manipulation to serve political purposes and when there is an outright war of words that defies existing norms, it is indicative of a political situation in which people no longer share a language and truth becomes irrelevant. Accordingly, political order entails stability in language use. Truth and Politics As previously noted, current use of the term post-truth as an adjective to the term ‘politics’ suggests that once there was a time when politics aligned with truth. Indeed, if we start with Plato’s Republic as the key founding text of Western political thought, we see that the ideal polis (city-state of ancient Greece) is where truth and politics converge, and justice is achieved. Written around 380 BCE when Athens was still coping with its defeat by the Spartans in the Peloponnesian War, the Republic is a defence of the rule of the ‘philosopher king’, defined as someone who is ‘guided by the truth’ and is ‘always and in every way’ in pursuit of the truth (Plato 1974, 490a). For Plato, truth converges with virtues and hence, letting the philosopher take charge of politics is to let the wisest and the most virtuous lead the less wise and the less virtuous even if it requires compulsion (Plato 1974, 499b). In Plato’s words, ‘…until the philosophers attain power in a city there will be no respite from evil for either city or citizens…’ (Plato 1974, 501e). The uncompromising rule of philosopher-kings is made palatable by the claim that we are all ‘earth- born brothers’ with random mixtures of gold, silver, bronze and iron, but only the gold can rule (Plato 1974, 414–415). Understandably, academic debates over the interpretation of Plato’s Republic revolve around the question of whether truth as attained in philosophy can be realised in politics as action and whether such a connection is even desirable. Without getting into the details of these scholarly exchanges, I suggest that they all share the concern that truth acquired through the rigorous process of philosophical reasoning is not without problem when applied to the real world of living humans. This is because not all humans are philosophers – and indeed, in Plato’s view, not everyone is capable of becoming a philosopher given the protracted and arduous training that one needs to endure to become one. Hannah Arendt (1906–1975), a highly influential political philosopher of the twentieth century, notes that ‘Plato was the first to introduce the division between those who know and do not act and those who act and do not know’ and that such a separation has remained ‘at the root of all theories of domination’ (Arendt 1958, 223, 225). What Arendt points out in this remark is not the gap between theory and practice, but rather that Plato provides the normative ground for those who know the truth to tell those who do not know what to do. Arendt herself took on the challenge of understanding the relationship between truth and politics through her analysis of Nazism and Stalinism. Arendt’s insight, which was controversial when The Origins of Totalitarianism was published in 1951, was to identify Nazism and Stalinism as representative of a new form of political rule – totalitarianism – making it distinct from ‘other forms of political oppression... such as despotism, tyranny and dictatorship’ (Arendt 1973, 460). Arendt defines totalitarianism as a self- contained system of ideas driven by their ‘logic’ and marked by a mode of reasoning called ‘ideological thinking.’ Ideological thinking as such is a distinctive form of political reasoning defined by three characteristics. First, ideological thinking claims to provide a ‘total explanation’ of all historical happenings, encompassing the past, the present, and the future. Second, while ideological thinking is an attempt to account for ‘factual reality’ in its totality, this mode of thinking is paradoxically divorced from reality and experience. This is because experience, being rooted in specificity, is clearly limited in its claim to totality. It follows that as its third characteristic, ideological thinking aims to emancipate thought from the limitation imposed by experience through a ‘specific method of demonstration.’ The method involves arranging facts into an ‘absolutely logical procedure’ that starts from an ‘axiomatically accepted premise’. It is, in short, a ‘process of deduction from a premise’ – which is the only possible movement in the realm of logic that leads to one definitive conclusion. This is how the ‘logicality of ideological thinking’ provides the basis for total explanation and the ‘principle of action’ for totalitarian movement (Arendt 1973, 468–474). Stated differently, totalitarianism is a form of uncompromising idealism that exists in one’s head irrespective of shared reality as experienced. It is the perverse form of what Arendt later refers to as ‘rational truth’, which is the product of the ‘speculative mind’ that belongs to philosophy, mathematics and the sciences. The ‘speculative mind’ is the mind working on its way to generate axioms and theories by relying on the cognitive capacity of the human brain (Arendt 1977, 231). The presence of others has no bearing whatsoever on rational truth. In contrast, ‘factual truth’ is what happens when humans are ‘living and acting together’ (Arendt 1977, 231). Factual truth is therefore particular and temporal by definition. But more importantly, factual truth is ‘political by nature’ because it can only be validated in the context of the human community (Arendt 1977, 238). In other words, factual truth is about humans in their plurality rather than in their singularity. For factual truth to be sustainable, we need what Arendt calls ‘common sense’ – understood as ‘community sense’ (Arendt 1982, 72). There is also another distinction about truth that Arendt makes which is pertinent to understanding how totalitarianism works. The issue is whether the so-called totalitarian ideology is simply an unnecessarily cumbersome way of saying that it is an all-round and polished lie. Here, Arendt calls totalitarian ideology the ‘modern lie’ – in contrast to the ‘traditional lie’. The latter is restricted by two conditions: that it is a lie about the ‘particulars’ and that it deceives only the ‘enemy’ – which means that the liar is not engaged in self- deception. The modern lie, however, involves a ‘complete rearrangement of the whole factual texture’. It also intends to deceive everyone alike, to the extent that those who initiate the lie eventually ‘fall victims to their own falsehood’ (Arendt 1977, 249–254). This distinction between the traditional and modern lie is important. It indicates that not only is totalitarianism a lie, but the lie is in fact too big to fit into the standard meaning of the word. To tell a lie from truth, we need a common standard. In the case of a traditional lie, the common standard is precisely ‘the fabric of factuality’. As such, a lie always appears as a ‘tear’ to that fabric. Yet, modern lies require making a surrogate reality with a completely different context for facts to fit ‘without seam, crack, or fissure, exactly as the facts fitted into their original context’. Arendt notes that as long as those who concoct the surrogate reality are prepared to engage in self- deception to ‘create a semblance of truthfulness’, there is nothing to prevent ‘these new stories, images, and non-facts from becoming an adequate substitute for reality and factuality’ (Arendt 1977, 253–254). Totalitarianism therefore requires a person to stand outside of the system itself in order to make sense of it. Arendt points out that it is futile for us to argue with (for example) a Nazi or a Stalinist on race or class. To confront totalitarianism requires more than just a confrontation with specific facts. It is a more fundamental confrontation between reality as experienced and its total rejection. This means that Nazism and Stalinism are more than radical ways of conducting racial conflict or class struggle. Rather: Totalitarian politics – far from being simply antisemitic or racist or imperialist or communist – use and abuse their own ideological and political elements until the basis of factual reality, from which the ideologies originally derived their propaganda value– the value of struggle, for instance, or the interest conflicts between Jews and their neighbours – have all but disappeared (Arendt 1973, xv). Accordingly: The ideal subject of totalitarian rule is not the convinced Nazi or the convinced Communist, but people for whom the distinction between fact and fiction (that is, the reality of experience) and the distinction between true and false (that is, the standards of thought) no longer exist (Arendt 1973, 474). Who then is the ‘ideal subject’ of totalitarianism? Although there is a revival of interest in Arendt’s observation on truth and politics since the onset of post- truth politics, not enough has been said about her reply to the question (Hyvönen 2018; Klinkler 2018; Lee 2019; Zerilli 2020). Yet if we take a look at Arendt’s portrait of this ideal subject, her view is even more pertinent to our current challenge. As a self-contained system of ideas that is detached from experience, totalitarian thinking offers consistency in ways that reality cannot. Arendt notes that this kind of consistency is especially appealing to those who have lost a sense of bearing in the world (Arendt 1973, 353). They constitute what she calls the ‘masses’. The ‘mass man’ is thus a highly isolated and atomised individual, who is ‘obsessed by a desire to escape from reality’ (Arendt 1973, 318, 352). In his ‘essential homelessness’ the mass man can ‘no longer bear its accidental, incomprehensible aspects’ (Arendt 1973, 352). This longing for escape from reality is a ‘verdict against the world’ in which one is ‘forced to live’ but ‘cannot exist’ (Arendt 1973, 352). Such a situation is ripe for the ‘revolt of the masses’ against ‘common sense,’ which is ‘the result of their atomisation, of their loss of social status’ and with it, the ‘whole sector of communal relationships in whose framework common sense makes sense’ (Arendt 1973, 352). In short, the masses are people who are considered to be ‘superfluous or can be spared … [who] cannot be integrated into any organisation based on common interest’ (Arendt 1973, 311). Whether one agrees with Arendt’s analysis of the social conditions in the interwar years that led to the formation of the ‘masses’, her portrait of the ‘mass man’ is a powerful account of what can happen to an individual who has become disposable to the society that they used to belong to. Hand in hand with this phenomenon is indeed the collapse of ‘common sense’ that leaves the dislodged individual scrambling for reconnection. By offering the masses a substitute reality validated by the ‘logic of an idea’ rather than by experience, totalitarianism makes it possible for them to live in a world where there is no condition of plurality. Between ‘facing the anarchic growth and total arbitrariness of decay’ and ‘bowing down before the most rigid, fantastically fictitious consistency of an ideology’, the masses will likely ‘choose the latter’ (Arendt 1973, 352). A world created by ideology, then, is more attractive to the masses not because ‘they are stupid and wicked, but because in the general disaster this escape grants them a minimum of self- respect’ by conjuring up ‘a lying world of consistency which is more adequate to the needs of the human mind than reality itself’ (Arendt 1973, 353). Moreover, it is precisely this ability to guarantee consistency that makes it possible for the leaders of totalitarian movements to demand ‘total, unrestricted, unconditional and unalterable loyalty of the individual member’ (Arendt 1973, 323). While this chapter is not a study of the social factors that led to specific contemporary developments such as the result of the Brexit referendum or the election of Donald Trump in 2016, Arendt’s ‘mass man’ seem to have found their counterparts among the supporters of Brexit and Trumpism. Studies of voters’ profiles in both events point to a disproportionate share of supporters from white male lower income backgrounds without university educations. These are individuals who have either already lost their jobs to globalisation or who are at high risk of losing their job with very little capacity to be retrained for the twenty-first century market economy of advanced industrialised states (BBC 2016; Pew Research Center 2018). In short, these displaced workers are part of the tapestry forming the modern equivalent of Arendt’s ‘mass man’ – ready to be the recruits of totalitarianism. Conclusion If we step back to take a more comprehensive approach to the relationship between truth and politics, both historically and theoretically, it is not so obvious that 2016 is a defining moment. From ancient China and ancient Greece to our so-called post-truth age, the indeterminacy of language appears to be a persistent political challenge. Language is always open to manipulation by its users to serve power. Nonetheless, the tendency these days is to single out the ubiquity of social media and the proliferation of Internet platforms as the incubator for the countless cyberwars of words that in turn fuel the real world of politics. In this context, language is no longer the conveyor of objective facts and accurate information, but rather the medium for expressing subjective opinions and feelings, as captured by the Oxford Dictionary’s definition of the term ‘post-truth politics’. In contrast, the historical approach used in this chapter shows that it is in fact too easy to point the figure at the Internet and digital communication for the political challenge that we face today. What is being suggested here is that with or without the Internet, language, be it used to convey facts or emotions, is simply a tool for communication that humans have invented. While language per se cannot adjudicate what is true or not true, what is right or wrong, it embodies such capacity when language is a shared norm. That shared norm cannot be sustained without some semblance of cohesion in any given community. Any war of words, irrespective of its platform, is indicative of the breakdown of such cohesiveness. Returning to the original context in which the term post-truth politics was first used by Steve Tesich helps to identify the important distinction between truth as the standard for knowledge and truth as the standard for action. The two do not necessarily coincide. Placed in the context of the history of political thought, this distinction is in fact at the heart of Plato’s Republic. Yet when the philosopher as the quintessential bearer of truth becomes king, the polis that he rules over is far from the ideal of a just state that it purports to be. Instead, it is one that is held together by lies and coercion. What Arendt reveals through her study of Nazism and Stalinism is that it is dangerous for the kind of truth that philosophy generates – ‘rational truth’ – to become the guide to politics. Politics guided by rational truth can only be uncompromising and follows a logic of its own that cannot afford the ambiguity and indeterminacy of reality as lived experiences of humans. A world of post-truth politics can be an opportunity for a new kind of politics if it is indeed about dismantling the idea that truth is the ideal that politics should strive for. But as it stands, the post-truth politics of today is more about invoking a past that never exists to judge the presence as a crisis in naming when the real crisis is about rebuilding a shared space that has room for all – be they of the left, right or centre; cosmopolitan or parochial; civic-minded or self-centred; liberal-minded or bigoted. Politics is and always will be about striving for that space, without which no human can thrive. References Arendt, Hannah. 1958. The Human Condition. Chicago: The University of Chicago Press. Arendt, Hannah. 1973. The Origins of Totalitarianism. Rev. ed. New York: Harcourt Brace Jovanovich. Arendt, Hannah. 1977. “Truth and Politics.” In Between Past and Future, 227–264. New York: Penguin Books. Arendt, Hannah. 1982. Lectures on Kant’s Political Philosophy, edited by Ronald Beiner. Chicago: University of Chicago Press. British Broadcasting Corporation. 2016. “Brexit vote: The breakdown.” BBC News, December 7, 2016. https://www.bbc.com/news/uk-politics-38227674 Cao, Feng. 2016. “A New Examination of Confucius’ Rectification of Names.” Journal of Chinese Humanities 2: 147–171. https://doi-org.subzero.lib. uoguelph.ca/ doi/ 10.1163/23521341-12340032. Connor, W. Robert. 1984. Thucydides. Princeton: Princeton University Press. de Jonge, Casper C. 2017. “Dionysius of Halicarnassus on Thucydides.” in The Oxford Handbook of Thucydides, edited by Sara Forsdyke, Edith Foster, and Ryan Balot. Oxford University Press. DOI: 10.1093/ oxfordhb/9780199340385.013.17 https://www-oxfordhandbooks-com.subzero. lib.uoguelph.ca/view/10.1093/oxfordhb/9780199340385.001.0001/oxfordhb-9780199340385 Hyvönen, Ari-Elmeri. 2018. “Careless Speech: Conceptualizing Post-Truth Politics.” New Perspectives 26 (3): 31–55. https://www.proquest.com/ scholarly-journals/careless-speech-conceptualizing-post-truth/ docview/2204515132/se-2?accountid=11233. Hobbes, Thomas. 1839–1845. The English Works of Thomas Hobbes, edited by Sir William Molesworth. London: John Bohn. Vol. 8. Klinkner, Melanie. 2018. “Reasonable Truth.” International Journal of Media & Cultural Politics 14 (3): 393–99. doi:10.1386/macp.14.3.393_7. Lee, Haiyan. 2019. “When Nothing Is True, Everything Is Possible: On Truth and Power by Way of Socialist Realism.” PMLA/Publications of the Modern Language Association of America 134 (5). Cambridge University Press: 1157–64. https://doi.org/10.1632/pmla.2019.134.5.1157 Lewis, Mark E. 1999. “Warring States Political History.” In The Cambridge History of Ancient China: From the Origins of Civilization to 221 BC, edited by Michael Loewe and Edward Shaughnessy, 587–650. Cambridge: Cambridge University Press. Makeham, John. 2003. “Zheng ming (Rectification of names).” In RoutledgeCurzon Encyclopedia of Confucianism, edited by Xinzhong Yao. Vol. 2: 813-814. New York: Routledge. Oxford Languages, n. d. “Word of the Year 2016.” Accessed 19 August 2017. https://languages.oup.com/word-of-the-year/2016/ Peters, Richard. 1979. Hobbes. Westport: Greenwood Press. Pew Research Center. 2018. “An examination of the 2016 electorate, based on validated voters.” Report, August 9, 2018. https://www.pewresearch.org/ politics/2018/08/09/an-examination-of-the-2016-electorate-based-on- validated-voters/ Plato. 1974. Republic. Translated by G. M. A. Grube. Indianapolis: Hackett. Tesich, Steve. 1992. “Watergate Syndrome: A Government of Lies.” The Nation: 12-14. January 6/13, 1992. Thucydides. 1972. The Peloponnesian War. Translated by Rex Warner. Harmondsworth, England: Penguin Books. Wolin, Sheldon. 2004. Politics and Vision: Continuity and Innovation in Westen Political Thought. Expanded Edition. Princeton: Princeton University Press. Zerilli, Linda M. G. 2020. ‘Fact-Checking and Truth-Telling in an Age of Alternative Facts.’ Le foucaldien 6, no. 1: 2, 1–22. Theresa Man Ling Lee is an Associate Professor of Political Science at the University of Guelph (Canada). Lee is a political theorist who specializes in contemporary political thought. Her research and teaching areas include continental philosophy, Marxism and critical theory, feminism, postmodernism, philosophy of social science, psychoanalysis, multiculturalism, human rights, disability studies, modern Chinese political thought and comparative political theory. Lee has published on a wide range of subjects in these areas, including intercultural pedagogy and the challenges of teaching as a person with multiple minority designations in a Canadian university classroom.

Sep 16 • 7:16 AM EDT • Politics • e-ir.org

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Sep 16 • 5:00 AM EDT • Politics • washingtonpost.com

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Sep 16 • 4:25 AM EDT • Sports • sports.yahoo.com

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Sep 15 • 4:02 PM EDT • Sports • sports.yahoo.com

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Sep 15 • 3:13 PM EDT • Politics • washingtonpost.com

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Sep 15 • 1:30 PM EDT • Politics • washingtonpost.com

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Sep 15 • 11:09 AM EDT • Politics • washingtonpost.com

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Sep 15 • 6:13 AM EDT • Politics • washingtonpost.com

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Sep 14 • 7:15 PM EDT • Politics • washingtonpost.com

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Sep 14 • 3:07 PM EDT • Sports • sports.yahoo.com

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Sep 14 • 2:36 PM EDT • Technology • macrumors.com

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Sep 14 • 2:23 PM EDT • Entertainment • newsweek.com