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The Literacy Crisis Reaches Dog-Bear Science
“New analysis of more than 300 bear encounters suggests our canine companions often increase odds of conflict and rarely serve as early warning systems many recreationists assume,” reads a subhead in Mountain Journal. The thing is, that study reaches no such conclusion. But you have to read beyond the abstract to understand that. Mountain Journal is not alone. Let’s look at a brief list of takeaways published elsewhere just to establish that none of them seem to know how to read science. Wes Siler’s Newsletter is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Here’s CBC: “A new peer-reviewed study, The Canine Conundrum: Is a Dog a Help or Hindrance in Bear Country?, dug into conflicts similar to what the video depicts, by analyzing 326 reported human-bear conflicts from 1901 to 2023 involving dogs.” “The study found 54 per cent of conflicts were started by dogs. In the encounters researchers included in the study, five people and 56 dogs were killed, and 170 people were injured.” “Lana Ciarniello, an independent researcher who co-authored the study, said researchers found when a person goes hiking with at least one other person, the odds of a negative bear encounter decrease by 50 per cent.” “However, when a dog is involved, the chances of a negative bear encounter increase because ‘a dog really adds a chaotic factor into the mix of recreation,’ said Ciarniello.” Again, the study finds no data supporting that conclusion. “Hiking with your pet dog may make you feel safer in bear country—but a hiker’s recent encounter and a new study prove that the numbers don’t add up,” writes Backpacker, which is now part of Outside. The numbers don’t add up to support this take. There’s plenty more examples, but all are equally dumb, so I’ll stop there. How did so many people get this so wrong? Three reasons: 1) the study is published behind a paywall, with only the abstract freely available. 2) the methodology sets out to create work relevant to a hyper-specific audience, not the public. And 3) the dataset studied is almost absurdly limited and doesn’t bear (get it?!) comparison to wider information. Let’s work through all three. The Problem is Money I understand the irony, since I’m writing about this on a subscription-model newsletter, but information wants to be free. The study is published by The Wildlife Society and costs $16 to access. Reprinting it is specifically prohibited by the terms of use, so I can only share snippets and my conclusions with you here. Having worked as a journalist for 24 years, I can report with some authority that journalists are both lazy and cheap. I don’t think it’s a stretch to say that much of the material you’re seeing written about this study is drawn from the freely-available abstract (above) only, and not a deep dive into its methodology or data. And that’s a problem, because abstracts are where researchers are able to break from their numbers and editorialize their opinions about conclusions. So what’s getting reported isn’t based on numbers, it’s based on an opinion designed for a specific audience, not the general public. Hell yeah ladies, kick that bear’s ass. The Methodology is Designed to Support a Predetermined Conclusion One of the biggest issues with the science that everyone likes to cite about bear spray’s efficacy is that no one understands that study was designed for a specific audience, looking for a specific answer. And since that audience is not the public, and our safety was not the question being asked, its conclusion is rendered irrelevant to our needs. Yes, I’m talking about Efficacy of Bear Deterrent Spray in Alaska, which was created by Tom Smith and Stephen Herrero, two of the same scientists who put together this dog-bear conflict analysis. In the spray study, the purpose was to present relevant agencies with the information they needed to issue their field workers with bear spray. As such, incidents where people were unable to access the spray or similarly failed to get it deployed in time were excluded from the results, and only incidents they deemed successful were included. Could a ranger roll down their vehicle’s window and scare a bear away from a dumpster by spraying it? Turns out the answer was yes, and that was good enough for the purposes of that study. The sample size of actual bear attacks—the thing you and I would want bear spray to provide a solution to, was too small to draw conclusions from, and didn’t indicate success in that role. Is a Dog a Help or Hindrance in Bear Country? has similar limitations. “Insights provided here are intended to help wildlife managers create effective guidelines regarding the presence of domestic dogs in bear habitat,” is explained clearly by the study’s text. To conduct the study, Smith and Herrero went looking for publicly available reports of dog-bear conflicts: “All incidents included in our analysis involved at least one bear, one dog, and one person who was at immediate risk of injury (e.g., not in a protective structure such as a cabin or vehicle), injured, or killed,” explains the report’s methodology. Why is that a problem? “We recognize that data used in this study are biased in that people generally only report adverse interactions with bears, not benign ones. Consequently, we assume that for the most part, people and their dogs pass through bear country without incident.” As was the problem with the bear spray study, people are drawing conclusions here from a study that was never intended to be relevant to the general public. The Smith-Herrero database famously excludes Alaska’s Defense of Life and Property records, which are elsewhere considered the largest and most authoritative source on human-bear conflict. The Dataset is Absurdly Limited A 2009 study conducted by the Washington Department of Fish & Wildlife estimates that each year there are at least 43,000 documented complaints of human-bear conflict across North America. Is a Dog a Help or Hindrance in Bear Country? Examined those reports for years ranging from 1901 to 2023, and only managed to find 326 such incidents that met the criteria explained above. Let’s do some quick math, poorly. 43,000 incidents x 122 years = 5,246,000 total incidents of documented human-bear conflict. Smith and Herrero were only able to find 326 incidents that met their criteria for dog+human+bear+risk or occurrence of injury. That means there’s a 0.006 percent chance that the study’s conclusion—that dogs make bear encounters more dangerous—even gets a chance of occurring. And remember, that’s only in documented conflicts. There’s no way to know how many people across North America run into a bear in any given year without any conflict, but it’s probably safe to assume that the total number is well in excess of 43,000. And, dig deeper into the study and you can find further restrictions that skew its conclusions even more. “While the people involved in these incidents did not report the level of training their dogs had received, it is our assumption that most were untrained companion dogs as opposed to well-trained bear dogs, such as Karelians and livestock guardian breeds that have proven to be significant aids in bear country,” the study’s methodology explains. And that’s a problem, because an ongoing study here in Montana is finding that the simple presence of a Kangal like our youngest dog Teddy can reduce visits to private property from grizzly bears by 87.8 percent. In addition to being a badass, Teddy is also a companion animal. And in my admittedly limited sample size of the three dogs currently present in our living room, she’s no more effective than her mutt brothers. Plenty of people own a dog capable of deterring bears, even if they didn’t set out to own a bear dog. The real purpose of this study appears to be a recommendation that leashes are mandated and recreationists pursue training in their deterrent of choice. But that doesn’t make for sensational headlines. Are There Any Real Takeaways Here? Let’s throw some numbers around, just to try and get our hands around what the larger picture might look like for bears and dogs here. The American Veterinary Medical Association estimates that 42.6 percent of American households own a dog. The Canadian Animal Health Institute says roughly 35 percent of households in Canuckistan own a dog. In an attempt to create the worst possible result for dogs, let’s run with that 35 percent number. And given that outdoorsy and rural people are more likely to both own a dog, and have bear encounters, let’s just make a giant assumption and apply that number to those 43,000 conflicts documented annually. If 35 percent of 43,000 human-bear encounters involve a dog, then we can assume that at least 15,050 dog-bear conflicts are occurring annually in North America. 15,050 x 122 = 1,836,100. Smith and Herrero were only able to find 326 incidents that met their human, dog, chance or occurrence of injury criteria across 122 years. And only 170 documented human injuries. So, with all the obvious caveats about these numbers in no way describing reality beyond narrow study parameters, what they actually found is that your risk of injury if your dog tangles with a bear is only 0.009 percent. I’ll take those odds next time I’m hiking my dogs in bear country. Top photo: “Superintendent Horace Albright, eating pancakes with bears, at Lake Lodge, Yellowstone National Park.” NPS. A journalist with more than two decades of experience working around the world, Wes Siler is here to cut through the outrage and disinformation to bring you the factual, insightful, actionable reporting you need to understand what’s going on. Upgrading to a paid subscription supports this reporting, and buys personal access to Wes, who will help you save money on gear, plan outdoor adventures, and prepare for real life, and who promises he’s less salty in real life than he sometimes comes across as on the Internet. Wes Siler’s Newsletter is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Packers RB Josh Jacobs charged after May arrest for domestic incident, could face NFL suspension
Nude suspect breaks into business: Report
Officers spoke with a manager of the business, who described an incident captured on security footage taken around 9:20 p.m. Monday.
Kissimmee business owner speaks out after illegal dumping caught on camera
The incident, which happened on a Sunday night, has since sparked a wave of threatening messages after the owner shared the footage on social media
‘There’s a whole process’: Bangor business owner highlights needle disposal challenges after patio incident
James Gallagher owns Bangin’ Whoopie in Bangor. He said he was first alerted to the person injecting drugs by a five-year-old and her grandmother.
Boston Scientific hit by cyberattack causing ‘disruptions’ to parts of its business
This year has seen a growing number of medtechs hit by cyberattacks, and now Boston Scientific has become the latest victim. In an SEC filing posted Aug. 26, the medtech giant said it had detected a “cybersecurity incident” the day before. The incident has affected certain parts of its information technology systems, something that “has resulted in a global disruption to the company’s operations.” The incident has hit not just its information systems but also its business applications, which “support aspects of the Company’s operations,” it said in the filing. This includes its ability to process and ship customer orders. Boston Scientific said it is working to restore the systems, but the timeline remains unknown. Related Baylor Genetics hit by cybersecurity attack targeting patient, staff information As the company investigates the incident, it remains unclear how significantly its business will be affected. “Accordingly, the Company has not yet determined whether the incident is reasonably likely to have a material impact.” The company’s shares were down 3.5% in premarket trading as the news broke. This adds another layer of pressure for the medtech, which last month revealed a new global restructuring program that starts this year and is slated to be completed by 2029. The company said at the time that it “does expect some headcount reductions to result from these restructuring activities,” but did not provide any numbers or specify areas where the cuts may be made. It added, however, that new jobs are also set to be “created in areas of growth.” It was also forced to cut its sales guidance in Q2, saying in late July that it now expects full-year 2026 organic revenue growth of 5% to 6%, down from its previous guidance of 6.5% to 8%. Boston Scientific is one of a growing number of life sciences companies, notably medtechs, that have been hit by cyberattacks this year. These include Abbott, iRhythm, Medtronic and Stryker, as well as Big Pharmas Amgen and Novo Nordisk.
Youth football coach relieved of duties after incident at Center Point sports park
It is not immediately known what the incident that occurred was.
Centralia Police warn businesses after gift card scam attempt
Centralia police are warning local businesses about a scam after officers were notified Saturday night of an incident targeting a business in town.Police said s
41,000 HUSKY Health members impacted in second security incident this year, DSS says
For the second time this year, the Connecticut Department of Social Services is notifying HUSKY Health members about a security incident involving a Medicaid provider portal. The latest incident affects approximately 41,000 HUSKY Health members after an unauthorized person accessed certain claims and payment information through a provider’s account. The last incident happened in March, and an unauthorized user gained…
Montrose business targeted twice in less than a week in copper wire theft attempts
A Houston dessert shop owner says her business was targeted twice in less than a week by people trying to steal copper wiring. Doorbell camera video shows both of the incidents — leaving her with electrical damage, a power outage and thousands of dollars in lost inventory.
KSU, Technovative AI sign pilot agreement with Moultrie Police Department for AI-powered behavioral health detection tool
Technovative AI, Inc. and Kennesaw State University today announced a pilot agreement with the Moultrie Police Department to deploy CaseFinder, an AI-powered behavioral health detection platform that analyzes police incident reports and 911 call transcripts to identify individuals in behavioral health crisis who would otherwise go undetected.
Saints, Cowboys Joint Practice Erupts Into Multiple Brawls
What was supposed to be a productive joint practice between the New Orleans Saints and Dallas Cowboys quickly turned chaotic Tuesday as tensions boiled over into multiple fights. At least six separate altercations broke out during the session, disrupting practice and drawing the attention of both coaching staffs. Players exchanged punches and, in one incident,…
Uli Hoeneß on Musiala health scare: "I go to bed thinking of him"
In an interview with RTL/ntv, Bayern chief Uli Hoeneß revealed that he was “shocked” when Musiala suffered another collapsing incident just days apart. "I was speechless. I go to bed thinking of...
Yankees prospect Core Jackson addresses past mistakes
Somerset infielder Core Jackson addressed past incidents that drew national attention and said growth, accountability and baseball define him today.
Governor Newsom secures federal disaster assistance for small businesses impacted by Boyle Heights warehouse fire
What you need to know: Governor Gavin Newsom today announced that low-interest federal disaster loans are now available to help small businesses and private nonprofit organizations recover from economic losses caused by the 2026 Los Palos incident, also known as the Boyle Heights warehouse fire, in Los Angeles. SACRAMENTO – Governor Gavin Newsom today announced that the […]
Salt Lake City offers to reimburse businesses hit by property crime
Some business owners in Salt Lake City have reported incidents of vandalism and security challenges.
Aesto Health Data Security Incident Affects Multiple Healthcare Provider Clients
A data breach at Aesto Health, a Birmingham, Alabama-based healthcare technology company, has affected several of its healthcare provider clients. Aesto A security incident at the Alabama healthcare technology company Aesto Health has affected at least 27 of its healthcare provider clients and exposed the protected health information of hundreds of thousands of patients.
Jalen Carter Shares Health Update After Enormous Contract Extension
The Philadelphia Eagles took on at least some modicum of risk back in 2023 when they moved up one spot to the ninth overall pick to select Jalen Carter out of Georgia. Whilst phenomenally talented, after a car-incident that resulted in the deaths of two students and saw Carter himself serve 12 months of probation […] The post Jalen Carter Shares Health Update After Enormous Contract Extension appeared first on HEAVY.
Multiple employees hospitalized after incident at Hudson industrial businesses
Several employees at an industrial business in Hudson were brought to area hospitals with various symptoms Thursday morning, prompting a hazardous materials response.
Hazmat incident at Hudson business sends 16 people to hospitals
Sixteen people were hospitalized at an industrial business in Hudson, Massachusetts, on Thursday, fire officials said. A chemical process is believed to have contributed to what happened, according to the Hudson Fire Department, which called in a Hazardous Materials team to help respond to the incident, reported about 8:47 a.m. on Parmenter Road. Employees at the business reported serious illnesses,…
'Chemical process' at Hudson MA business hospitalizes 16 people
Hudson firefighters responded to what they are calling a "mass casualty incident" on Parmenter Road.
16 people hospitalized following chemical Hazmat incident at Mass. industrial business
Over a dozen people were hospitalized after a chemical incident at a Massachusetts industrial business made workers seriously ill.
UF Health doctor dies in custody at Alachua County Jail
Incident occurs Thursday morning.
Deep learning shines at predicting incidental lung nodules' severity
Experts believe AI's performance on a diverse dataset gives it an edge over other prediction models in real world settings.
Rashee Rice: Jail time was "learning experience" and "reality check"
Chiefs receiver Rashee Rice had an unexpected 30-day offseason jail stint, due to a positive THC test while on probation for felony charges arising from a 2024 street-racing incident.
Man stabbed in face after argument inside business
Officers said the incident occurred around 7:30 p.m. in the 1200 block of South Saratoga Street.
Crash closes southbound U.S. 41 Business in Venice
The incident happened about 6:45 a.m. at the intersection of U.S. 41 and San Marco Drive.
Blocked storm drains blamed for Ringgold flooding, but some businesses remain uncertain
Downtown Ringgold business owners were able to get some answers Monday night as they continue to recover from two flooding incidents last week.Questions remain
Long list of embarrassing WNBA incidents is what happens when sports leagues made politics their primary focus
From Caitlin Clark's treatment to Sophie Cunningham's stance on trans athletes, the WNBA's political battles are overshadowing the sport itself.
Long list of embarrassing WNBA incidents is what happens when sports leagues made politics their primary focus
From Caitlin Clark's treatment to Sophie Cunningham's stance on trans athletes, the WNBA's political battles are overshadowing the sport itself.
The world's leading AI companies struggle to contain latest models
There's been a recent string of cybersecurity incidents among the world's leading AI models. Here's a look at what's happened.
Speeding driver plows through South St. Louis County sidewalk, foot from crashing into a business
St. Louis County Police said the incident happened around 2:40 a.m. Aug. 7. The driver admitted to speeding and losing control to officers on the scene, according to a statement from police.
Science on Tap: The Evolution of NEST
What does it take to prepare for the nation’s most challenging nuclear and radiological emergencies?Discover the answer with the Nuclear Emergency Support Team (NEST), the National Nuclear Security Administration’s elite emergency response unit composed of leading scientists and technical experts.Join Michael Peters, NEST Director and Deputy Director for the Office of Nuclear Incident Response, as he takes audiences on a journey through the history of nuclear response in the United States. Explore the pivotal moments that shaped NEST, learn how the organization has evolved to stay ahead of emerging threats, and gain insight into the innovative approaches that continue to strengthen national security today.Whether you're interested in science, history, technology, or emergency response, this presentation offers a unique perspective on one of the nation's most important missions.Event Details:Friday, September 4, 2026 | Doors Open at 5:30 pm | Presentation at 6:00 pmLocation: National Museum of Nuclear Science & HistoryAdmission: $12 per personRequirement: Must be 21+ to attend. An adult must accompany younger guests.
Disturbing online incident involving Perez Hilton prompts renewed talk about mental health
A recent incident on TikTok is serving as a good reminder to talk to your kids about mental health.
VA accelerates electronic health record rollout
After years of delays, the Department of Veterans Affairs says its federal electronic health record (EHR) program is now firmly back on track. VA Secretary Douglas Collins has accelerated the program with a renewed goal: full deployment across all VA medical centers by 2031. A major governance overhaul, replacing multiple competing councils with a single decision-making body, has cut through bureaucratic delays and allowed the VA to move faster and more consistently. Deputy Secretary Paul Lawrence has taken a hands-on role, including visiting deployment sites and holding daily meetings with Oracle Health to ensure front-line clinicians have what they need. Here’s how the rollout is going, according to the VA: The federal EHR has only experienced four outages since December 2025. The system has gone nearly two consecutive years without a major incident. It is currently live at six sites, supporting care for over 188,000 veterans. The system creates a lifelong medical record, integrating data across the VA, the Department of Defense and private community providers. With the first new deployments underway and four Michigan medical centers already live in 2026, the VA is entering its first true expansion phase since the program’s reset. Officials say the system’s improved stability, streamlined governance and standardized national workflows have cleared the obstacles that once stalled progress. With 13 sites scheduled for deployment in 2026 and a market‑based rollout strategy guiding future waves, the department believes it’s finally positioned to move at scale toward a modern, fully interoperable EHR, advancing steadily toward its goal of reaching every VA medical center in five years.
4 men stabbed in central London, woman arrested amid mental health incident: Police
Four men were stabbed in London’s busy Covent Garden, police say. A 47-year-old woman was arrested, scissors were recovered, and officers say early signs point to a mental health-related incident.
4 men stabbed in central London, woman arrested amid mental health incident: Police
Four men were stabbed in London’s busy Covent Garden, police say. A 47-year-old woman was arrested, scissors were recovered, and officers say early signs point to a mental health-related incident.
4 men stabbed in central London, woman arrested amid mental health incident: Police
Four men were stabbed in London’s busy Covent Garden, police say. A 47-year-old woman was arrested, scissors were recovered, and officers say early signs point to a mental health-related incident.
OpenAI reported 2 more incidents of rogue AI agents
External parties reported that OpenAI's AI agents had gone rogue during their evaluations.
Scott Eastwood reveals what he said to Shia LaBeouf during onset fight
Scott Eastwood detailed a tense ‘incident’ that occurred with Shia LaBeouf while filming the 2014 World War II movie ‘Fury.’
Novant Health investigates suspicious intruder at medical center
The incident occurred on July 25 and prompted a response from the Matthews Police Department.
How repeated burglaries left a Grant Park business owner facing $30K in losses
A Grant Park smoke shop owner faces over $33,000 in total damages and stolen goods following two separate break-in incidents.
Crash investigation underway after pole knocked over in Lower Merion, Montgomery County
According to investigators, the crash stemmed from an incident that began in Delaware County, but not much more information has been released at this time.
Iran Considered Retaliatory Strike on Ukrainian Seaport
A flurry of diplomacy has eased tensions, officials said, after an incident risked triggering a wider war.
3 years ago an Israeli hospital modeled extreme disaster response. Here are 4 takeaways for US healthcare.
Hospital leaders who want to be ready should a mass casualty incident arise nearby would do well to look for insights—and inspiration—from Samson Assuta Ashdod Medical Center.
Armed person in mental health crisis parked outside Mansfield police station, police say
Mansfield police are asking residents to avoid the police station due to an active incident.
Dana White decries UFC broadcast production again: ‘Brutal’
UFC CEO Dana White continues to publicly criticize the production quality of his promotion’s broadcasts. Earlier this month, following UFC 329, White took aim at his producers after another high-profile incident of misidentifying a celebrity attending the event. While showing an image of Shakur Stevenson, a boxer who was recently signed to the boxing promotion…
Vanderbilt Health warns about ‘data security incident’ potentially involving patient info
Vanderbilt Health announced Friday that it’s notifying “a limited number of patients” about a data security breach from earlier this year.
White House Correspondents’ Association hosts rescheduled dinner nearly 3 months after shooting incident
Trump to deliver ‘unifying yet vicious’ remarks at press dinner months after shooting incident, White House says
The president, first lady and top administration officials had to be evacuated and the April dinner canceled after a heavily armed man rushed past security.
OpenAI claims its artificial intelligence gained access to the Internet on its own and breached a ‘partner’
The technology company claims the incident stemmed from a cybersecurity test gone wrong, where its application escaped a closed environment and broke into an external database to complete its task of being an elite hacker
Woman accused of breaking items in Manhattan business
Incident reported in 1900 block of Little Kitten Avenue.
Attempted kidnapping, break-in at day care likely tied to mental health issues, docs say
Two separate incidents, which according to court documents, are likely related to mental health issues and drug psychosis.
🚨 For now: FIFA will NOT sanction Leandro Paredes
It has been confirmed that Leandro Paredes will not receive any sanction from FIFA following the incidents in the World Cup Final, where he struck Eric García in the throat. According to the BBC, th...
MLB fan slaps spectator for sitting during national anthem in viral video
The incident went viral on Sunday.
Jose Caballero's "routine'' sparks Yankees-Pirates bench clearer
Pirates' reliever Dennis Santana's overreaction to Jose Caballero's habitual, but legal, stall tactics at the plate led to an eighth inning incident.
Safety fears limit Ebola response in Congo, with more than 12 attacks on health facilities and workers recorded
Many of the attacks have been carried out by angry mobs who have stormed treatment centers or targeted response teams in the field, Pierre Akilimali, incident manager for the Ebola response, said at a press briefing.
Abbott investigates two separate cyber incidents, says no operations affected
Abbott Laboratories is investigating two cyber incidents involving unauthorized access to some internal systems at its cancer diagnostics business and its LabCentral portal, the company said on Friday, adding that its operations were not affected.
White House defends Argentina team over Falklands banner
The comments could further fuel the row over the incident, which has seen Downing Street back calls for Fifa to investigate.
Sources: Silver persuaded Engelbert to suspend Thomas after Clark incident
WNBA Commissioner Cathy Engelbert was not going to suspend Alyssa Thomas for burying a fist onto Caitlin Clark’s throat three weeks ago until NBA Commissioner Adam Silver implored her to reverse course and issue a suspension, multiple sources told SBJ Tuesday.
Sources: Silver persuaded Engelbert to suspend Thomas after Clark incident
WNBA Commissioner Cathy Engelbert was not going to suspend Alyssa Thomas for burying a fist onto Caitlin Clark’s throat three weeks ago until NBA Commissioner Adam Silver implored her to reverse course and issue a suspension, multiple sources told SBJ Tuesday.
An ICE Shooting in Maine Puts Pressure on Senator Susan Collins
The Democrats hoping to challenge Ms. Collins, a vulnerable Republican, have seized on the fatal incident, drawing attention to her record on immigration matters.
Shah calls out Collins for votes on ICE funding, leadership
In response, Collins’ spokesperson Blake Kernen said Collins has negotiated funds for body cameras and de-escalation training. In addition, she’s increased by 17% funds for investigations into the types of incidents that occurred Monday in Biddeford.
Fatal ICE shooting in Maine comes just days after similar incident in Texas
Monday’s ICE-involved killing in Maine is at least seventh instance of a person shot dead during immigration enforcement operations since January 2025
Country music star shares young daughter’s health scare: ‘We thought we had lost her’
The incident took place just two weeks after teh 12-year-old had heart surgery.
Draymond Green Calls Out Udonis Haslem Over Miami Heat Altercation
Draymond Green used Udonis Haslem to chime in on the incident between ex-Miami Heat teammates Bam Adebayo and Tyler Herro
Democratic congressman says he was detained in the West Bank
The Israeli Defense Forces denied detaining any visitors in the incident
North Haven man arrested after stabbing, robbery at Groton business
GROTON, Conn. (WTNH) — A North Haven man was arrested Thursday in connection with a combined stabbing and robbery incident at a business in April, according to the Town of Groton Police Department.…
McConnell was loaded into ambulance on a stretcher, according to eyewitness and new video
Emergency responders took Sen. Mitch McConnell to an ambulance on a stretcher after being called to his home last month for a report of an unconscious person, according to new video of the incident and an eyewitness account.
Ebola: Misinformation fuels violent attacks on health workers
BBC Verify looks at multiple incidents linked to misinformation during latest Ebola outbreak, which has infected more than 1,700 people and killed 580 in DR Congo since mid-May.
The Ozempic and Wegovy mistake sending thousands to poison control
Poison control calls involving semaglutide (Ozempic and Wegovy) soared after the drug was approved for weight management, with researchers linking the increase to accidental dosing mistakes rather than intentional misuse. Simple education about proper weekly dosing and gradual dose increases could help prevent many of these avoidable incidents.
Katie Couric suffers stroke scare, diagnosed with temporary amnesia
Katie Couric, 69, reveals she recently had a ‘freaky’ incident that turned into a stroke scare before she was ultimately diagnosed with temporary amnesia.
World Of Warcraft Plague Kills Players, Makes Infected Spread Nasty Green Goo
World Of Warcraft's 'Corrupted Blood Incident 2.0' resulted in the game getting even more toxic than usual
Douglas police arrest suspect linked to multiple business burglaries
The Douglas Police Department arrested a suspect following burglaries at two businesses, according to police. The first incident occurred July 4 at a business on South Peterson Avenue. Officers responded to an alarm after the business owner reported seeing a suspect on surveillance cameras attempting to force entry into the building.
India investigating Tata data leak that exposed Apple iPhone secrets
India is investigating a data breach at Tata Electronics that exposed documents linked to Apple's unreleased iPhone 18 Pro, the country's IT secretary said on Thursday in the government's first public comments on the incident.
China says man who flew plane into Beijing skyscraper had mental health problems
Official statement offers the most detailed official account yet of the highly unusual and fatal incident in Beijing
MLB suspends Red Sox's Willson Contreras, Nationals pitcher Cade Cavalli, others after benches-clearing incident
New mobile health clinic launches in Boyle Heights for residents affected by warehouse fire
A new mobile health clinic has launched in Boyle Heights to provide medical services to residents affected by the warehouse fire, as some community members continue to report health concerns tied to the incident.
Mitch McConnell has had freezes, falls and health scares. See timeline
Sen. Mitch McConnell has had multiple freezes, falls and health scares in recent years. See the timeline of when these incidents occurred.
Seth Rogen shares awkward moment with 'Lion King' collaborator Pharrell Williams at dinner party (exclusive)
'The Invite' star Seth Rogen is recounting an incident where Pharrell Williams confronted him at a dinner party over Rogen's 'Lion King' interviews.
Lionel Richie's ex-wife shares update on singer's condition after hospitalization
Lionel Richie's ex-wife, Brenda Harvey Richie, shared news on her former husband's health after a medical incident led to a concert stoppage and hospitalization.
A New Way to Uncover How Science Is Under Attack
Science is being threatened at a pace and scale we’ve never seen before in the federal government. It’s nearly overwhelming—but we’ve built a new system to help us monitor and explain what’s happening, looking both incident by incident and at the larger pattern. Last week, the Union of Concerned
Nancy Pelosi, Connie Chan condemn Scott Wiener harassment incidents
Chan and Pelosi did not sign onto a letter condemning the incident captured in a viral video, but spoke out against harassment in statements to the Chronicle.
Concerns with the Sebastian County Sheriff’s office
The recently-surfaced video showing the potential maltreatment of a Sebastian County Jail inmate, and a subsequent statement about the troubling incident from interim Sheriff Mike Conger point to the need...
Americans keep poisoning themselves with semaglutide, other weight loss drugs
These incidents became much more common after the FDA started approving GLP-1 drugs for chronic weight management in 2021.
We have an epidemic of political violence in this country: National Review columnist
National Review columnist Caroline Downey discusses growing political violence and criticizes Illinois Gov. J.B. Pritzker for his remarks about the Chicago cross-burning incident.
We have an epidemic of political violence in this country: National Review columnist
National Review columnist Caroline Downey discusses growing political violence and criticizes Illinois Gov. J.B. Pritzker for his remarks about the Chicago cross-burning incident.
Lionel Richie reportedly hospitalized after medical incident forced concert to end early
Lionel Richie has reportedly been hospitalized after a medical incident on stage forced him to sit down to sing a song on the opening night of his tour with Earth, Wind & Fire.
In wake of homicide on Tyler Street, nearby business owners reaffirm faith in community
In the aftermath of last week’s homicide on Tyler Street, local business owners in the area told The Eagle that the incident is not representative of the neighborhood’s character.
Jon Stewart blames JD Vance's Iran negotiations failure on a nose-picking incident: 'Classic diplomatic faux pas'
'The Daily Show' host Jon Stewart blames the failure of Vice President JD Vance's Iran negotiations on a nose-picking incident seen in viral video: 'Classic diplomatic faux pas.'
Bardstown Road businesses call for change following fights, shootings
The mayor’s office says it is exploring more options to crack down on crime after a string of incidents on Bardstown Road.
Police investigating incident at Midland business
The Midland County Sheriff’s Office is investigating an incident at a business near N County Road and Highway 80.
Giants downplay Rafael Devers incident late in third consecutive loss
MIAMI — Once again, Rafael Devers is stirring up drama. This time, the Giants first baseman, who refused to play the position with the Red Sox, again tried to stand...
The Science Behind Aldi's Exploding Turkey Burger Scandal
A few years ago Aldi had to contend with a lawsuit regarding an exploding turkey burger. Here's the science behind why that incident unfortunately occurred.
Italian foreign minister cancels trip to US over Trump’s comments about Meloni
US President Donald Trump’s comments to an Italian media outlet about the country’s Prime Minister Giorgia Meloni have sparked a fresh diplomatic incident.
Waymo recalls nearly 4,000 robotaxis after cars enter freeway work zones
Waymo has paused freeway robotaxi operations and recalled nearly 4,000 vehicles after more than a dozen incidents involving autonomous cars entering closed construction zones.
Healthcare AI vendor suffers data breach, exposing patient records to hackers
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.