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Stuart Gilly on leading through uncertainty: Why moving forward is the key
In June’s episode of “Strictly Business”, entrepreneur, investor and leadership coach Stuart Gilly shared a powerful message about leading through uncertainty. His central insight is that great leaders are not defined by certainty, but by their willingness to move forward when certainty is impossible. Gilly’s leadership journey began at age 15 when he started a […]
iPhone Ultra final design shared by Apple’s nemesis
Despite the ongoing legal battle, leaker Jon Prosser has been active in sharing leaks and renders for upcoming iPhone models. His latest could very well be the final version of the iPhone Ultra.
'It's Going To Be Pretty Brutal' - Jason Schreier Reveals More On Upcoming Xbox Layoffs
The Bloomberg reporter has published a new 30-minute video
Marvel Rivals - The Super Hero Team-based PVP Shooter
Play for free Now!! Get ready to Ignite the Battle with Marvel Rivals!
Science, Public Health, and the Politics of Truth
Presented as part of the McCloskey Speaker Series.Peter Hotez, M.D., Ph.D., professor and dean of the National School of Tropical Medicine at Baylor College of Medicine, joins the Aspen Institute for a keynote lecture on the intersection of science, medicine, and public trust. A leading authority on vaccines and neglected tropical diseases, Hotez reflects on the challenges facing public health today, the growing politicization of science, and what it will take to rebuild trust in scientific institutions in the years ahead.Paepcke Auditorium, doors at 5:00 pmRegistrationThis event is free and open to the public, but registration is required, and capacity is established on a first-come, first-served basis. Once an event is at capacity, we will have an in-person waitlist at the door.Public registration is now open for summer 2026. Please click here to register.ParkingParking is very limited. Please carpool, walk, bike, or ride RFTA.Book signing will immediately follow the event. To learn more about his book or to order a copy, please click here.
Science, Public Health, and the Politics of Truth
Presented as part of the McCloskey Speaker Series.Peter Hotez, M.D., Ph.D., professor and dean of the National School of Tropical Medicine at Baylor College of Medicine, joins the Aspen Institute for a keynote lecture on the intersection of science, medicine, and public trust. A leading authority on vaccines and neglected tropical diseases, Hotez reflects on the challenges facing public health today, the growing politicization of science, and what it will take to rebuild trust in scientific institutions in the years ahead.Paepcke Auditorium, doors at 5:00 pmRegistrationThis event is free and open to the public, but registration is required, and capacity is established on a first-come, first-served basis. Once an event is at capacity, we will have an in-person waitlist at the door.Public registration is now open for summer 2026. Please click here to register.ParkingParking is very limited. Please carpool, walk, bike, or ride RFTA.Book signing will immediately follow the event. To learn more about his book or to order a copy, please click here.
A first look at ‘Apocalypse Z 2,’ the upcoming post-apocalyptic action sequel coming to Prime Video this Halloween
The highly anticipated second installment in the ‘Apocalypse Z’ movie franchise releases worldwide this Halloween.
Jay Bilas recalls NFL tryout offer after college basketball career
During his interview with @EdEastonJr, ESPN Analyst Jay Bilas recalled his NFL tryout offer after concluding his college basketball career
Samsung Galaxy Z Fold 8 Ultra: The Foldable We’ve Been Waiting For
Recent FCC filings confirm the upcoming Samsung Galaxy Z Fold 8 lineup, highlighting a new Wide model and more.
Baton Rouge General's Health Tip of the Week: The return of the flesh-eating screwworm
Sponsored by Baton Rouge General The new world screwworm, a flesh-eating parasite once eradicated from the U.S., is making headlines again. Recently detected in a calf in Texas, the screwworm, which is not a worm at all, is raising concern among public health officials. Female flies lay their eggs in open wounds or mucous membranes […]
World Cup Day 7 What to Watch: Tournament favorites Portugal and England begin their campaigns
“The Five Star Weekend” boss on which role was 'hardest' to cast
Peacock's upcoming adaptation of Elin Hilderbrand's best-selling novel stars Jennifer Garner, D'Arcy Carden, Regina Hall, Chloë Sevigny, and Gemma Chan.
“The Pitt” cast officially clocks back in for start of season 3 production
The HBO Max drama's next batch episodes will be set in November.
NFL, NFLPA, NBPA tell Congress they back college sports bill
The NFL, NFLPA and NBPA on Tuesday sent statements to Congress supporting the Protect College Sports Act and lauding specific provisions it includes while also encouraging further "negotiations" during the legislative process.
Planning Ahead Can Actually Make You Happier—Here's the Science Behind It
Research shows that simply having something to look forward to—big or small—can meaningfully boost your sense of well-being.
Merchants of Doubt and the attacks on Extreme Event Attribution science
Last week, I attended a meeting at Columbia University on attribution science and climate law, hosted by the Sabin Center. It was a fantastic event, bringing together scientists and legal experts working at the intersection of extreme event attribution and climate law. Subscribe For those unfamiliar with it, extreme event attribution attempts to quantify the contribution of climate change to an extreme event. For example, several groups analyzed the impact of climate change on Hurricane Harvey’s enormous rainfall totals over Houston, Texas and they found that climate change increased rainfall by 15 to 38%. One thing that came up again and again was how terrified fossil-fuel interests are of extreme event attribution science. They are acutely aware that this research could land them in court. And losing those cases would leave them legally liable for billions of dollars in climate damages. Because the legal stakes are so high, the blowback has turned ugly. I spoke with several scientists at the meeting who are facing ongoing harassment over their work. This blowback is a coordinated campaign to make the entire field look suspect. The goal is to create the impression that attribution science is too uncertain, too political, or too conflicted to be useful in court or in public policy. The strategy is not based on actual science or evidence of misconduct, but on the generation of doubt. The new Merchants of Doubt We’ve seen this before. In fact, not that long ago: We only have to go back a year to the Department of Energy (DOE) Climate Working Group (CWG) report to see an example of using doubt as the tool to push back against well-established science. This strategy is laid out in an email from a member of the CWG, Dr. Roy Spencer, that was released during litigation over the Climate Working Group process. The key quote is: About all I can hope is that what we write will provide sufficient “reasonable scientific doubt” regarding the science claims in the 2009 TSD [technical support document], based upon almost 2 decades of new science, to call into question the original reasoning for the EPA Administrator’s decision that CO2 presents a threat to human health and welfare. This statement is strong evidence that at least some members of the committee were working to support a particular policy outcome: revoking the Endangerment Finding. The email also explains how they planned to do it: by attempting to generate “reasonable doubt”. This is going to be hard, Spencer implies. Despite falsely claiming that “2 decades of new science” weakens the case, Spencer explicitly acknowledges that the actual peer-reviewed science of climate change overwhelmingly rejects his position: But if the science argument is decided upon by a vote, or by the number of published citations, we lose the science argument. We can go back even further: This CWG email shares unmistakable DNA with the infamous 1969 tobacco memo that declared: “Doubt is our product, since it is the best means of competing with the ‘body of fact’ that exists in the mind of the general public. It is also the means of establishing a controversy.” The tobacco memo also acknowledges the limit of this strategy: Like the CWG, they knew the science was not on their side. Share The new new Merchants of Doubt The people attacking the IPCC chapter on extreme event attribution are the newest iteration of the Merchants of Doubt. Their goal, like all Merchants before them, is to introduce doubt into the process. Because the report is not even out yet, they cannot attack its conclusions. So they are attacking the authors instead. Here is a press release from the House Science, Space, and Technology Committee: In the letter, the Chairmen express concerns about potential conflicts of interest involving members of the Attribution Committee, stating that “publicly available information suggests a troubling pattern” in which committee members are affiliated with nonprofits that support climate accountability lawsuits, “raising the appearance of impropriety and member bias.” To be clear, this is just innuendo. There is no actual evidence of bias. And given the robust process that these reports go through, including multiple lines of peer review, it seems very unlikely that significant bias can survive into the report. When the report comes out, critics will have the opportunity to make legitimate criticisms of the report — if any exist. If none do, however, they’ll still make criticisms, but they’ll be bogus, simply designed to generate doubt. We’ll see. A note to the press: Fix your frame To any journalists reading this: The public debate over extreme event attribution science is not going away. The science is simply too dangerous to fossil-fuel interests for them to stop fighting it. You very well might be assigned to write an article about this area of research in the future. When you do, do not automatically adopt the framing that climate misinformers want you to use. They want you to frame the story around questions like: Are climate scientists trying to put their thumb on the scale to achieve a predetermined, politically motivated result? Are climate scientists improperly letting their politics invade the science of the IPCC? That frame is a trap. Instead, you need to view this through the historical lens of the Merchants of Doubt. How does the ecosystem of doubt operate? Who funds it? What methods do they use to misrepresent science and slime researchers? What scientific results are they trying to keep people from understanding are legitimate? Ultimately, you instead need to focus your article on the generation of doubt as a way to maintain the fossil fuel industry’s social and legal license to keep burning oil, gas, and coal. If you treat the misinformers’ frame as a legitimate, good-faith scientific critique, you are helping them produce doubt. Don’t do it. Don’t be a Merchant of Doubt. Thanks for reading The Climate Brink! Subscribe for free to receive new posts and support our work. Subscribe other stuff The Staying Curious Substack has an interesting post about the different flavors of climate sensitivity. This is crucial information if you want to understand how scientists think about how much warming the Earth will experience. I’d be grateful if you could hit the like button ❤️ below! It helps more people discover these ideas and lets me know what’s connecting with readers.
“The Five Star Weekend” cast on how women are 'siloed' away from each other in Hollywood — but not on their show
Jennifer Garner, Gemma Chan, Regina Hall, D'Arcy Carden, and Chloë Sevigny star in the upcoming Peacock series based on Elin Hilderbrand's best-selling novel.
Cameron Jordan announces the 2026 season will be his last
Aaron Rodgers isn't the only veteran player who knows the upcoming season will be his last.
Exploring the Current Boundaries of AI for Science at TPC26
Last week’s TPC26 event brought together many of the world’s preeminent experts in using AI for science and engineering. The conference demonstrated that we have come quite far in just […]
Steam Machine one step closer to launch as benchmarks surface online, here’s how it compares to the Steam Deck
We can now have an early look at some Steam Machine benchmarks after results were uploaded to Geekbench, suggesting reviews are underway.
Microsoft weighs DeepSeek for Copilot Cowork
Microsoft will also shift to usage-based pricing for the enterprise agent.
Apple Plans Camera AirPods Alongside Upgraded Foldable iPhone in 2027
Apple Inc.’s upcoming camera-equipped AirPods, a product meant to vault the company into the AI device market, is scheduled to launch in late 2027 as part of a flurry of new releases.
5 things to do this week in Greenville
See our curated list of upcoming and ongoing arts, culture and entertainment events in the Greenville area. Send us your events at greenville@postandcourier.com.
Financing, regulatory concerns stall SunGas’ Louisiana biofuels ambitions
SunGas Renewables has halted development of its Beaver Lake Biofuels Project near Alexandria, ending plans for a major renewable fuels facility that would have converted sustainably sourced wood fiber into low-carbon methanol, 10/12 Industry Report reports. The project was expected to produce more than half a million metric tons of methanol annually while capturing and […]
Why are American politics so volatile?
Both parties are divided. Older issues divide Republicans by education, while newer ones divide Democrats by race.
More than a thousand games in Steam Next Fest feature a generative AI disclosure of some kind
SteamDB offers insight into the true scope of AI's use in the latest PC store promotion.
Xbox Game Pass adds new day-one game today
Xbox Game Pass subscribers can play Stormcloud Games' 3D action-platformer Junkster today, as it launches into the service for console and PC.
After resurrecting an iconic PC brand, Commodore is getting into flip phones
It’s $499, it’s beige, and it’s hoping to get you off your smartphone.
Yankees news: Rice, Caballero go deep to take Toronto series
Yanks win first series in Toronto since 2023; no catching “yet” for Rice; Dominguez’s long day ends in long ball; remembering Al Closter.
Stop managing your business finances in spreadsheets — QuickBooks is $300 right now
Intuit QuickBooks Desktop Pro Plus 2024 is on sale for $299.99 (reg. $536) for one year. Built for small business owners, freelancers, and accountants, it handles invoicing, expense tracking, inventory, payroll hours, and project profitability reporting.
OPCW and UNODA partner to bridge gap between scientists and policymakers
Scientists learn how to apply policy and diplomacy at OPCW-UNODA workshop on chemical and biological disarmament
Joe Rogan makes bold declaration about UFC Freedom 250
UFC commentator Joe Rogan had some lofty praise for the company's Freedom 250 card on Sunday night.
“Gilmore Girls ”is leaving Netflix after 12 years
Raise your cozy coffee mugs in tribute.
Community Conversations: Black Business Expo to showcase local black-owned businesses
Dave Hunter spoke with Sharmain Cooper-Richardson about the upcoming Black Business Expo.
SpaceX aquires SPCX ticker from ETF firm in unusual deal
Tuttle Capital Management CEO and CIO Matthew Tuttle discusses selling the SPCE ticker to SpaceX on 'The Claman Countdown.'
Siouxland company L.G. Everist marks 150 years in business
One of Siouxland’s oldest companies is celebrating their 150 years of business in coal and mining.
United is blocking middle seats on its new Airbus A321XLRs
The new premium-economy set-up resembles a "Eurobusiness" class and will likely come at an upcharge.
Steam Next Fest June 2026: Here Are The Featured PC VR Demos
Steam Next Fest starts today, and here's a full list of new PC VR demos available.
The Relic: First Guardian launches July 31 for PS5 and PC, later this summer for Xbox Series and Switch 2
Dark fantasy Soulslike action RPG The Relic: First Guardian will launch for PlayStation 5 and PC via Steam on July 31, followed by Xbox Series and Switch 2l later this summer, publisher Perp Games …
Here Are Monday’s Best Wall Street Analyst Research Calls: Accenture, Caesars Entertainment, Datadog, Dupont, Epam Systems, Ferrari, Paychex, Rocket Lab, TeraWulf, and More
Pre-Market Stock Futures: Futures are exploding higher on news of a peace deal with Iran expected to be signed this Friday. This follows a historic Friday that saw the coming-out party of Space Exploration Technologies (NASDAQ: SPCX), widely known as Elon Musk’s SpaceX. The record-breaking size of the offering, raising $75 billion, the company’s debut ... Here Are Monday’s Best Wall Street Analyst Research Calls: Accenture, Caesars Entertainment, Datadog, Dupont, Epam Systems, Ferrari, Paychex, Rocket Lab, TeraWulf, and More
Here Are Monday’s Best Wall Street Analyst Research Calls: Accenture, Caesars Entertainment, Datadog, Dupont, Epam Systems, Ferrari, Paychex, Rocket Lab, TeraWulf, and More
Pre-Market Stock Futures: Futures are exploding higher on news of a peace deal with Iran expected to be signed this Friday. This follows a historic Friday that saw the coming-out party of Space Exploration Technologies (NASDAQ: SPCX), widely known as Elon Musk’s SpaceX. The record-breaking size of the offering, raising $75 billion, the company’s debut ... Here Are Monday’s Best Wall Street Analyst Research Calls: Accenture, Caesars Entertainment, Datadog, Dupont, Epam Systems, Ferrari, Paychex,
Electronic Arts Introduces EA Advertising, Launching Brands Directly Into Gameplay and Live Experiences
Connecting brands to highly engaged audiences through an exclusive EA SPORTS Partner Program, in-game integrations, creative partnerships, and scalable advertising capabilities across EA’s global portfolio Electronic Arts Inc. (NASDAQ: EA), the global leader in interactive entertainment, today announced the launch of EA Advertising , a new platform transforming how brands connect with audiences through digital and real-world experiences across its global portfolio of games. EA sits at the intersection of entertainment, sports, technology, music, and culture. Across console, mobile, and PC, our games and services reached more than 120 million players 1 each month during fiscal year 2026. Together, this scale and frequency of engagement create meaningful opportunities for brands to connect with audiences through authentic, interactive experiences. EA SPORTS is one of the largest interactive sports platforms in the world, connecting hundreds of millions of players across console, PC, and
Ultimate Marvel vs. Capcom 3 just received its first significant patch in nearly a decade on Steam, but it appears to have broken more than it fixed
A surprise update to Ultimate Marvel vs. Capcom 3 on Steam has broken one of its most powerful characters.
Juneteenth, Mumford & Sons, Westcott Art Trail: 18 things to do this week in CNY
A busy week in Central New York culminates with Father's Day and the first day of summer on Sunday.
From PCOS to PMOS: New name reflects women’s metabolic health
Global multidisciplinary health professionals and organizations have updated the name polycystic ovary syndrome (PCOS) to polyendocrine metabolic ovarian syndrome (PMOS), arguing that the former is “inaccurate.” They critique that the old name implied greater focus on pathological ovarian cysts, contributing to slower diagnosis, stigma, and limited research and policy framing for the 170 million women living with the condition.
Q+A: Faraday Future Moves Beyond EVs
Faraday Future Intelligent Electric Inc. is sizing up for a key pivot. Initially a luxury electric vehicle company, the El Segundo-based manufacturer is
Keir Starmer set to announce under-16s social media ban
Prime minister expected to unveil ‘Australia plus’ ban for under-16s on apps such as TikTok, Instagram and Snapchat
DOKAPON 3-2-1: Super Collection! coming to PC on June 29
Sting will release sugoroku RPG bundle DOKAPON 3-2-1: Super Collection! for PC via Steam on June 29, the developer announced. It will only support Japanese as a language option.
Trump Claims Strait Will be ‘Permanently Toll Free’ Under Agreement With Iran
In a call to The New York Times, President Trump praised Russia and China’s leaders and described Israel’s prime minister as “a very difficult guy.”
Best laptops coming in 2026 after Computex
From RTX Spark powerhouses to affordable AI PCs, these are the most exciting laptops announced at Computex 2026 that are worth waiting for in 2026.
Teladoc Health (TDOC) Stock Valuation As Analyst Sentiment Improves Despite Expected Earnings Decline
Analyst sentiment shift and near term expectations Teladoc Health (TDOC) is back on investors’ radar after analysts turned more positive in their earnings estimates, even as they still expect a 26.32% year over year decline in the upcoming report. This change in sentiment, paired with a recent 1.44% gain that outperformed key indices, has focused attention on how the company’s virtual care and mental health businesses might shape near term performance. See our latest analysis for Teladoc...
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Steven Spielberg’s “Disclosure Day,” billed as his first popcorn movie in years, launched with $44 million in domestic theaters.
Steven Spielberg's 'Disclosure Day' opens No. 1, while 'Obsession' sensation continues
Steven Spielberg’s “Disclosure Day,” billed as his first popcorn movie in years, launched with $44 million in domestic theaters. “Disclosure Day” opened largely as expected, collecting $92.9 million worldwide over
Steven Spielberg’s ‘Disclosure Day’ opens No. 1, while ‘Obsession’ sensation continues
NEW YORK (AP) — Steven Spielberg’s “Disclosure Day,” billed as his first popcorn movie in years, launched with $44 million in domestic theaters, according to studio estimates Sunday. “Disclosure Da…
Steven Spielberg's 'Disclosure Day' opens No. 1, while 'Obsession' sensation continues
Steven Spielberg’s “Disclosure Day,” billed as his first popcorn movie in years, launched with $44 million in domestic theaters.
Steven Spielberg's 'Disclosure Day' opens No. 1, while 'Obsession' sensation continues
NEW YORK — Steven Spielberg’s “Disclosure Day,” billed as his first popcorn movie in years, launched with $44 million in domestic theaters, according to studio estimates Sunday.
The ‘Galaxy Z Fold 8 Ultra’ has the potential to be a cruel joke
There are actual reasons to get excited about Samsung’s upcoming foldables but, the more I think about it, the more...
Laramie County health and food inspections (6/5/26–6/11/26)
CHEYENNE, Wyo. — The Cheyenne-Laramie County Health Department inspects restaurants, bars, convenience stores, delis, grocery stores, bed and breakfasts
Brandon Marsh Takes Change to Heart
Sometimes success comes from taking the middle of the road. Or of the zone.
Nothing new to report
Truly. Nothing new. Same ol’, same ol’ in this one. A 6-1 loss that felt pre-determined, or determined immediately after Pete Crow-Armstrong homered on the first pitch of the game thrown by Trevor McDonald. PCA continued to be a menace all evening: he collected two more hits, came up a triple shy of the cycle, […]
PS5 Controller's Best Features Are Finally Working Over Bluetooth on PC
Devs do what Sony won't
SAMA launches Black Hole Turbo case with sound-damping panels for around $44
Now available in China for just $44. The Black Hole Turbo measures 473 × 230 × 490 mm and supports ITX, M-ATX, ATX and E-ATX motherboards.
Texas NTS AI, May business changes make Around the Hub Lubbock news
Business Reporter Alana Edgin reviews recent Lubbock area business news and hints at upcoming articles in the weekly Around the Hub column.
Draymond Green on LeBron James' upcoming free agency
Draymond Green of the Warriors made an interesting comment about LeBron James' upcoming free agency.
Side-by-side size comparison of Samsung's upcoming foldable lineup leaked
A new leak reveals alleged screen protectors for Samsung’s Galaxy Z Flip 8, Z Fold 8 and Z Fold 8 Ultra, suggesting a wider, shorter Fold 8 design and clearer differentiation across the foldable lineup. While expectations are high that the Fold models will bring some significant changes, the same cannot be said for the Flip.
Journey brings Final Frontier tour to Heritage Bank Center. See photos
Journey performs at Heritage Bank Center in downtown Cincinnati for their Final Frontier tour.
Cowboys fans give their projection for Dallas defense
What Cowboys fans think of the defensive rebuild for 2026
Trump and Macron will meet over dinner at Versailles palace after G7 summit in France
President Donald Trump and French President Emmanuel Macron will meet over dinner at the Palace of Versailles after the upcoming G7 summit of leading industrialized nations in France
AMD goes after Apple Macbook Neo, says 15 out of 20 top PC games do not even work on Apple system
Ryzen 5 220 comparison uses a 2025 Hawk Point processor.
Official PC Requirements for Gears of War: E-Day Revealed
Microsoft has revealed the official PC system requirements for its new Gears of War game, Gears of War: E-Day.
Court Blocks Censorship and Erasure of American History and Science at National Parks
Injunction Halts Effort to Unlawfully Remove History and Science from Park Displays
AMD Tackles NVIDIA’s $4679 DGX Spark AI PC With Its $3999 Ryzen AI Halo: Now Available With 128 GB Memory For Blazing Fast LLMs
AMD has officially launched its Ryzen AI Halo AI PC, which offers super-fast token throughput at a $3999 price point.
Independent Cascadia? Greater Idaho? Disunited States Look Toward Divorce
At a moment when even the prospects of dialogue seem far-fetched, movements to redraw state lines to link like-minded regions, or even to secede from the union, are gaining strength.
GentleOS, A Simple OS For Your Old PC
Every month or so we bring you a Jenny’s Daily Drivers article, in which we share with you an esoteric OS and try to use it for the everyday work of a Hackaday scribe. As part of that ongoing…
Why is Tupac headlining an upcoming video game?
Gamers and influencers watching Summer Game Fest mostly expressed shock and confusion at the inclusion of the influential American rapper and political activist who died in 1996.
BBB warns Alaskans about businesses pressuring customers to change online reviews
Better Business Bureau representatives are urging consumers to document and report instances in which a business pressures a customer to remove or soften an online review, warning the practice can undermine information people rely on when deciding where to spend their money.
EAST TEXAS POLITICS: Texas ag commissioner contacts White House over USDA screwworm handling
Texas Agriculture Commissioner Sid Miller criticized the USDA’s response to the New World screwworm on this week’s edition of East Texas Politics on East Texas Now with Blake Holland. Smith County Pct. 3 Commissioner J. Scott Herod, a cattle rancher and owner of Cut Beef in Tyler, also appeared on the program. Plus, State Rep. Cody Harris talks data center water usage.
Exploring the Current Boundaries of AI for Science at TPC26
Last week’s TPC26 event brought together many of the world’s preeminent experts in using AI for science and engineering. The conference demonstrated that we have come quite far in just a few years. But it also showed us limits to the use of the technology as it currently exists, as well as possible ways the […]
How to See Which Mac Apps Will Stop Working After macOS Golden Gate
Apple is phasing out support for Rosetta 2, which is a feature that allows Intel-based apps to run on Apple silicon Macs. Rosetta is going to stop working for most apps in macOS 28, and when that happens, apps that use it will stop working. Apple began warning customers and companies about the upcoming sunsetting of Rosetta with macOS Tahoe, and the warnings go even further in macOS Golden Gate.
"It was an emergency acquisition": Former Destiny 2 dev says if Sony didn't buy Bungie, the studio would have been "very close to shutting its doors"
Sony's acquisition of Bungie likely saved the Destiny 2 developer from closure, says one former dev.
William Floyd High School Science Students Win Second Consecutive LI Water Quality Challenge
For the second consecutive year, a team of William Floyd High School science students under the direction of Christopher Orlando were selected as winners in the Long Island Regional Planning Council’s (LIRPC) annual Long Island Water Quality Challenge. The team received a $2,500 grant to implement its proposal at the school, and earned WFHS the recognition of being the first school to earn back-to-back victories in the competition!
Side-scrolling beat ’em up game The Walking Dead: Streets of Survival announced for PS5, Xbox Series, Switch 2, Switch, and PC
New publisher Trailmark Games and The Karate Kid: Street Rumble developer Odaclick Game Studio have announced The Walking Dead: Streets of Survival, a side-scrolling beat ’em game set in the …
How to secure Charli XCX tickets during hectic ‘Music, Fashion, Film Tour’ presale
The 12-date North American tour kicks off in September, with the presale launching today, Friday, June 12.
Ana Navarro revealed what she'll ask JD Vance in VP's upcoming 'View' interview
'The View' cohost Ana Navarro revealed what she wants to ask Vice President JD Vance when the controversial politician visits the talk show next week: 'Several issues,' Navarro explained.
AMD changes rules, denies researcher $10,000 bounty after taking 124 days to patch security flaw
The vulnerability was discovered by security researcher MrBruh after an AMD updater console window kept appearing on his new gaming PC.
City Council Business Meeting on June 16, 2026, at 9:00 a.m.
The Palm Coast City Council meets regularly to discuss and vote on official City business. These meetings are open to the public, and Palm Coast residents are strongly encouraged to attend. An increase in public engagement helps to build a stronger sense of community, increase valuable discussions, and decrease division.
America Is Finally Getting Better Sunscreen. Dermatologists Are Thrilled.
The FDA just approved the first sunscreen filter in more than two decades. Here's why experts are excited.
Galaxy phones are finally getting a feature Android users have wanted for years
Samsung finally adds a network speed meter to Galaxy phones with One UI 9.
Forza Horizon 6 devs address mysterious save file deleting bug, roll out fix for PC ahead of Xbox patch
Playground Games have been scrambling to fix an issue in Forza Horizon 6 that is causing players to lose their save files and all progress.
Summerville council delays vote on downtown entertainment district
Summerville City Council delayed a vote on creating a new outdoor entertainment district that would allow open-container alcohol in downtown.
Men's College World Series preview: 8 players to watch as games begin in Omaha
Weekend Entertainment Roundup for June 11, 2026
Eric Harrison joins LRPR to share upcoming arts and culture events on the weekend entertainment roundup.
Tennessee Building Commission approves Neyland Entertainment District projects
Tennessee’s State Building Commission approved Thursday the University of Tennessee’s upcoming major project aimed at building an entertainment district right outside Neyland Stadium.
SpaceX live updates: Elon Musk's rocket company set to price hyped IPO
SpaceX will price its hugely anticipated IPO on Thursday, setting the stage for SPCX stock to begin trading on Nasdaq on Friday.
SpaceX IPO buyers are betting on an idea, not a business
Market Catalysts host Julie Hyman sits down with Epistrophy Capital Research Chief Market Strategist and The Drill Down podcast host Cory Johnson to discuss the upcoming SpaceX (SPCX) IPO. Johnson breaks down the company's key business segments and weighs in on its valuation. Asked whether he agrees with the proposed $135 IPO price, Johnson expressed caution, saying, "Projections out to the future to get to today's price are really optimistic."
Parker Solar Probe Makes 28th Close Pass of Sun
NASA's Parker Solar Probe completed its 28th close approach to the Sun on June 8, again matching its record distance of 3.8 million miles from the solar