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Everything New in iOS 27 Beta 2
Apple released the second beta of iOS 27 today, and as is common with a second beta, there are multiple changes. There are new features and updates to existing features as Apple prepares for a July public beta and a September software launch. Write with Siri There is a new Write with Siri button above the keyboard in Notes, Mail, Messages, and more. It makes it easier to locate the option to use Siri for writing. In the first beta, the Write with Siri tool was only available when selecting text.
Zane’s Trace Commemoration Continues with Parade, Entertainment and Community Spirit - WHIZ - Fox 5 / Marquee Broadcasting
The second day of the Zane’s Trace Commemoration wrapped up with a full schedule of activities, entertainment and family-friendly fun in Putnam. The day began with a parade and a 5K before crowds gathered at Putnam Park to browse vendors and enjoy a variety of performances throughout the afternoon. What was once an event that had faded away has found...
Gwyneth Paltrow’s health-food restaurant coming to a second San Diego location this fall
The Goop Kitchen restaurant chain is part of Paltrow’s Goop business, which also sells beauty, wellness, clothing and lifestyle products.
iOS 27 Beta 2 Adds Inline Replies to iPhone-to-Android RCS Chats
With the second beta of iOS 27, Apple added support for replying to a specific message in an RCS conversation with an Android user. You can now long press on a message to get to the option to reply, and it works the same way that it does with iMessage. Apple added support for RCS in iOS 18, and has been improving it since then. iOS 26.5 added encryption for RCS messages sent between iPhone and Android users, and now more of the RCS features are being implemented.
Examining the Eagles’ hidden roster strength entering training camp
The Eagles enter training camp with a hidden roster strength in the secondary, where Quinyon Mitchell, Cooper DeJean, and Riq Woolen headline a deep defensive back group.
Apple Seeds iOS 27 and iPadOS 27 Second Betas to Developers
Apple today seeded the second betas of iOS 27 and iPadOS 27 to developers for testing purposes, with the update coming a week after Apple released the first betas following the WWDC 2026 keynote. Registered developers can download the betas from the Settings app on the iPhone or iPad by going to the General section and selecting Software Update. iOS 27 introduces Apple's smarter version of Siri, Siri AI.
Computer science graduate Anthony Burrows set to begin pursuing second bachelor’s in engineering this fall
Burrows, a member of the UMSL’s men’s tennis team, first came to the university as part of a cohort of 20 students from The Bahamas.
Register now for even bigger Run Dollywood race weekend this fall
Runners who want to join in the glittery fun of the second Run Dollywood race weekend - set for this fall - might want to register soon to get a spot.
Rome's 'Fireworks on the Fourth' Returns to Bellamy Harbor Park
Fireworks on the Fourth will return to Bellamy Harbor Park for Rome’s second annual Independence Day celebration.
Monthly BAT Days Initiative Connects Residents to Free Health, Recovery and Support Services
On the second Wednesday of each month, these organizations come together at the Centers for Addiction and Mental Health Programs (CAMP) on Orange Blossom Trail to provide HIV and Hepatitis-C testing, connections to affordable or free primary care providers, mental health resources and case management services.
Politician behind 'top two' primary has second thoughts
The man who brought California the top-two open primary now thinks it needs a drastic overhaul.
Kansas City small businesses say World Cup is hurting sales. There's no bump like the city promised
Kansas City has welcomed thousands of visitors as the metro enters its second week of the World Cup. But as international crowds come in, many local shop owners feel they're taking a backseat. Some small businesses say the economic boost is not evenly distributed.
4 Takeaways From Egypt's Landmark Win vs. New Zealand At The World Cup
Egypt moved to the top of the Group G table with a near-perfect second half in a 3-1 comeback win over New Zealand on Sunday night in Vancouver. Here are four takeaways from the match.
📸 Hossam Abdelmaguid suffers a nasty knock against New Zealand
Hossam Abdelmaguid suffered a shocking blow in the final minutes of Egypt vs. New Zealand, on the second matchday of the World Cup group stage. It happened during an aerial challenge for the ball, w...
Pinterest and SM Entertainment Partner on K-Pop Content With Hearts2Hearts
Pinterest and SM Entertainment have partnered to launch official Pinterest boards tied to K-pop group Hearts2Hearts' second mini album, Lemon Tang, offering fans exclusive behind-the-scenes visuals.
Thunder reportedly trading Aaron Wiggins to Hawks for picks in deal that provides tax relief for OKC
The Oklahoma City have traded guard Aaron Wiggins to the Atlanta Hawks in exchange for two second-round picks, ESPN’s Shams Charania reports.
Blue Reflection Quartet second trailer, pre-orders now available
Publisher Koei Tecmo and developer Gust have released the second official trailer and opened digital pre-orders for heroic RPG collection Blue Reflection Quartet.
Scheffler praises Clark's resolve in gutsy US Open triumph
World number one Scottie Scheffler praised playing partner Wyndham Clark for defying New York hecklers as well as formidable Shinnecock to win his second US Open title on Sunday.Scheffler settled for a share of fourth after firing a one-over par 71 to finish on 280 while Clark edged fellow American Sam Burns by one stroke for the title.
Clark blocks out noise to stumble to US Open title
Wyndham Clark blocks out the noise of the fans to win a second US Open title at Shinnecock Hills.
Senators trade All-Star Brady Tkachuk to Panthers in blockbuster for package that features 3 first-round picks, unites him with his brother
The Senators will receive three-first round picks and a second in exchange for dealing the All-Star winger in his prime.
Senators reportedly trading All-Star Brady Tkachuk to Panthers in blockbuster for package that features 3 first-round, unites him with his brother
The Senators will receive three-first round picks and a second in exchange for dealing the All-Star winger in his prime.
Senators reportedly trading All-Star Brady Tkachuk to Panthers in blockbuster for package that features 3 first-round, unites hit with his brother
The Senators will receive three-first round picks and a second in exchange for dealing the All-Star winger in his prime.
UFL viewership stays level from Year 2 to Year 3
It seems as if the UFL, the upstart spring football league that just completed its third season, is finding somewhat of a baseline when it comes to viewership. The league averaged 674,000 viewers in its third season across ABC, ESPN, ESPN2, Fox, FS1, and NFL Network, up 1% versus average viewership in its second season…
Trump administration still trying to cancel school-based mental health programs
Officials say the second attempt to revoke funds could threaten key support for already-overwhelmed families.
Solar storms don't shock people directly — they induce electric currents in long metal, meaning power lines, pipelines and undersea internet cables become the very antennas that channel the damage into modern life
Solar storms do not electrocute people. They induce slow electric currents in long conductors — power lines, pipelines and undersea internet cables — which then channel the damage into substations and shore stations. The 1989 Quebec blackout took down a continent's grid in 90 seconds without a single direct strike from the Sun.
We’ve got the most GOATed World Cup display 🐐
In the record books.World Cup history was written last night.Against Ecuador, Curaçao claimed the first point (0-0) in its World Cup history, in its second match. One feat hiding another.Eloy Room, ...
Senate’s likely next No. 2 warns Trump if Democrats take the majority: ‘It’s going to be a fight’ on key values
Sen. Brian Schatz, who many believe will take over the second most powerful role in the Democratic caucus next year, has a warning for President Donald Trump: He could be dealing with a very different Washington if Democrats achieve the electoral gains they’re hoping for this fall.
England vs New Zealand: Matt Henry ends hosts' miserable fortnight
England's miserable fortnight ends with a crushing defeat in the second Test against New Zealand at The Oval - setting up a high-stakes decider at Trent Bridge.
Second person suspected of contracting Ebola put in isolation, Israel's health ministry says
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Google's Gemini Partially Figures Out A Lengthy Linux Boot Time On Modern ASUS Laptop
Google Antigravity with the Gemini 3.5 Flash model helped a Linux user sort out a situation where his laptop was taking around 36 seconds to boot the kernel, which shouldn't be the case for the high-end laptop with AMD Ryzen 9 processor and 32GB of RAM
New Zealand vs Egypt – Match preview and team news
New Zealand and Egypt meet in their second round match of the FIFA World Cup 2026 at the BC Place, Vancouver on Monday as both teams looks to register their first win of the competition.New Zealand vs...
The Women Running Businesses Under Taliban Rules
With secondary education and most jobs out of reach, thousands of Afghan women have turned to entrepreneurship as the only path to make money and maintain a social life.
Baltimore Orioles Make Adley Rutschman Decision Before Dodgers Game
Baltimore Orioles catcher Adley Rutschman was held out of the starting lineup for a second straight game.
Dua Lipa shares new photos of second wedding with husband Callum Turner
One wedding is not enough for everyone's favorite celebrity travelers, Dua Lipa and Callum Turner.
Germany and Ivory Coast name sides for Cup clash
The national teams of Germany and Ivory Coast have announced their lineups for this Saturday’s (20th) match in the second round of the World Cup group stage.The clash in Toronto, Canada, pits two te...
The real reason Trump wants to crack down on California's elections
California has had the second-highest voter turnout of any state so far this year, and mail voting is a big reason why, political columnist Joe Garofoli writes.
Royals double their pleasure, double our fun against Cardinals
It’s KC’s second winning streak of three games in the month of June!
USA tops Australia to clinch spot in final 32
SEATTLE — Christian Pulisic’s injury absence didn’t hurt the Americans one bit. The U.S. national soccer team found a way to advance to the knockout round without the injured forward on the field, beating Australia 2-0 Friday for its second straight victory at the largest World Cup in history. “C.P. is a fantastic player — […]
USA tops Australia to clinch spot in final 32
SEATTLE — Christian Pulisic’s injury absence didn’t hurt the Americans one bit. The U.S. national soccer team found a way to advance to the knockout round without the injured forward on the field, beating Australia 2-0 Friday for its second straight victory at the largest World Cup in history. “C.P. is a fantastic player — […]
Double endorsement drama: Trump backs second candidate in red state’s GOP gubernatorial runoff
Trump endorses both Wilson and Evette in South Carolina's GOP gubernatorial runoff, hedging his bets ahead of the high-profile Tuesday contest.
Microsoft confirms Windows 11 26H2 for fall 2026 release, reveals supported PCs and other details
Microsoft reveals Windows 11 26H2 will be a 200KB update, killing major feature releases for the second year.
Cowboys 2026 roster rundown: S Julius Wood
In his second go-around with Dallas, this safety is a longshot for the roster
The MacRumors Show: Hands-On With iOS 27, Brutal watchOS 27 Cuts, and More
On this week's episode of The MacRumors Show, we continue unpacking WWDC 2026 and take a closer look at iOS 27, macOS Golden Gate, and Apple's other new software updates coming this fall. Subscribe to The MacRumors Show YouTube channel for more videos iOS 27 supports the same iPhones as iOS 26, including the iPhone 11 and second-generation iPhone SE, giving the update the widest device compatibility of any iOS release to date.
WATCH: Would-be second-term President Biden left searching for family on stage after Obama Center opening
Biden sparked an awkward moment at Obama's presidential library dedication, drifting back toward the stage and shouting for his granddaughter.
UCLA adds former five-star pitching recruit Cambria Salmon
Former Texas Longhorn Cambria Salmon committed to UCLA on Wednesday, becoming the second pitcher to commit to the Bruins.
2026 U.S. Open Friday leaderboard, live updates: Wyndham Clark carries lead into second round at Shinnecock
Wyndham Clark is carrying a four-shot lead into Friday at Shinnecock Hills.
Trump’s Fatal Second-Term Mistake: Underestimating Nationalism
In his second term, Trump has underestimated the power of patriotic sentiment in countries besides the United States.
Waymo recalls 3,871 robotaxis over software issue
This is Waymo's second recall this year, following a May recall tied to one of its robotaxis entering a flooded roadway.
Canada's Ismaël Koné stretchered off after scary leg injury vs. Qatar at 2026 World
Qatar's Assim Madibo was given a red card for the tackle, marking the team's second red card of the match.
Google Is Using Nvidia’s Playbook to Build a Rival AI Chip Business
Wielding its war chest to win data-center customers for its silicon, the world’s second-biggest company is taking a page from No. 1.
2026 World Cup: Canada's Ismaël Koné stretchered off with potential leg injury
Qatar's Assim Madibo was given a red card for the tackle, marking the team's second red card of the match.
Two Maryville restaurants fail initial health inspections
KNOXVILLE, Tenn. (WATE) — The restaurants with the failing scores are in Maryville. It was a customer complaint that sent the inspector to a pizza place. The second restaurant is a cafe that serves…
Second Annual Cenevo Survey of Life Science Professionals Reveals Future of AI in Modern Labs
AI adoption is widespread across life sciences laboratories, but it is still mostly in the experimental stage, with only 5 percent using AI agents in production, according to Cenevo's second annual survey.
Second Annual Cenevo Survey of Life Science Professionals Reveals Future of AI in Modern Labs
/PRNewswire/ -- AI adoption is widespread across life sciences laboratories, but it is still mostly in the experimental stage, with only 5 percent using AI...
📸 2026 World Cup: our team of the opening round
Some big names.The first matchday of the 2026 World Cup group stage wrapped up this Thursday morning with Colombia’s 3-1 win over Uzbekistan. And this afternoon at 6 p.m., the second matchday gets ...
Four GOP US Senate candidates face off at Casper’s Politics in the Park
CASPER, Wyo. — Four Republican candidates for the U.S. Senate seat held by retiring Sen. Cynthia Lummis met in Casper on Wednesday for the second Politics
Four GOP US Senate candidates face off at Casper’s Politics in the Park
CASPER, Wyo. — Four Republican candidates for the U.S. Senate seat held by retiring Sen. Cynthia Lummis met in Casper on Wednesday for the second Politics
Katie Couric (@katiecouric)
3,068 likes, 268 comments - katiecouric on June 17, 2026: "Rahm Emanuel has been a major force in Democratic politics for decades—from congressman and White House chief of staff to mayor of Chicago and U.S. ambassador to Japan. As the 2026 midterms approach, he joined me on Next Question to discuss President Trump's second term, why Democrats "lost the plot," why he believes the U.S. should end taxpayer-funded military aid to Israel, and what it will take for the party to reconnect with voters and regain lost ground. 🎧 Watch the full interview on YouTube or listen wherever you get your podcasts.".
Gurman: Apple AirPods with built-in camera may arrive in late 2027
The AirPods are said to debut alongside the second-gen iPhone foldable. Back in May, a report claimed that Apple had entered the final stages of...
Alphonso Davies available for Canada’s second World Cup game against Qatar
Canada drew 1-1 with Bosnia in its World Cup opener last week, with Davies having to watch from the sidelines.
Exclusive: Salem business owner faces denaturalization by US DOJ
Officials are seeking to revoke the citizenship of a Keizer resident and Salem business owner, the first such case in Oregon in Trump's second term.
Mize returns but Tigers can’t solve Astros’ pitching
The Tigers dropped a second close game in a row and lost the series.
Apple Prepares Second-Generation iPhone Air for Spring 2027
Apple Inc. is preparing a second-generation iPhone Air for spring 2027, aiming to boost the appeal of the slimmed-down device, according to people with knowledge of the matter.
Penn State Health raises $51,742 during second annual ‘Let’s Get Ahead’ campaign
Penn State Health raised $51,742 through its second annual “Let’s Get Ahead” campaign during Head and Neck Cancer Awareness Month in April.
Jimmie Johnson joining TNT Sports as analyst
As it enters the second season of its media rights deal, TNT Sports is bolstering its NASCAR coverage by adding Jimmie Johnson.
Kent County health officials confirm Jamestown Canyon virus in West Michigan mosquitoes
A second mosquito-borne virus has been detected in West Michigan's Kent County, local health officials said.
US business inventories increase as expected in April
U.S. business inventories increased strongly in April, suggesting that inventory investment could contribute to economic growth in the second quarter.
USF names new dean of the Taneja College of Pharmacy
Janice Zgibor has been appointed as the new dean of the USF Health Taneja College of Pharmacy. A pharmacist and epidemiologist, Zgibor has served at USF for more than a decade and brings over 20 years of academic leadership experience to the role.She will become just the second permanent dean of the college.
Dodgers notes: Shohei Ohtani, Justin Wrobleski, Kyle Tucker
Tuesday was as low scoring of an affair as one could as for, as the Dodgers came away with their second 1-0 win since June 5. In what has been an unbelievable offensive stretch since May 12, Shohei Ohtani kept it going as he provided the only offense for either side, blasting a solo home […]
A first look at ‘Apocalypse Z 2,’ the upcoming post-apocalyptic action sequel coming to Prime Video this Halloween
The highly anticipated second installment in the ‘Apocalypse Z’ movie franchise releases worldwide this Halloween.
Patriots seeing growth from second-year wide receivers
Kyle Williams and Efton Chism each ended minicamp with touchdown receptions.
'House of the Dragon' Season 2 recap in 60 seconds
A full season recap in a bite-sized package.
South Africa’s DA Commits to Coalition Despite Clashes With ANC
The Democratic Alliance, South Africa’s second-biggest political party, remains “100%” committed to remaining in the ruling coalition, even though it isn’t functioning as intended, its new leader said.
Burke High School hosts second annual free sports physical clinic
For the second year in a row, many student athletes got an extensive sports physical exam for free at Burke High School.
Merchants of Doubt and the attacks on Extreme Event Attribution science
Last week, I attended a meeting at Columbia University on attribution science and climate law, hosted by the Sabin Center. It was a fantastic event, bringing together scientists and legal experts working at the intersection of extreme event attribution and climate law. Subscribe For those unfamiliar with it, extreme event attribution attempts to quantify the contribution of climate change to an extreme event. For example, several groups analyzed the impact of climate change on Hurricane Harvey’s enormous rainfall totals over Houston, Texas and they found that climate change increased rainfall by 15 to 38%. One thing that came up again and again was how terrified fossil-fuel interests are of extreme event attribution science. They are acutely aware that this research could land them in court. And losing those cases would leave them legally liable for billions of dollars in climate damages. Because the legal stakes are so high, the blowback has turned ugly. I spoke with several scientists at the meeting who are facing ongoing harassment over their work. This blowback is a coordinated campaign to make the entire field look suspect. The goal is to create the impression that attribution science is too uncertain, too political, or too conflicted to be useful in court or in public policy. The strategy is not based on actual science or evidence of misconduct, but on the generation of doubt. The new Merchants of Doubt We’ve seen this before. In fact, not that long ago: We only have to go back a year to the Department of Energy (DOE) Climate Working Group (CWG) report to see an example of using doubt as the tool to push back against well-established science. This strategy is laid out in an email from a member of the CWG, Dr. Roy Spencer, that was released during litigation over the Climate Working Group process. The key quote is: About all I can hope is that what we write will provide sufficient “reasonable scientific doubt” regarding the science claims in the 2009 TSD [technical support document], based upon almost 2 decades of new science, to call into question the original reasoning for the EPA Administrator’s decision that CO2 presents a threat to human health and welfare. This statement is strong evidence that at least some members of the committee were working to support a particular policy outcome: revoking the Endangerment Finding. The email also explains how they planned to do it: by attempting to generate “reasonable doubt”. This is going to be hard, Spencer implies. Despite falsely claiming that “2 decades of new science” weakens the case, Spencer explicitly acknowledges that the actual peer-reviewed science of climate change overwhelmingly rejects his position: But if the science argument is decided upon by a vote, or by the number of published citations, we lose the science argument. We can go back even further: This CWG email shares unmistakable DNA with the infamous 1969 tobacco memo that declared: “Doubt is our product, since it is the best means of competing with the ‘body of fact’ that exists in the mind of the general public. It is also the means of establishing a controversy.” The tobacco memo also acknowledges the limit of this strategy: Like the CWG, they knew the science was not on their side. Share The new new Merchants of Doubt The people attacking the IPCC chapter on extreme event attribution are the newest iteration of the Merchants of Doubt. Their goal, like all Merchants before them, is to introduce doubt into the process. Because the report is not even out yet, they cannot attack its conclusions. So they are attacking the authors instead. Here is a press release from the House Science, Space, and Technology Committee: In the letter, the Chairmen express concerns about potential conflicts of interest involving members of the Attribution Committee, stating that “publicly available information suggests a troubling pattern” in which committee members are affiliated with nonprofits that support climate accountability lawsuits, “raising the appearance of impropriety and member bias.” To be clear, this is just innuendo. There is no actual evidence of bias. And given the robust process that these reports go through, including multiple lines of peer review, it seems very unlikely that significant bias can survive into the report. When the report comes out, critics will have the opportunity to make legitimate criticisms of the report — if any exist. If none do, however, they’ll still make criticisms, but they’ll be bogus, simply designed to generate doubt. We’ll see. A note to the press: Fix your frame To any journalists reading this: The public debate over extreme event attribution science is not going away. The science is simply too dangerous to fossil-fuel interests for them to stop fighting it. You very well might be assigned to write an article about this area of research in the future. When you do, do not automatically adopt the framing that climate misinformers want you to use. They want you to frame the story around questions like: Are climate scientists trying to put their thumb on the scale to achieve a predetermined, politically motivated result? Are climate scientists improperly letting their politics invade the science of the IPCC? That frame is a trap. Instead, you need to view this through the historical lens of the Merchants of Doubt. How does the ecosystem of doubt operate? Who funds it? What methods do they use to misrepresent science and slime researchers? What scientific results are they trying to keep people from understanding are legitimate? Ultimately, you instead need to focus your article on the generation of doubt as a way to maintain the fossil fuel industry’s social and legal license to keep burning oil, gas, and coal. If you treat the misinformers’ frame as a legitimate, good-faith scientific critique, you are helping them produce doubt. Don’t do it. Don’t be a Merchant of Doubt. Thanks for reading The Climate Brink! Subscribe for free to receive new posts and support our work. Subscribe other stuff The Staying Curious Substack has an interesting post about the different flavors of climate sensitivity. This is crucial information if you want to understand how scientists think about how much warming the Earth will experience. I’d be grateful if you could hit the like button ❤️ below! It helps more people discover these ideas and lets me know what’s connecting with readers.
Photos: Derik Queen, Jeremiah Fears receive All-NBA Rookie Second Team trophies
New Orleans Pelicans rookies Derik Queen and Jeremiah Fears received their All-NBA Rookie Second Team trophies on June 16, 2026.
Live Results: California special primary election to replace Eric Swalwell
For several of these candidates, it’s the second time in two weeks that they have appeared on a ballot for this U.S. House seat.
Takeaways from JD Vance’s new book, ‘Communion’
Vance’s second book is focused on his faith and includes his cleanup from his infamous remarks about “childless cat ladies.”
Titans' defining number in 2026 relies on Cam Ward's improvement
The Tennessee Titans' one defining number, as named by NFL.com, is around the improvement of Cam Ward in his second year.
Video of Patriots rookie Gabe Jacas training surfaces amid controversy
With Gabe Jacas' contract status still in question, the rookie second-round pick is preparing away from the team for the 2026 season.
Detroit Tigers Lose Gleyber Torres to Apparent Injury Against Astros
Detroit Tigers second baseman Gleyber Torres exited Monday night's game against the Houston Astros
Examining the connection between sport and global relationships
Right now, the world is turning its attention to the United States as it hosts the 2026 FIFA World Cup. It is the first of the two largest global sporting events coming to American shores in the next couple of years, the second being the 2028 Olympic Games hosted in Los Angeles. It also provides an opportunity to explore sport’s role in shaping America's relationship with the rest of the world — and one lab at Arizona State University has a head start.
Alaska boots second Dan Sullivan from Senate race
Republicans alleged he entered the competitive race to syphon votes away from the incumbent, Sen. Dan Sullivan.
No music, no TV: Later last call in Worcester doesn't allow later entertainment
The License Commission plans to hold a second vote on extending hours for entertainment.
No music, no TV: Later last call in Worcester doesn't allow later entertainment
The License Commission plans to hold a second vote on extending hours for entertainment.
IKEA to open second upstate New York location in early 2027
Tentative plans call for IKEA to transform the 67,000-square-foot lower level of the former Sears and Sears Auto space.
This strange material can become strong or fall apart in seconds
Scientists have found that staple-shaped particles can tangle together to create a material that is both strong and flexible. Unlike conventional materials, these particles can be locked into a sturdy structure or rapidly unraveled using vibrations. The unusual behavior could open the door to recyclable buildings, reconfigurable structures, and even futuristic robotic technologies.
White Sox's Erick Fedde: Earns second win in relief Sunday
White Sox's Erick Fedde: Earns second win in relief Sunday
Microsoft's new Outlook takes 10 seconds to do what Outlook Classic does instantly on Windows
New Outlook takes 10 seconds to show an email after clicking a Windows 11 notification. Outlook Classic does it instantly. Here's why.
Pittsburgh Riveters top Erie Sports Center for 5th straight win
Sabrina Bryan scored in the 21st minute to help the Pittsburgh Riveters score a 1-0 victory over Erie Sports Center (1-5-0) at Saxon Stadium on Sunday evening. Bryan buried a diagonal feed from Riverview grad Lola Abraham, finding the bottom corner of the net with a second touch for her
Hurricanes Finally Break Through for First Stanley Cup Since 2006
Carolina extended its dominance and claimed its second title.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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