SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " wic " 1,184 found 🔀 AI-powered Shuffle
A Republican attack ad misidentifies its Democratic target. Twice.
A GOP ad used a photo of Republican Myron Lizer instead of Democrat Jonathan Nez. Nez is challenging Rep. Eli Crane (R-Arizona).
Gears of War: E-Day sells 230K copies
Gears of War: E-Day has sold 230K copies since its advance-access launch on October 1 and full release on October 6. Steam accounts for 168K of those, with Xbox (console and PC) selling 62K. But there’s more to this story, as Xbox makes up the bulk of revenue. E-Day is the best-reviewed Gears game in nearly two decades (and the best one ever made, in my opinion). The Coalition has made a banger here (it’s currently in my top 10 of the year). Despite E-Day’s undeniable quality, this is a soft result. And it’s down to the business model, really. E-Day has made $37M so far, thanks to the Premium upgrade On Xbox, Game Pass is cannibalising much of the premium revenue. Our estimates show that 1.7M folks accessed E-Day via their subscription rather than a copy. But Xbox is having it both ways – or having it halfway, at least – via its Premium Edition Game Pass upgrade. Game Pass subscribers could pay $30 (or their local equivalent) for up to five days of early access starting October 1. Our estimates show that of the 1.7M who accessed E-Day through Game Pass, 722K paid for the upgrade. Between the review embargo lifting on October 1 and the full release, E-Day managed to shift another 250K early-access upgrades – no doubt helped by the campaign’s rave reviews. So despite selling far fewer copies on Steam, Xbox accounts for almost three-quarters of the revenue (roughly $26M of the $37M, versus about $11M on Steam). So “230K copies” undersells the paying audience. Including the 722K upgrades, nearly 950K people actually paid something for E-Day. The $30 upgrade is a halfstep from cannibalisation, but will Xbox go all the way? While E-Day is a sublime game, these are soft numbers for a flagship when Xbox badly needs revenue wins. E-Day sold 62K copies on Xbox against 722K Premium upgrades, so for every one copy sold on Xbox, nearly 12 Game Pass upgrades were sold. The $70 premium SKU is – functionally – dead on Xbox. Normally you can’t see what a Game Pass player would have paid, because the game’s just there in the subscription. But the $30 early-access upgrade estimate shows that 722K people demonstrated they’ll spend real money on this game. In a world without day-one Game Pass, many of these folks would have bought E-Day at $70. They paid $30 for five days early access to something they don’t own. Xbox is, in effect, charging its most valuable customers the least, based on a hangover from a tried-and-exhausted strategy from a previous administration. Those 722K willing-to-pay players generated about $21.7M via the upgrade. If three quarters of this group – mostly US and European audiences – bought E-Day outright, that’s nearly $40M. Of course, Game Pass does bring in meaningful recurring revenue, and E-Day is adding value for hundreds of thousands of subscribers. However, Game Pass is no longer growing, so Xbox is at a crossroads. Xbox is reportedly looking to do a Netflix and bolt on an ad-supported tier to pad it further. But that will just set a new floor, and leadership keeps telling us the priority now is revenue growth, which is subscriber-speak for ARPU. Xbox has already pulled Call of Duty from day-one Game Pass after day-one inclusion hammered its sales, with new CoD titles now arriving on the service around a year late. We know that some Microsoft executives believe the service devalues games outright, and rumours (which Microsoft has dismissed so far, to be fair) suggest that day-one releases could be taken off Game Pass. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe When a game this well-reviewed does this softly on its home platform, the model – not the game – gets brought into question. What else E-Day’s early adopters have played (including this month so far) Looking at E-Day‘s players on Xbox, most have played the franchise before (86% have played Gears 5, 76% Gears 4), and every game on the crossover list is either a shooter or a title from an Xbox-owned studio (though Game Pass is inflating those numbers, of course, more on that later): As for what else Xbox’s E-Day players have played this month, the top three are Fortnite (16%), Roblox (7%), and Call of Duty (6%). Another 5% played Minecraft Dungeons II, which is also on Game Pass and launched a couple of days before Gears‘ advance-access date. Many Game Pass players are happy to check out most big new additions. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Over on Steam, the top crossover games are also mostly shooters (slightly more PC-coded ones), including Space Marine 2, which was itself heavily inspired by Gears: Looking at what E-Day‘s Steam players are into this month shows who they are – as subscriptions don’t skew the data. The top three are Wardogs (13%), Deadlock (12%), and CS2 (10%), so you’ve got the restless shooter crowd checking out the new hotness. A little further down are Helldivers 2 and Space Marine 2, your co-op PVE shooter players who’ll feel right at home in Horde mode. Game Pass is skewing the playtime distribution on Xbox Looking at the playtime distribution in our platform, E-Day players on Steam are – relatively speaking – playing for longer: 54% of E-Day players on Xbox have played for five hours or less (versus 32% on Steam) 19% of Xbox players played for over 15 hours (versus 33% on Steam) 14% of Xbox players played for over 20 hours (22% on Steam) The absolute number of people playing for over 15, 20, and 50 hours is, of course, bigger on Xbox, thanks to the sheer volume of folks who came in through Game Pass (upgraders included). None of that is cause for alarm. Game Pass is the reason Xbox playtime skews lower, as when a game is free to try, people try it and bounce without putting in even an hour (17% under an hour on Xbox versus 6% on Steam). Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe The subscription brings in tourists alongside the committed, dragging down the average even when the game is excellent (but also perhaps winning over the uninitiated). It’s standard across every subscription-included title, on PS Plus too. Forza Horizon 6, for instance, had 11% of its Xbox players bounce under an hour, versus just 2% on Steam. So, Xbox’s crossroads So there we have it. Gears of War: E-Day is an incredible game whose revenues have been stifled by subscription inclusion and exclusivity. It’s the best-reviewed entry in the series in fifteen-odd years, but it still turned into one of the year’s softer flagship launches, not because players didn’t want it, but because Xbox’s own storefront gave its most willing buyers a reason not to pay. Which leaves Xbox at a crossroads. Will it keep making Gears games when the financial returns are this thin and the margins this low? And if it does, does the next one arrive off Game Pass at day one – the way CoD now does, or even on PlayStation? I think it should. Alright, back to E-Day for me! The last word Reply to this email – or reach out here – if you have any feedback for the newsletter – or want to request a game for us to cover. [Alinea Analytics boasts the most accurate PC and console estimates in the business. Game makers use our platform to understand their audience, keep an eye on the competition, monitor sales trends, and spot new opportunities. We equip game studios and financial institutions with accurate data and the confidence to make smarter, data-driven decisions. Want to talk about all things games market data? We’d love to chat!]
Jeudevine Library Hosting Informational Discussion About Medical Aid In Dying
At the Jeudevine Memorial Library in Hardwick on Wednesday, Oct. 14, hear from Jen Carlo of Patient Choices Vermont about Medical Aid in Dying (MAID) and end-of-life choices in Vermont.
How candidates are spending in Wichita Falls for political races
Candidates have filed their campaign finance reports ahead of Nov. 3 local elections.
Monmouth Medical Center Honored by AMA for Commitment to Well-Being of Physicians
Monmouth Medical Center (MMC) has earned bronze level recognition from the American Medical Association (AMA) as a Joy in Medicine® organization. MMC joins fellow RWJBarnabas Health facility Community Medical Center, Toms River, in being named to the 2026-2027 list of Bronze-level hospitals and sister hospitals Cooperman Barnabas Medical Center, Livingston, and Robert Wood Johnson University Hospital, New Brunswick, who currently hold the Bronze level status.
Iowa Stops Hunger recap: A conversation on campus hunger
Mallary Allen empathizes with students who struggle with food insecurity because she used to be one herself. When she was in college, she became a parent and used programs like SNAP and WIC. “It was kind of scary for me,” she said. “It would have been helpful, maybe, to share what I was going through,…
Health and Human Services Secretary Mahaniah visits Sharing Kindness
Massachusetts Health and Human Services Secretary Kiame Mahaniah visited Sharing Kindness in Harwich on his statewide tour.
Meet the Journal Sentinel’s high school interns helping cover local prep sports
Meet Zoe Gryniewicz and Karol Lazarski, the Journal Sentinel’s 2026 high school interns helping cover local prep sports.
Bro Man's Sammiches claims top ranking in family-owned burger joints
After being recognized twice in 2025 by Mashed, Bro Man's Sammiches gets top spot in Yelp analysis by OnDeck business lender.
Dak Prescott tosses two picks in upset loss
Dak Prescott passed for over 300 yards for a second straight game but was also intercepted twice in a Week 5 loss to the Bucs.
Dontayvion Wicks added to injury report Thursday
Hamstring injury lands Eagles WR Dontayvion Wicks on injury report
Eagles Get Hit With Another WR Injury Preparing For Jaguars
There are a lot of names on the Philadelphia Eagles‘ injury report, and another weapon for the quarterback, Jalen Hurts, was added on Thursday. Dontayvion Wicks, the first-year Eagle, was downgraded to being a limited participant during Thursday’s practice action. “Dontayvion Wicks was added to the Eagles injury report with a hamstring injury. He was […] The post Eagles Get Hit With Another WR Injury Preparing For Jaguars appeared first on HEAVY.
Def Leppard, Goo Goo Dolls coming to Wichita next year
“Known for their high-energy performances, rock fans can expect a thrilling ride on this upcoming tour from some of rock ‘n’ roll’s most influential bands.”
Sandwiches to socialism: How a DSA chapter in Austin is building political power
The Democratic Socialists of America has experienced rapid growth and increased influence within American politics, driven by grassroots organizing and a platform focused on issues like housing, healthcare, and social justice.
Sandwiches to socialism: How a DSA chapter in Austin is building political power
The Democratic Socialists of America’s membership has more than doubled to 126,000.
Tri-county region receives over $2M in mental health service funding
SOUTHEASTERN N.C. — New Hanover, Brunswick and Pender counties will see more mental health funding coming their way after the federal government allotted $17 million to the state.
Mars’ ‘oddest cloud’ may be even more unusual than scientists thought
The cloud is 1,800 km long, nearly twice the length of the UK, and appears every spring and summer in Mars' southern hemisphere during the Martian dusty season.
Pull Up to 7-Eleven in Forza Horizon 6
A storefront inspired by 7-Eleven stores in Japan, a Konbini Prop Pack, an Egg Salad Sandwich Collectible, and an exclusive 7-Eleven Toyota Supra GR livery – all available in Forza Horizon 6 today.
ELRIG and The Protein Society announce keynote speakers for Protein Sciences in Drug Discovery 2026
ELRIG, a not-for-profit, volunteer-led organization dedicated to the global drug discovery community, and The Protein Society, an international, not-for-profit, scholarly society, with the mission to provide forums for the advancement of research into protein structure, function, design and applications, today announced the keynote speakers for Protein Sciences in Drug Discovery 2026.
Arsenal Beat Norwich City In International Break Friendly
Arsenal faced a Norwich City academy side in a friendly during the international break, in a bid to maintain fitness ahead of upcoming matches.
Sandwiches to socialism: How a DSA chapter in Austin is building political power
AUSTIN, Texas (AP) — When the socialists filed into the pews of a church sanctuary in Texas, there were far more than would have attended just two years ago.
Sandwiches to socialism: How a DSA chapter in Austin is building political power
The Democratic Socialists of America has seen its membership more than double to 126,000 over the past two years.
Locally authored ‘The Other Disney’ discovers gold, twice
SUSQUEHANNA COUNTY — “The Other Disney,” a novel by Hallstead physician-author Dr. Bernard Leo Remakus, tells the story of a father, who has just lost his job, and a resourceful
Cottagers best ever XI: Who is Fulham's greatest right winger?
Our ongoing international break series continues, as Fulham's next Premier League match against Ipswich approaches. Next up in the series of naming the Cottagers' best-ever Premier League players comes the right wing position.
Pick of the stats: Swansea City v Norwich City
BBC Sport highlights some of the key stats and facts for the Championship game between Swansea City and Norwich City.
Pick of the stats: West Bromwich Albion v Birmingham City
The key stats before West Bromwich Albion's clash with Birmingham City in the Championship on Saturday.
Man charged in burglaries at Watertown business
A man is accused of breaking into a Watertown business twice and stealing money and power tools.
In Good Health: The Evolution Of Prostate Cancer Treatment
Prostate cancer is the most commonly diagnosed cancer in American men — and the second leading cause of cancer-related deaths. One in eight men will be diagnosed in their lifetime. And Black men are more than twice as likely to die from it.Between the social stigma and misconceptions about diagnostic methods, it’s not something many men want to talk about. Some 99 percent of people diagnosed early with prostate cancer live at least 5 more years. And treatment options and guidelines are evolving rapidly.Our “In Good Health” series continues. We gather a group of doctors from three of the disciplines involved in the treatment of prostate cancer.Find more of our programs online. Listen to 1A sponsor-free by signing up for 1A+ at plus.npr.org/the1a.
Ben Affleck explains why he was banned from Instagram twice
The actor also weighed in on his iconic smoking meme.
Musicians host a magical, free concert
RANCHO CORDOVA — Something wicked this way comes. The Rancho Cordova River City Concert Band invites the community to an evening of musical mayhem, monstrous melodies, and magical mischief at
Version of popular game show coming to Wichita Orpheum
“The Price is Right Live” will be making a stop at the Orpheum Theatre in February.
Health organization in Wichita gives more than $1M for Kansas medical students
Wichita’s Riverside Health Foundation has given more than $1 million to Kansas Health Science University through an endowed scholarship fund established to benefit medical students.
Health organization in Wichita gives more than $1M to benefit Kansas medical students
Wichita’s Riverside Health Foundation has given more than $1 million to Kansas Health Science University through an endowed scholarship fund established to benefit medical students.
Health organization in Wichita gives more than $1M for Kansas medical students
Wichita’s Riverside Health Foundation has given more than $1 million to Kansas Health Science University through an endowed scholarship fund established to benefit medical students.
NLR Chamber CEO to exit for Florida post
The North Little Rock Chamber of Commerce announced Tuesday (Oct. 6) that President and CEO Derrell Hartwick will depart the organization effective October 9, 2026. Hartwick has served more than...
The GTA VI Rush Is Drying Up New PS5 Pro Stock, and GameStop Now Wants $1,399 for Used Units
Used PS5 Pro units now cost more than new ones at GameStop: $1399 for Digital, twice the console's 2024 launch price, with GTA VI weeks away.
This tool frees up Apple Intelligence storage on macOS, but think twice before using it
A new open-source tool is going viral over its promise to let users who aren’t interested in Apple Intelligence reclaim 12GB or more of storage on their Macs.
Classic Chronicle: Norwich, Vermont, showcases sustainability and hands-on science
A 2006 Classic Chronicle explores how Norwich, Vermont, embraces sustainable living and interactive science education
Springfield to host its first ever LEGO fan convention
SPRINGFIELD, Ill. (WICS/WRSP) - LEGO fans rejoice! For the first time, a LEGO fan convention is coming to Springfield.
Astronomers discover possible planet born from a dead star’s ashes
A second-generation planet might be orbiting a white dwarf, in an astronomy first, according to new research.
Collaborating with Canadian Scientists on Marine Carbon Dioxide Removal Research
I first met Dr. Helen Gurney-Smith in fall 2024, when Dr. Shannon Meseck and I drove just beyond the U.S.-Canada border to the St. Andrews Biological Station in New Brunswick. We went there to study larval sea scallop respiration when exposed to near-future temperature and pH. This past winter, Dr.
What Holding Eye Contact While Someone Speaks Really Reveals About Your Psychology, According to Science
You are mid-conversation with a friend, nodding along, and suddenly you wonder: am I looking at them too much? Or not enough? Most of us treat eye contact like an automatic reflex – something we either do or don’t, without thinking twice. But researchers say the way you hold someone’s gaze while they speak is...
Backlash to Trump hasn’t bolstered Florida Democrats’ voter registrations
More than twice as many Democrats switched their party to Republican since September 2024 than the other way around.
Chuba Hubbard scores twice in Week 4 win
Chuba Hubbard racked up 129 total yards and two touchdowns during the club's Week 4 victory over the Detroit Lions.
Curiosity Blog, Sols 5022-5028: Cashing in at Cache Creek
Written by Lucy Thompson, Senior Research Scientist, University of New Brunswick, Canada
Anticipation builds for Shocker basketball season
Wichita State hosted Shocker Madness at Koch Arena Saturday night ahead of the 2026-27 basketball season.
Dodge City hands Rose Hill its first loss of season
The Red Demons opened the scoring on an Austin Pinon penalty kick in the seventh minute.
Saka moves past Beckham after superb England display
Bukayo Saka delivered another outstanding England performance against Croatia, scoring twice in a 7-0 win and reaching a new international milestone.Photo by Carl Recine/Getty ImagesBukayo Saka scored...
Ontario Reign drop home opener to Coachella Valley Firebirds
The Ontario Reign fall 6-2 to the Coachella Valley Firebirds in Ontario's home opener Saturday night. Jani Nyman scored three goals and Jagger Firkus found the back of the net twice while Koehn Ziemmer and Jared Wright scored for the Reign. Ontario starts the 2026-27 AHL season at 1-1 with two points.
WATCH: Midwestern State hosts senior night and military appreciation night
WICHITA FALLS – Stang Park hosted a pair of events Saturday evening for No. 3 Midwestern State men’s soccer’s conference matchup with Oklahoma Christian. Airmen from Shephard Air Force Base were welcomed for a pizza dinner and as guests of honor for military appreciation night, while senior players and athletic trainers were honored on senior […]
Patriots fan-favorite fined twice for same Week 3 play
Patriots veteran wide receiver Mack Hollins was hit with two fines from the same play in last week's game against the Jaguars.
Mack Hollins fined twice on the same play, losing $34,441
The NFL fined Patriots receiver Mack Hollins $34,441 for his actions on the same play against the Jaguars.
‘A complicated map’: Henderson candidates push Boulder Highway updates
Henderson Councilwoman Carrie Cox and mayoral candidate Hollie Chadwick are sharing Boulder Highway construction and traffic updates on social media as the $184 million project continues.
4 new businesses coming to East Brunswick’s Legacy Place
A pet groomer has opened at East Brunswick’s Legacy Place, while a yoga studio, IV therapy business and Mediterranean bakery are coming soon.
Friday Football Fever: Week 5 scores and highlights
Week 5 of the Kansas high school football season is officially underway, and KSN has you covered with scores and highlights from the Wichita area and around the state.
11 Philadelphia business owners accused of defrauding WIC program of nearly $1M
Eleven Philadelphia business owners were charged in connection with a fraud scheme involving the WIC program, according to the attorney general.
Deshaun Watson solid in divisional win
Deshaun Watson threw for 268 yards and a touchdown in a Week 4 win over the Pittsburgh Steelers, though he did turn the ball over twice.
‘I Was Dealing With a Lot,’ ‘It Was Hard’ — Browns QB Deshaun Watson Opens Up About Bouncing Back From Mental Health Struggles
Deshaun Watson worked his way back from tearing his right Achilles twice to earn his starting quarterback job and lead the Browns to a surprising 2-1 start in 2026. Watson spoke with Taylor Rooks about how he overcame these obstacles mentally and bounced back from potentially career-altering injuries.
Team of the Week: Midwestern State women’s soccer
Midwestern State women's soccer hasn't lost a home match since October 21, 2023, most recently winning a pair of home contests to advance to 10-0-1 in their 2026 campaign.
Follow live Week 6 Wichita Falls high school football scores
Follow Week 6 high school football scores and updates from Wichita Falls and across Texoma, including district and non-district matchups.
Wichita candle business owner indicted Covid-era loan fraud
Grand jury accuses Wichita woman of submitting false information to obtain pandemic-era small business loans
Allowing remote access to WIC nutrition, health benefits could keep more children enrolled | Harvard T.H. Chan School of Public Health
Allowing families to recertify their WIC eligibility remotely helped keep more kids in the program, according to a new Harvard Chan School study.
'Worrying signs but not a crisis yet'
Paul: League form is not representative of actual form - the Champions League exit is still having an impact. Yes, European results have been bad but that is no surprise and nothing new. Patrick: Out of the Champions League and out of the League Cup, lost twice to Rangers in a week and seemingly have no consistent starting line-up.
In Hindsight, the Packers Should Have Never Traded Dontayvion Wicks
Jayden Reed’s devastating season-ending injury exposes a critical depth chart void, leaving the Green Bay Packers to rue an offseason trade that sent a potential rising star to Philadelphia.
2 massage businesses suspected of trafficking shut down in Kennewick sting
The same locations were shut down earlier this year under different names.
Trump administration misspells United States twice while promoting AI
The Trump administration misspelled the United States twice in images of the White House artificial intelligence memo it published following President Donald Trump‘s accord on Tuesday with the country’s biggest names in AI. On Tuesday evening and Wednesday morning, both Trump and the White House posted the “Joint Commitment on Frontier Responsibilities,” which came from […]
Trump administration misspells United States twice while promoting AI
The Trump administration misspelled the United States twice in images of the White House artificial intelligence memo it published following President Donald Trump‘s accord on Tuesday with the country’s biggest names in AI. On Tuesday evening and Wednesday morning, both Trump and the White House posted the “Joint Commitment on Frontier Responsibilities,” which came from […]
New York-based Blank Street Coffee coming to Chicago
New York-based Blank Street Coffee plans to open a 2,300-square-foot store in Wicker Park at 1588 N. Milwaukee Ave., the trendy chain's first Chicago outpost.
Trellis Health expands member-based primary care to Brunswick
Trellis Health, a MaineHealth subsidiary offering membership-based primary care, now has two offices in Maine
Cannabis users were twice as likely to commit violence, review finds
A review of more than 265,000 people found that cannabis use was associated with higher rates of both committing violence and becoming a victim of it. The researchers say the link is significant but does not prove cannabis itself is the cause.
Seaport Entertainment Group Completes Sale of 85 South Street Residential Building for $8.25 Million
NEW YORK, September 29, 2026--Seaport Entertainment Group Inc. (NYSE: SEG) ("Seaport Entertainment Group," "SEG," "we," "our," or the "Company") announced today it has successfully completed the sale of the eight-story residential building located at 85 South Street, New York, NY to an affiliate of MD Squared Property Group and Churchwick Partners for a sale price of $8.25 million.
I tried Ina Garten's breakfast sandwich with microwave eggs
Ina Garten's bacon, egg, and cheddar breakfast sandwich takes less than 15 minutes to make. Garten recommends cooking the eggs in the microwave.
Matthew Perry’s sister says he ‘spent $7 million’ on sobriety: ‘That’s how seriously he took his disease’
Matthew Perry’s younger sister says the ‘Friends’ star ‘spent $7 million trying to get sober’ before his death at 54, in trailer for ‘The One About Matthew Perry.’
Tuesday ‘Dawg Bites Knows Effort Counts Twice
Welcome to Tuesday, Bulldog Fans! Your Bulldogs are 4-0, and undefeated in conference play. 40+ points in each win, each by 4 touchdowns, ranked #2 in the land, and yet (we know, we know). These are the first world problems UGA fans face in this golden era of Georgia football. A wise man once told […]
Dontayvion Wicks generates little in Chicago
Dontayvion Wicks saw five targets in Week 3 but caught just two of them for 32 yards in a loss to the Chicago Bears.
Iowa State Association of Counties brings on new government relations director
Emily Schwickerath has joined the Iowa State Association of Counties as the director of government relations. She comes to the team after working with U.S. Rep. Randy Feenstra, who represents Iowa’s Fourth Congressional District. She has also worked in the Iowa Legislature and hopes to bring her governmental experience to ISAC to strengthen relationships between…
Kierra M with the latest in entertainment headlines
Family members of Chadwick Boseman are said to be at odds over a documentary.
Pumpkin Patch Is Open At Methodist Church
The Pumpkin Patch is back at the Bourne United Methodist Church, 37 Sandwich Road in Bourne village. The patch will be open every day through Saturday, October 31, from 10:30
Defensive concerns and possible transfers
Graeme: I wouldn't bet against the club bringing in a couple of additional players to freshen up the squad, but I would envisage that, before anyone else arrives, someone is likely to leave. Hayden asked: We seem to have some decent firepower this season, but can Ipswich get away with having pretty much a Championship defence? Graeme: I share concerns about Town in that part area of the pitch, but I think 'Championship defence' might be a tad harsh, Hayden.
Koch and the Chase Koch Foundation donate $1 million to The Pinnacle
The $1 million donation will go toward completing renovations to the state-of-the-art facility, offering local first responders comprehensive health and wellness services.
Will Ipswich stay in the Premier League?
Cameron asked: Will Ipswich stay in the Premier League this season? Also, what are your opinions on summer transfer business? Graeme: Obviously I can't say for certain that Town will stay up, but I am confident they will.
Buttler out of tri-series while England prepare central contracts
Wicketkeeper Jos Buttler will miss England's 50-over tri-series in Pakistan next month, with Jordan Cox set to be given another chance to impress in his place.
Jalen Brunson hosts 'SNL' Season 52 premiere as Weekend Update spoofs Anthropic's Dario Amodei
Knicks star Jalen Brunson hosted the "SNL" Season 52 premiere with help from his teammates, Katseye made its debut and Jane Wickline spoofed Anthropic CEO Dario Amodei.
This wireless eGPU claims to deliver RTX 5090-like performance over Wi-Fi
WiCi recently began inviting interested parties to sign up for updates about the WiCi One, which aims to become the first successful wireless external graphics card. The...
Politicians' superpower might allow them to avoid blame
Politicians' superpower is that we, members of the voting public, often do not understand how elected officials' actions can impact issues such as healthcare costs.
This External GPU Uses Wi-Fi To Transform Any Device Into A Gaming Rig
The WiCi One is available for preorders starting at $1,999.
Alajbegovic on right Juventus decision, Spalletti help and Scudetto ambition
Kerim Alajbegovic insists he ‘didn’t think twice’ about joining Juventus, despite an offer from Chelsea, thanks Luciano Spalletti for advice, and wants to ‘compete for the title.’The Bosnia ...
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Hip-hop legend Darryl ‘DMC’ McDaniels making appearance at Wichita’s Somewhere Fest
McDaniels, a founding member of Run-DMC, told KSN he will join Two Lot during the band’s set on Friday night.
Wici Wireless eGPU Promises RTX 5060 Ti and 5090 Performance Over Wi-Fi 7
There has been a lot of development in the eGPU scene lately, with Thunderbolt 5, OCuLink, and MCIO 8i providing serious gains in bandwidth and throughput for eGPU use cases. However, Wici has just launched the Wici One, a new wireless eGPU solution that relies on Wi-Fi 7 for data transfer...
‘Those interactions won’t always happen through a screen’: Qualcomm
Snapdragon Sound Elite Gen 2 puts Wi-Fi 6E and twice the AI power in earbuds. Qualcomm also showed 1-bit AI glasses platforms and a health alliance.
An army of paid creators is carpeting the web with political content
Functioning more like birdshot than a single bullet, these high-volume social media campaigns represent the new vanguard of modern political influence, saturating the internet with a topic.
First wireless eGPU with RTX 5060 Ti set to ship this year, Cyberpunk 2077 demo shown
WiCi One wants to make the eGPU cable optional. The RTX 5060 Ti box uses Wi-Fi 7 and a virtual GPU driver, with shipping planned this year.