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Louisville basketball adds NKU transfer LJ Wells
It’s the middle of September and Pat Kelsey and company are still active in the transfer portal. LJ Wells, a 6’8 power forward who played the last four seasons at Northern Kentucky, has committed to play for Louisville in 2026-27. Wells is the namesake plaintiff in the ongoing Wells vs. NCAA case in Jefferson County Circuit Court […]
First look at ‘Arctic Skies’ starring Morfydd Clark and Ariyon ...
EXCLUSIVE: Independent continues sales on the sci-fi thriller at TIFF.
‘CODA’ didn’t change Hollywood for the disabled. Siân Heder hopes ‘Being Heumann’ can
“CODA,” the first film featuring a largely deaf cast to triumph at the Oscars, marked a watershed moment for the film industry | WBBM Newsradio 780 AM & 105.9 FM
'R.L. Stine’s Pumpkinhead 2' Launches At TIFF Market, Details Revealed
'R.L. Stine’s Pumpkinhead 2' Launches At TIFF Market, Details Revealed With Cassandra Peterson AKA 'Elvira Mistress Of The Dark' Joining Cast.
Donald Trump mocked on TIFF opening night with 3 jabs at his attempt to rename Lake Ontario
Donald Trump received 3 rousing jabs from Toronto International Film Festival personnel and Toronto’s mayor on opening night, all of whom took aim at the president’s attempt to rename Lake Ontario.
Too much light at night may quietly reshape your heart
Nighttime light exposure was linked to thicker, stiffer heart chambers and early signs of reduced heart function in a study of more than 11,000 people. The findings suggest that keeping bedrooms darker could be an overlooked strategy for protecting the heart.
Editorial | Black infant mortality rate is a public health crisis
Editorial: Despite a mortality rate three times higher than white infants, Republicans like Tom Tiffany have opposed efforts to address race-based inequities in healthcare.
The 98 Biggest TV Show Flops, Bombs and Misses in the First Half of 2026
(Welcome to the Entertainment Strategy Guy, a newsletter on the entertainment industry and business strategy. I write a weekly Streaming Ratings Report and a bi-weekly strategy column, along with occasional deep dives into other topics, like today’s article. Please subscribe.) In July, I updated my look at how the “streaming bubble” popped since 2023, showing the decline in streaming TV shows over time. But after compiling and analyzing and writing about over one hundred TV show flops in the first half of 2026—I counted 99 “nominees” and there are even more honorable mentions—I couldn’t have told you that the number of shows is going down. When it comes to scripted, English-language TV shows, it feels like we have as many bombs as ever. I don’t keep a specific count, but some streamers probably had as many flops as they’ve ever had.1 That’s right, it’s time for part two of my analysis of the biggest flops, bombs and misses on streaming in the first half of 2026. Two weeks ago, I took a look at films. Today, TV shows. If you want to read the full methodology for how I assemble this list, you can find it at the bottom of this article. In short, this list is… ...scripted and unscripted TV shows,...from the nine major streamers,...in the US (using US-only ratings),...excluding true crime, kids and foreign-language shows,...that got no/poor ratings,...from Jan-2026 to the end of June-2026. Reminder: this article does not represent my personal opinion—many of these shows are great!—but I follow the data, and a miss is a miss and a bomb is a bomb. Also, price matters. If a TV show costs north of $100 million, it needs to get lots and lots of streaming viewership to justify that budget. As with past editions, I ordered this list by streamer, going from best (fewest flops) to worst (the most misses)—taking the size of the flops into consideration—and like the last edition, three or four streamers vied to take the win/loss of having the most flops. (But the actual winner is no surprise.) I try to avoid tooting my own horn too much, but seriously, in just under 5,000 words (including the methodology section) I provide a mostly comprehensive overview of the eight major streamers (Netflix, Disney+, Prime Video, Hulu, HBO Max, Peacock, Paramount+, and Apple TV) for the first half of the year, mentioning most of their hits and all their misses. It summarizes the entire first half of 2026! If you want to support this work, please subscribe. Subscribe Tubi Big Mood Boarders The Freak Brothers Twenty Twenty Six Honorable Mentions: Busted on Bodycam, Deestroying the Pitch, Destination World Cup 2026 I don’t think that Tubi spends all that much making or (mostly) licensing these original TV shows—Big Mood, Boarders and Twenty Twenty Six all come from the UK—but they’re not free and they didn’t chart anywhere. Winner: The Freak Brothers Have you even heard of this show? It’s an animated comedy...that’s on its third season! And Pete Davidson, Woody Harrelson, John Goodman and Tiffany Haddish all provide voice talent for it. Yes, animated shows don’t cost as much as live action shows, but cheap isn’t free! So a show with this level of talent needs to perform better. Disney+ Daredevil: Born Again Star Wars: Maul – Shadow Lord Honorable Mentions: Behind the Attraction, Donna Hay Coastal Celebrations, We Call It Imagineering Disney+ doesn’t make all that many original shows anymore. They had two flops, and one was animated. Their one not-a-miss show, Wonder Man, got just good enough viewership to not be considered a “miss”...but it’s since been cancelled. At this point, Disney has pivoted entirely away from making big budget TV shows for Disney+ to making...almost nothing for Disney+? Sure, Disney’s spending circa 2019-2022 was unsustainable, but now they’re pivoting too far in the other direction. At some point, Disney needs to stop shifting strategies so wildly. Really, Disney should have made fewer shows for Disney+ at launch and the shows they did make at that time needed to be made at more reasonable budgets. And they should adopt that strategy now. Winner: Daredevil: Born Again Daredevil, the Marvel Comics character, is on my personal Mount Rushmore of favorite superheroes, so it pains me to give him the win/loss today, but this show deserves it. I’ll repeat my hot take from last spring: “Based on his popularity, Daredevil should be in movies, and probably ones that cost a lot less than the MCU’s usual price tag. Disney/Bob Iger/Ike Perlmutter (who, based on reporting, made the decision) made a huge mistake selling TV shows to Netflix in the 2010s, thus limiting this character to the small screen. Daredevil could have anchored Marvel’s post-Infinity War plans, and if he did, the MCU would probably be in a better place than it is now.” HBO Max We’re just getting started with this issue, but the rest is for paid subscribers of the Entertainment Strategy Guy, so if you’d like to find out… What four streamers had the most misses... HBO’s strong start to 2026… The caveat to Peacock’s turnaround this year... Paramount+’s key man problem… What country isn’t delivering hits for Netflix or Hulu... The cavalcade of stars on a streamer where no one is watching their shows... Across nearly 5,000 words of analysis… And a lot more... ...please subscribe! We can only keep doing this great work with your support. If you’d like to read more about why you should subscribe, please read this article about the Streaming Ratings Report, why it matters, why you need it, and why we cover streaming ratings best.
Supporting small business across North Dakota
ND SBDC State Director Tiffany Ford joins ‘North Dakota Today’ to discuss the organization’s statewide impact
New Mexico tribe and pueblos wrap up case that Kalshi sports betting hurts their sovereignty
The New Mexico plaintiffs' filing cites a new appeals court ruling restoring state regulators' oversight of the prediction market.
Pediatrician-soprano to headline Bayfield concert finale
Soprano Dr. Tiffany Darling will headline the season finale of Bayfield Summer Concerts with an evening of arias and art songs Wednesday, Sept. 9, at 5:30 p.m. at Bayfield Presbyterian
UE men’s soccer set to host Louisville
EVANSVILLE, Ind. (WEHT) — The University of Evansville men’s soccer team is gearing up to host their second ranked opponent of the season in the 22nd ranked Louisville Cardinals. The Purple Aces are still looking for their first win of the season in what has been a competitive preseason so far. UE has played some stiff […]
Letters to the Editor: Constitutional amendment, state and local races
One reader discussed the constitutional amendment on the ballot this November. Another wrote in response to a student regarding local elections. And another discussed gubernatorial candidate Tom Tiffany, who serves as U.S. Rep. for the 7th Congressional District.
Tokyo University of Science develops 137 MJ/m3 tough glassy polymer
Researchers combined bulky DMAP counterions with an ionic comb polymer to achieve both high stiffness and toughness while suppressing nanoscale phase separation.
PlayStation And Xbox Hit Back At Gamer Lawsuits Demanding Tariff Refunds: 'There Is Nothing Unjust About Plaintiff Purchasing An Xbox At An Advertised Price And Getting Exactly What He Paid For'
The companies say there's no proof anyone was harmed
Jake Johnson hopes hustle, political conditions add up to upset over Republican Brad Finstad
Rochester math teacher Jake Johnson is waging a stiff challenge to Republican incumbent Rep. Brad Finstad. Johnson has gained national Democratic attention but still has an uphill climb to reach a seat in Congress.
Sony and Microsoft say they’re not obligated to pass U.S. tariff refunds to consumers, echoing Nintendo
Back in July, Sony executives told investors that the company expected to receive $508 million in refunds from the U.S. government, after tariffs that the PlayStation-maker paid were ruled mostly in 2025 were found to be illegal. “Most” of the refund would by recouped by Sony’s gaming division, its chief financial officer said. This week, Sony’s lawyers are arguing that the company is not legally obligated to pass those proceeds on to consumers who paid for recently price-hiked PlayStation consoles. That’s in the face of a lawsuit from gamers calling on them to do exactly that. “Paying fair market price for voluntarily purchased consumer goods is not a legally cognizable injury in fact,” the lawyers wrote in a legal motion filed on Monday, as they asked a judge in California’s Northern District to dismiss a potential class action lawsuit over the tariff refunds. Microsoft made a similar argument two weeks ahead of Sony’s lawyers, in a similar lawsuit brought by a gamer in federal court in Washington State. As Microsoft’s legal team put it on August 21, in their request for a dismissal of that lawsuit: “There is nothing unjust about Plaintiff purchasing an Xbox at an advertised price and getting exactly what he paid for—regardless of whatever theory he devised months later about Microsoft’s cost structure.” Both legal fights are set to go on for some time. How things got to this point U.S. tariffs impacting a wide range of imported goods, including game consoles, had kicked off in early 2025. In May 2025, Microsoft raised the price of its Xbox consoles, citing “market conditions and the rising cost of development.” They raised them again that September. In August of that year, Sony raised the price of PlayStation 5 consoles, citing “a challenging economic environment.” Sony later told investors that its tariff fees for the fall quarter were nearly $200 million. in February of this year, the U.S. Supreme Court ruled the 2025 tariffs illegal, prompting impacted companies to begin to request refunds. In turn, consumers began suing the likes of Sony and Microsoft to get what they said was their share. The gamers in the Microsoft and Sony lawsuits argue that the 2025 price hikes of PlayStation and Xbox consoles, which added $50 or more to their sticker price, were due to illegal tariffs and should now be returned to consumers. The Sony suit started in May, when a group of gamers sued in federal court in California, saying Sony Interactive Entertainment (PlayStation) would be unjustly enriching itself if it did not pass tariff refunds to its PS5 buyers. “Sony is poised to be paid twice for the same unlawful tariff burden: once by its customers (through elevated prices) and once by the U.S. government (through tariff refunds),” the gamers’ lawyers wrote at the time. They called for Sony to partially reimburse anyone who bought a PlayStation in the U.S. since August 1, 2025. The Microsoft suit, filed by gamer Trevor Hastings against the Xbox giant in July, made similar claims. The console makers push back In late July, Nintendo’s lawyers, facing a similar suit accusing them of double-dipping on tariffs and refunds, replied with arguments that previewed Microsoft’s and Sony’s: “Nintendo or one of its retailers set a price for each product, and consumers decided whether that price was worth paying,” they wrote. Sony has buttressed that Nintendo-style argument this week by saying that the gamers have failed to prove that tariffs were the reason for its August 2025 PS5 price hike. They call thatclaim “speculative and illogical.” Other factors, including “inflation, currency fluctuations, component costs, logistics, competitive dynamics, or demand,” could have played a role. (No, the Sony lawyers do not break down the costs and factors that officially triggered the price increases). Microsoft has also argued that there’s no proof in these lawsuits that tariffs drove all or some of the price increase, as it seeks to dismiss the tariff refund suit it’s facing: “Plaintiff provides no specific allegations that would establish any pricing differential attributable to tariffs or suggest any possibility that Microsoft applied then or could recreate now any dollar-for-dollar calculation of tariff-related pricing—any more than it could any other market factor that affects pricing.” To further skewer the gamer side’s argument in its case, Sony’s lawyers have pointed to what might be a surprising defense: yet another PlayStation 5 price hike from this past spring, after the tariffs were ruled illegal. “If the original price increase were attributable to tariffs, SIE [Sony Interactive Entertainment, aka PlayStation] would have had no reason to raise prices again after the Supreme Court invalidated the IEEPA tariffs.” … “If tariffs were the cause of the price increases, one would expect SIE to lower prices once the tariffs were eliminated—not raise them again. Instead, the timeline confirms that the pricing of PlayStation consoles includes a diverse and dynamic set of input costs.” Judges have not yet ruled on the arguments made by Sony, Microsoft or Nintendo. Last week, Panic, the company behind the small, yellow Playdate handheld said it would be passing its tariff refunds on to consumers. It is the only gaming hardware maker to have made such a pledge. Game File is a reader-supported publication. To receive new posts and support my reporting, please consider becoming a free or paid subscriber. Subscribe Item 2: A reporter’s second Second Life Wagner James Au, who from 2003-2006 was paid by San Francisco-based tech company Linden Lab to be a full-time journalist embedded in their virtual world Second Life, is returning to the company. This time, he’ll be an editorial advisor and business development specialist, he tells Game File. The new role will involve trying to share the stories of people inhabiting Second Life’s ongoing online world with reporters and by extension the public. Au plans to continue to also chronicle some of that through his long-running blog New World Notes. I’ve known Au since the mid-2000s and featured him in a 2007 article for the Columbia Journalism Review about reporters like him opening up virtual news outlets within Second Life. As I wrote at the time: On April 22, 2003, writing as Hamlet Linden for the New World Notes blog on Second Life’s Web site, Au introduced himself. “For the next few months, Linden Lab has invited me to set aside my journalist cap, and instead, don the digital beanie of their in-house virtual correspondent.” He wasn’t paid to keep it positive. He wrote about builders and eccentrics, but then in August of that year, he reported on a tax revolt against Linden Lab (a complaint about the fees it charges users who build stuff) led by a resident whose avatar was a big cat. Second Life has always been less of a video game and more of a virtual world where people can live, hang out, make art, sell virtual items and flirt. Back in 2007, Au described touring it as “sort of like underwater lucid dreaming.” For the past two decades, Au has maintained New World Notes as an independent publication. But he said he’s been drawn back to Second Life and Linden Lab as a place to directly work. The virtual world has around 650,000 monthly active users, he said, “which is actually about what it was during the hype wave.” Au says he’s still finding rich stories in Second Life, the kind that keep him interested 20 years into the beat: “Over the last few months for instance, I wrote about an SL creator in Venezuela whose apartment was destroyed by the earthquakes, so the global SL community rallied to get him back on his feet,” he told me. “Then there’s the woman from a Middle Eastern country who explored her lesbian sexuality in SL, then earned enough from her virtual jewelry to escape her abusive family situation and country.” Au wants to beckon more reporters to give Second Life another look. He argues that it is often ahead of internet trends, noting, for example, an early backlash in the community against AI-made art. Now the platform is drawing curiosity from more of the user-generated content community who’ve grown up with the likes of Roblox, according to Au. “Second Life was too early during its hype wave in 2005-2010, but it now feels right for a new wave of interest,” he told me.
Bayer's investigational PET tracer shows high accuracy for cardiac amyloidosis
The imaging agent could offer a new approach for diagnosing stiff heart syndrome, according to data presented during the European Society of Cardiology Congress.
Vanderbilt University Medical Center sued after allegedly exposing dozens of patients to bloodborne pathogens
Many of the details are unknown, but a primary plaintiff in the lawsuit said the exposure stemmed from a contaminated solution used during a 2024 colonoscopy. An attorney representing the patient said as many as 100 people could have been exposed to bloodborne pathogens.
SEC’s stiff penalties could force Lane Kiffin’s hand at LSU
We are about to find out what Lane Kiffin's LSU Tigers are going to do.
Tom Tiffany touts business success, but for years owed no taxes
Tom Tiffany, now the GOP candidate for governor, and his business went years without paying state income taxes, Department of Revenue records show.
Jakobe Thomas Returns To Vikings Practice
After missing time with back stiffness, the rookie safety returned to extensive practice work Monday.
Fed up with high prices, California weighs penalties against hospitals, other entities
California is weighing stiff penalties for hospitals and other healthcare entities that don’t stay under state spending limits.
Advocates say Tiffany’s vote for 2025 Medicaid cuts bodes ill for healthcare
Healthcare advocates say they don't approve of Tom Tiffany's vote for the 2025 tax cut bill that cut Medicaid and other benefit programs.
Celine Dion shares health update on stiff-person syndrome ahead of Paris shows
The singer opens up about her health, stiff-person syndrome and preparing to return to the stage in Paris.
What your feet say about your health
Tiffany Nesfield joins Good Day DC.
Scientists reveal why walking gets so much harder with age
As we age, the body appears to sacrifice walking efficiency in exchange for stability. Older adults stiffen the ankle more with each step, which may help prevent falls but also forces the muscles to work harder while producing less forward motion. This leads to shorter strides, slower walking, and faster fatigue. Exercises targeting balance, coordination, and lower-leg strength could help preserve mobility.
Investors sue Selena Gomez alleging fraud tied to her mental health startup
The plaintiffs say they invested nearly $1.2 million in the company, and are accusing Gomez of failing to build and market the startup.
The election deniers coming to a swing state near you
Tom Tiffany said 2020 was stolen. Now he’s the GOP pick for Wisconsin governor. And there are others like him.
Trial lawyers reclaim political clout in Texas GOP’s MAGA wing
Texas plaintiffs’ lawyers are bankrolling populist GOP insurgents. Tort reform groups like Texans for Lawsuit Reform are aghast.
Tiffany Haddish pleads guilty in DUI case, avoiding more jail time
Tiffany Haddish pleaded guilty in a Georgia DUI case, avoiding more jail time. The ‘Girls Trip’ actress was sentenced to 12 months probation.
North Dakota’s SBDC turns 40
Organization's work has created tens of thousands of jobs in North Dakota, says State Director Tiffany Ford
Cornish-Adebiyi v. Caesars Entertainment: The Third Circuit Deals Algorithmic-Pricing, Hub-and-Spoke Theory Another Hand
Antitrust scrutiny of information exchanges and algorithmic pricing tools has intensified recently—from public enforcers and private plaintiffs alike—as companies across industries increasingly...
Virginia CBD businesses file injunction to stop restrictions on hemp products
“If the state took your property for a new ball yard or a new highway, they’d have to write you a check for the fair market value. And if the state’s not going to play along with us in terms of letting us recoup our investment, then at a minimum they have to write a check for the property they’re taking,” said Chap Petersen, the former state senator representing the plaintiffs
Panama: Haemophilus influenzae meningitis case reported in Veraguas Health Region
The Veraguas Health Region, located in the central-western region of Panama, confirmed a case of meningitis caused by the Haemophilus influenzae bacteria in a 12-year-old student from La Primavera School, diagnosed on July 29. The patient remains hospitalized, is receiving appropriate treatment, and is in stable clinical condition. The regional health director of Veraguas, Xavier A. Torres Domínguez, reported that, once the diagnosis was confirmed, the Ministry of Health (Minsa), in coordination with the Social Security Fund (CSS), immediately activated the epidemiological investigation and health response protocols established for this type of event. Canada: Haemophilus influenzae type B outbreak in Calgary As part of the actions implemented, the Epidemiology teams carried out the identification and monitoring of the patient’s close contacts, applying the corresponding preventive measures to reduce the risk of transmission and safeguard the health of the educational community. Health authorities explained that meningitis caused by Haemophilus influenzae is a bacterial disease that requires timely medical attention. In that regard, they urged the population to immediately seek medical attention if they experience symptoms such as high fever, severe headache, stiff neck, vomiting, drowsiness, or altered mental status. They also reiterated that vaccination is the main preventive measure against this disease, and therefore called on parents and guardians to verify that their children’s immunization schedules are complete, in accordance with the Expanded Program on Immunization (EPI). Outbreak News Today is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Teen plaintiff suing Meta over mental health harms drops his claims against company days before trial
A Florida teen whose lawsuit claimed Meta’s platforms were to blame for his depression and anxiety dropped his case against the company just days before the trial in Los Angeles was set to start, the company said.
Teen Plaintiff Suing Meta Over Mental Health Harms Drops His Claims Against Company Days Before Trial
By Diana Novak Jones July 22 (Reuters) - A Florida teen whose lawsuit claimed Meta’s platforms were to blame for his depression and anxiety dropped his case against the company just days before the trial in Los Angeles was set to start, his attorneys said on Wednesday. The lawsuit, brought ...
Letter | Tom Tiffany is the pro-business candidate we need
Dear Editor: I recently read the letter to the editor titled, "Tom Tiffany's anti-worker, anti-business owner agenda," and as a Wisconsin small business owner, I felt compelled to respond.
Nintendo says it has no legal duty to pass its U.S. tariff refunds on to consumers
Nintendo is asking a court to dismiss a proposed class action suit that was filed this past spring by gamers who say the Mario maker is breaking the law if it doesn’t pass on its U.S. tariff refunds to consumers. Those consumers “received exactly what they bargained and paid for” when buying price-hiked Nintendo goods last year, the company said in a filing on Monday in the case of Hoffert et al v. Nintendo. “Plaintiffs are not entitled to a rebate simply because of intervening legal developments related to tariffs.” Nintendo increased the price of Switch 2 controllers and the original Switch last year, following the imposition of globe-spanning U.S. tariffs (tariffs described by Nintendo’s lawyers on Monday as “sweeping” and “constantly changing”). This past February, the U.S. Supreme Court ruled that the tariffs were illegal. A month later, Nintendo sued the U.S. government to get a refund. And in April, gamers filed the class action claim against Nintendo in Washington, saying it would be illegally double-dipping if it made money from tariff-hiked sales and then from a refund. The gamers sought relief for anyone in the U.S. who bought price-hiked Nintendo items between February 2025 and February 2026. “The common thread among Plaintiffs’ claims is that it is somehow ‘unfair; that Nintendo has not retroactively adjusted its prices for completed sales in response to the outcome of the tariff litigation,” the company’s lawyers wrote in today’s motion to dismiss. “But that is now how commercial transactions work.
Urban Renaissance Entertainment Announces Marcus Nel-Jamal Hamm's Expanded Role on Merry F-ing Christmas and New Creative Partnership with Tiffany Toney
Filmmakers Tiffany Toney and Marcus Nel-Jamal Hamm join forces on Merry F-ing Christmas.LOS ANGELES, July 16, 2026 (GLOBE NEWSWIRE) -- Urban Ren...
Tiffany Naiman Breaks Down the World Cup Halftime Entertainment Show - The UCLA Herb Alpert School of Music
The 2026 World Cup brought a renewed focus on entertainment. Tiffany Naiman, director of the Berry Gordy Music Industry Center, explores why music has become central to FIFA's global strategy and examines its partnership with the Recording Academy.
White House Faces Stiff Pushback on Subjecting Grants to Political Review
Academics, city leaders and congressional lawmakers number among the thousands to urge the Trump administration to reconsider a plan to assert more control over grants.
Vatican hits back at U.S. claim that Pope Leo speaks as a politician
President Donald Trump's ambassador had sought to portray the pontiff as the political leader of the Holy See. The Vatican swiftly said he is “proclaiming the Gospel.”
Microsoft loses lawsuit after blocking hacked Xbox account with digital games
One gamer took extreme measures to restore access to his compromised Xbox account. The Brazilian user filed a lawsuit against Microsoft after it refused to unfreeze his digital library. A court ruled in the plaintiff’s favor, and the decline of physical games could lead to more legal challenges.
OMB’s plan to increase political control of science faces stiff opposition on Capitol Hill
The Trump administration has a fight on its hands as it pushes forward with a plan to exert greater political control over government funding of science. To access this subscriber-only content please log in or subscribe.If your institution has a site license, log in with IP-login or register for a sponsored account.**Not all site licenses […]
She blamed flu shots for her twins’ deaths. Now she’s charged with murder.
Andrea Shaw, a plaintiff in a lawsuit against the American Academy of Pediatrics for recommending childhood vaccines, is accused of suffocating her daughter and son.
FIFA's red card reversal: Fair play or political interference?
FIFA's Disciplinary Committee suspended US striker Folarin Balogun's one-game red card ban in exchange for a probationary period of one year.The decision was announced after President Donald Trump called FIFA President Gianni Infantino and asked him to review the red card.The suspended red card means Balogun can play in Monday night's win-or-go-home match in Seattle versus Belgium.But the decision has faced harsh criticism from fans and The Union of European Football Associations, which said the red card suspension "crossed a red line."What does the red card debacle tell us about political interference in elite soccer?For sponsor-free episodes of Consider This, sign up for Consider This+ via Apple Podcasts or at plus.npr.org. Email us at considerthis@npr.org.This episode was produced by Jeffrey Pierre and Karen Zamora, with audio engineering by Ted Mebane and Tiffany Vera Castro. Our director is Kai McNamee.It was edited by William Troop and Tinbete Ermyas.Or interim executive producer is Courtney Dorning.
SCOTUS won't block Texas from enforcing age verification law for app downloads
Plaintiffs' lawyers argued that the law impermissibly seeks to limit access to content protected by the First Amendment.
Judge tosses Edgewater residents’ lawsuit over Broadway upzoning
The plaintiffs, a group of Edgewater residents and businesses, said they plan to appeal the ruling.
Despite stiff political headwinds, tribe in Colorado brings utility scale solar project online
President Trump has made substantial efforts to curb renewable energy development. The Ute Mountain Ute tribe in Colorado managed to bring a big solar project online anyway.
Popular Windsor egg farm exits egg business amid hard times for small farms
Tiffany Holbrook, co-owner at Wise Acre Farm, announced this week that the farm shut down its local egg operations and will move to a new location in Sonoma County to focus on meat production. She said the realities and costs of running the…
Texas Supreme Court Requests Briefing on Kemah Entertainment District Street Closure Case
Plaintiffs say the city violated state law in closing the street.
Maryland-Bred Big Cuddle Joins Haskell Lineup
Pocket 3's Racing’s Big Cuddle will face his stiffest test yet in the $1 million, Grade 1 Haskell Stakes at Monmouth Park on July 18, the Daily Racing Form reports. The Haskell field is expected to draw Preakness winner Napoleon Solo and runner-up Iron Honor, as well as G3 Tampa Bay Derby ...
Medicaid work requirements challenged by coalition of 26 states
Led by Massachusetts and California, the plaintiffs say CMS ignored the will of Congress by strictly defining a “medically frail” exemption that would allow a person access to safety net medical coverage.
‘Noxious odors’ lawsuit involving organic residuals lagoon dropped by Fort Smith business owners
VAN BUREN -- A civil lawsuit focused on a widespread foul odor linked to an Arkansas River bottom organic residuals storage lagoon has been dismissed at the request of the plaintiffs.
Making sense of what Lars Tiffany’s lawsuit says about UVA sports
Analyzing a few points made by Tiffany’s camp and what they indicate about the UVA athletic department’s approach.
Bayer wins in US court, but at what cost to public health?
A landmark US Supreme Court ruling protects Bayer from thousands of lawsuits linked to its Roundup weedkiller. Plaintiffs alleged the German agrochemical giant failed to warn users about potential cancer risks.
ORED sues city, county, and more for entertainment district injunction
Oklahomans for Responsible Economic Development and several individual plaintiffs filed a lawsuit Tuesday seeking declaratory, injunctive and mandamus relief against the city of Norman, the Norman Tax Increment Finance Authority,
Hospital must pay $23M jury verdict after radiologist misses spinal cord injury on CT
Plaintiff attorneys believe this is the largest non-death-related malpractice payout in the history of Maine, with Brewer-based Northern Light Health system on the hook for the damages.
Edgecombe County woman wanted on embezzlement charges involving Bethel business
Tiffany Green is accused of stealing $18,500 in cash.
Dem who sued to remove Trump's name from Kennedy Center now says venue becoming 'lifeless husk' in fresh fight
The plaintiff in the case, Democratic Rep. Joyce Beatty, said that by refusing to take steps to resume shows, the Kennedy Center is in violation of a previous court order.
California's billionaire tax qualifies for the November election but faces stiff political pressure
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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