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How a fraud ring weaponized New Jersey business filings
Eight pleaded guilty in an $11-million scheme that changed or invented business registry records, then opened accounts as the payee at about 30 institutions.
Political dirty tricks upend midterm races across the country
Each one of these schemes could have an outsized impact on control of Congress.
‘The Cardinal Countdown: 22 Days Until Kickoff’
LEKHY THOMPKINS #22 Height: 6’2” Weight: 235lb Position: RB Class: Freshman Hometown: Alamo, TN Summary: Some guys walk into the program looking for help, they build a good work ethic, build a strong foundation of understanding in the schemes, develop a relationship with the coaches, and work their way into a nice role on the […]
Small Businesses Despise Trump’s Tariffs
Mere hours after the Trump administration's latest tariff scheme launched on July 24, the government was sued again by the same small businesses that had already defeated prior White House tariff shenanigans, most notably at the Supreme Court. As Bloomberg Law reported, these companies are part of an “increasingly vocal cohort of business owners who emerged as the face of mom-and-pop tariff resistance.” What about Walmart Inc., Ford Motor Co. and the other titans of corporate America paying many
M&M’s Makes NASCAR Return With Epic Kyle Busch Bristol Tribute
Joe Gibbs Racing made a surprise announcement on Thursday that will stun the sports world.M&M’s will make a shocking return to NASCAR racing after leaving the sport at the end of the 2022 season. The late Kyle Busch’s famed M&M’s bright yellow paint scheme will be back on track with Ty Gibbs, who just won […] The post M&M’s Makes NASCAR Return With Epic Kyle Busch Bristol Tribute appeared first on HEAVY.
State Dept axes Biden-era DEI scheme pushing woke politics across the globe and more top headlines
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The Steelers defense is still missing 3 of its key pieces, but their new coaching staff isn't concerned
Patrick Graham has been entrusted with running the Steelers defense, making sure it has some of the vestiges of the old 3-4 schemes Mike McCarthy embraces...
US accused of meddling in British politics with $500,000 grant scheme promoting ‘shared values’
Documents published on US embassy’s website prompt claims of attempt to export Maga propaganda to UK
19 charged in $4M Pennsylvania home health care fraud schemes
Nineteen people were charged in Medicaid fraud cases involving more than $4 million in alleged false home care billings, authorities said.
‘Your days are numbered’: DOJ, federal agencies target health care fraud, Medicaid schemers in Pennsylvania
Federal agencies and state partners announced criminal charges against 19 people who allegedly defrauded Medicaid with home health schemes.
19 defendants charged in Pennsylvania home healthcare fraud schemes
Nineteen defendants are facing criminal charges following an investigation into healthcare fraud in Pennsylvania, officials said.
Debt Digest | Federal Debt is a Health Care Problem
Welcome David Ditch to the Debt Dispatch! We are pleased to announce a new regular contributor: David Ditch will be joining the Cato Institute as a Policy Analyst for Budget and Entitlement Policy later this week. David has more than a decade of experience in fiscal policy issues, with a particular focus on federal spending. He previously worked at the Senate Budget Committee, the Heritage Foundation, and the Economic Policy Innovation Center. David’s areas of expertise include appropriations, transportation, agriculture, federalism, grantmaking, and policy options for deficit reduction. Originally from the Rochester, N.Y. area, David has a BA in Economics and Political Science from the University of Rochester and a MA in Political Management from George Washington University. David currently lives in Arlington, VA. You may have enjoyed his earlier guest posts: CBO: New Highway Bill Has More Spending, Taxes, and Deficits Trump Administration’s Proposed Changes to Federal Grants Highlight Problems of Big Government Here are this week’s reading links and fiscal facts: The federal debt is largely a health care problem. In a new report, the Congressional Budget Office and Joint Committee on Taxation find that “In 2026, federal subsidies for health insurance, net of related payments to the government, are projected to equal $2.4 trillion, or 7.4 percent of gross domestic product (GDP). In CBO and JCT’s projections, those subsidies grow by 65 percent, reaching $3.9 trillion, or 8.4 percent of GDP, in 2036. Subsidies for Medicare contribute most to that overall growth, increasing by $900 billion. Over the entire 2026–2036 period, federal subsidies for health insurance total $33.6 trillion.” Cato’s Michael Cannon emphasizes, “The long-term federal debt problem is a health care problem. […] Only two categories of federal outlays will grow faster than gross domestic product (GDP): health care subsidies and interest payments on the debt. The former is, therefore, the primary driver of the latter.” The bond market fears deficits, not the loss of tariff revenue. Responding to a New York Times essay claiming tariff revenue has grown too important for a future administration to unwind, Cato’s Kyle Handley argues: “Bond investors are not attached to customs duties as a line item revenue source. They care about the government’s overall fiscal position.” He continues, “tariff revenue is a side hustle. And the Trump administration has already promised to dole out the funds through schemes like tariff dividend rebates, farm subsidies, and pay-fors on tax cuts or other spending.” Furthermore, “tariff revenue is simply not large enough to transform the government’s fiscal trajectory.” Take net interest for example: it “reached $970 billion in fiscal year 2025, absorbing 18.5 percent of federal receipts. Customs duties accounted for only 3.7 percent of receipts—and that was before refunds (see Figure 2).” Handley concludes, “The real bond-market concern is a large and growing interest bill, persistent budget deficits, and a political system unwilling to bring spending and revenue into alignment.” Medicare’s spending growth is driven by more volume and utilization. A Congressional Research Service report finds that Medicare spending “grew at an average annual rate of 7.3%” from 1985 through 2025, and the trustees project health care expenditures will keep rising “faster than gross domestic product (GDP) in most future years.” Citing CBO, the report attributes Medicare’s projected 2026–2036 spending growth to “23% from higher enrollment, 31% from inflation, and 47% from the growth of inflation-adjusted spending per beneficiary. In other words**, the largest single driver of Medicare spending growth during the next decade is expected to be higher volume and intensity of health care services.”** Boccia and Thakur explain: “as the economy grows, Medicare spending tends to grow at least as fast—and often faster—because the program automatically pays the bill for more and more healthcare consumption by seniors, even as prices rise.” The Fed has little control over market interest rates. Cato’s Jai Kedia documents that the Fed has held its rate target steady since December, yet “nearly every rate Americans actually borrow at has climbed over the same stretch.” Kedia continues, “The Fed did nothing, and the cost of credit went up anyway. […] Markets spent these months repricing macroeconomic events such as sticky core inflation, a volatile energy market driven by the conflict in the Middle East, and global trade disrupted by tariffs, among others. None of that required a policy change to show up in borrowing costs because markets, not the FOMC, set prices.” He concludes, “Accurately priced borrowing rates will come from credible disinflation and disciplined budgets and from a Fed content to follow the economy rather than pretend it leads it.” Nearly half of US farm income comes from taxpayers. Former Reagan OMB director David Stockman notes that “in the most recently completed full year (FY 2025) farmer incomes in the US totaled $97.8 billion, but fully 42.7% or $41.8 billion of that amount came from taxpayers, not the marketplace. Nor is this some kind of one-year aberration. If we look at the most recent decade as a whole, total farm income posted at nearly $708 billion, but, as indicated, fully $322 billion or 45% of this came compliments of US taxpayers.” Cato’s Chris Edwards explains why so little of that income is market-earned: “Farmers are businesspeople, but the government shields them from just about every type of weather and market risk. Furthermore, just about every part of the agricultural industry is subsidized, including insurance, loans, marketing, research, export sales, and land improvements.” The Debt Dispatch is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Southlake man gets 9 years in prison for $8M business loan scheme
A former Southlake attorney was sentenced to nine years in federal prison for defrauding small-business owners seeking multimillion-dollar loans.
2 Baldwin men charged in sex trafficking scheme involving coded business cards
A federal grand jury has indicted two Baldwin County men on sex trafficking charges, alleging that they ferried women from Georgia to the Gulf Coast to have sex for money.
DOJ issues declination of charges against eye care group, opting to indict CEO for role in $3.4M fraud scheme
The shift in prosecutorial focus is part of a new enforcement policy to address healthcare fraud. The U.S. Department of Justice alleges the CEO of CampusEye paid kickbacks to doctors for referrals, going on to bill Medicare for unnecessary tests.
VA Employee, CEO Plead Guilty to $14 Million Health Care Kickback Scheme
The Florida-based individuals worked together to fraud patients of the VA Community Care Program (VACCP), per the Justice Department.
Patrick Queen opens up on Steelers new defensive scheme
Patrick Queen offers insights on how Patrick Graham is rebuilding the Pittsburgh Steelers defensive scheme around clarity and details.
Darryn Peterson’s Summer League Approach Sent Strong Message to NBA
Facing relentless traps and physical defensive schemes, Utah’s top pick is embracing the grit. Peterson aims to flip the script by using his foul limit to establish a dominant defensive identity.
Brazil uses forensic science to trace gold’s origin and tackle illegal mining in the Amazon
Investigators say criminals use schemes to insert illegally mined gold into legal market.
'The restaurant remains open': Gee, Ursula stunned by Capitol Hill business owner's alleged $1.5M tax scheme
A Capitol Hill restaurant faces scrutiny as its owner is charged with stealing $1.5M in payroll taxes from employees.
Netflix actress, model plead guilty to $3.4M Medicaid fraud scheme
The unusual defendants were swept up as part of a larger investigation into healthcare fraud in the Minnesota housing services program. An alleged third co-conspirator has pleaded not guilty and will take her chances at a jury trial.
Sussex Partnership NHS trust joins scheme to tackle racism
The new pilot aims to strengthen support for "racially marginalised" carers in mental health services.
Pols & Politics: Brensley launches write-in bid for Sec. of State following failed Lt. Gov. campaign
Former GOP Lt. Gov. candidate Anne Brensley is launching a write-in campaign for Sec. of State after failing to qualify for the ballot due to falling victim to a signature collection fraud scheme.
Can Buccaneers Top Saints as NFC South Division Kings?
After injuries derailed their dominance, Tampa Bay looks to Baker Mayfield and a new offensive scheme to reclaim divisional glory from surging rivals in a wide-open race.
4 Georgians named in record $6.5B health care fraud takedown
Four Georgians were named in a nationwide health care fraud crackdown involving alleged schemes totaling $6.5 billion.
Local sports facility developer’s home, business raided by FBI
Federal prosecutors allege Andy Card engaged in a wire-fraud scheme involving the development of the Mishawaka Fieldhouse and used proceeds from it to help purchase a home in Florida.
State warns of new "Mr. Finance" investment solicitations from man accused of running Ponzi scheme
The Illinois Secretary of State is warning a businessman known as Mr. Finance, already accused of running a Ponzi scheme, may be soliciting investments in an allegedly sketchy new business.
FBI: Motown Sports Village promoter charged in alleged multi-million dollar wire fraud scheme in Romulus
A West Bloomfield man has been federally charged with wire fraud in connection with a heavily marketed proposal to develop a sprawling youth sports and entertainment complex in Romulus.
FBI: Motown Sports Village promoter charged in alleged multi-million dollar wire fraud scheme in Romulus
A West Bloomfield man has been federally charged with wire fraud in connection with a heavily marketed proposal to develop a sprawling youth sports and entertainment complex in Romulus.
A businessman promised investors to build a $3B sports complex near DTW. Feds say it was a scam
A West Bloomfield man is facing a federal charge for his alleged role in a scheme to get millions of dollars in investment funds for a proposed sports complex in Romulus.
Pete Prisco: 3 Bills Land On CBS Sports Top 100 Players For The 2026 Season
CBS Sports Senior NFL Columnist Pete Prisco joined One Bills Live to recap and dissect his Top 100 players for the 2026 season. He shared his overall thoughts on the Bills roster this season, the new leadership under Joe Brady and the defensive scheme wit
PPG introduces PPG AEROVIEW virtual aircraft painter for business, general aviation
Innovative digital tool enhances aircraft paint color selection, design experience PPG (NYSE: PPG) today announced the launch of the PPG AEROVIEW™ virtual aircraft painter, a digital tool designed to help business and general aviation customers explore and customize aircraft paint colors with precision and ease. This web-based tool provides an interactive platform where users can select from a variety of aircraft models and digitally apply colors from PPG’s comprehensive aerospace color library to visualize custom paint schemes in real time. The PPG AEROVIEW™ virtual aircraft painter is a digital tool designed to help business and general aviation customers explore and customize aircraft paint colors with precision and ease. The PPG Aeroview virtual aircraft painter is designed to increase the visibility and accessibility of PPG’s aerospace coatings, particularly for business and general aviation markets. The tool provides a digital alternative to traditional physical color brochures
‘Politicians have always been schemers’: upheld conviction fails to dent Le Pen’s popularity
Presidential bid by leader of far-right National Rally has no shortage of supporters in scenic Montargis
Super Bowl champion LB says 49ers' scheme gave him nightmares
Retired Bucs LB Lavonte David says the Shanahan-era 49ers gave him more trouble than any offense he faced late in his career.
All potential scheme changes coming to Rams in 2026
The Rams and Sean McVay are signaling significant scheme changes in 2026
Hungary moves to overhaul university models banned from Horizon Europe
Hungary’s new government is aiming to overhaul the governance model of the institutions and universities that lost access to Horizon Europe and Erasmus+ funds “in a short timeframe,” according to Péter Horváth, the new state secretary for science policy and innovation. “As of today, the two non-university foundation-controlled institutions under my remit have been transformed,” he told Science|Business. “We hope the universities will follow and that this will be enough to satisfy the EU’s demands.”Under the previous government, led by Viktor Orbán and his Fidesz party, many academic and scientific institutions were restructured and made into special public trust foundations, with members strongly linked to the government given lifelong mandates and significant decision-making powers with little oversight. The European Commission deemed that this undermined academic freedom and transparency in the country, leading to a ban on 34 institutions in 2022, including 21 universities, which saw academics in Hungary lose access to Horizon Europe grants. The new Hungarian government, elected in May and led by Péter Magyar and his Tisza Party, has promised to dismantle this governance model and restore the institutions to EU programmes. As a result, the European Commission has promised to return access to the Erasmus+ education mobility programme, but so far no concrete agreement has been made on the Horizon Europe programme for research and innovation. Hungary has already made legislative changes in June to allow the institutions to be reformed and set a timeline for the implementation.The non-university foundations, which are mainly cultural centres such as the Foundation for Hungarian Culture or the Makovecz Campus Foundation, will all be dissolved by August 31 this year, a date tied to EU-set milestones that Hungary must meet to unlock frozen funds, with control transferred to relevant ministries. Meanwhile, the universities will have until 31 August 2027. For each university foundation, the government will set the dissolution date and the body to take over operations. There is no final decision on a permanent new model for the universities, according to Hungarian MEP Eszter Lakos, who is shadow rapporteur for the Horizon Europe specific programme, a separate piece of legislation detailing implementation rules for the EU’s next research programme, due to start in 2028. “The aim of the transition year is to settle this with [the universities], not to impose a model, and not to put them under state control,” she told Science|Business. “The goal is to give academic independence back to universities.”There are three models that are most likely to be implemented. One would be a return to a traditional, state-run model. Another could be a newer, more self-standing public institution. A third option would be a reformed version of the foundation models that meet EU standards. According to Lakos, the dismantling of the system put in place by the Orbán government is well underway and if all goes according to plan, Hungary could regain access to EU research money by the start of the next academic year in 2027. “I believe that the Hungarian government is doing the necessary changes so the universities could return as beneficiaries to Horizon from the next school year,” she said. In the meantime, “the universities, institutes and cultural assets carry on under proper public stewardship rather than a handful of unaccountable trustees,” said Lakos. The laws passed in June impose new safeguards: board terms are capped at four years and renewable only once, appointments are made through open competitions and sitting politicians cannot join joining these boards.It remains unclear whether a domestic science funding programme set up as a back-up scheme by the former government following the EU funding ban, called HU-rizon, could be continued. “This programme should never have had to have been established in the first place, but it has proven to be quite popular,” he said. “I am considering continuing this programme with a refined focus on helping international collaborations.”Re-organising the research network One of the first priorities for Horváth and his cabinet is to resolve questions over the future of the Hungarian Research Network, Hun-Ren. The network of academic institutes was taken away from the Hungarian Academy of Sciences in 2019 and turned into a quasi-private organisation, with similarities in its governance to the public trust foundations.Horváth and his team have consulted over 5,000 representatives from the network and the conclusion is broad unhappiness with the directors of all the institutes involved. “We have presented the results to the president and the chief executive of the network and this is currently being discussed,” Horváth said. The plan is to re-integrate the network back into the Academy of Sciences but in an improved way, “learning from mistakes of the past,” he added. The government also wants to reintegrate four humanities and social science research centres into the network that the previous government had transferred to Eötvös Loránd University. The transfer brought sharp criticism from the academic community, with a group of Hungarian research heads, including European Research Council grant recipients, sending an open letter to Orbán warning that the transfer would “cause historically significant harm to the entirety of Hungarian scientific life.” The transfer was “one of the biggest shames in Hungarian research in the past 20 years,” Horváth said. “We want to immediately re-integrate them back into the research network and to regain the trust of these institutions, because the way they were treated was really unfair.”Another pressing issue is the Élvonal Excellence Research and Talent Development Foundation, led by Nobel laureate Ferenc Krausz. The foundation signed a financing agreement with the former government earlier this year for a budget of over €730 million over the next five years. The goal is to create a world-class centre to attract top talent from abroad and to develop local researchers. But there was little transparency about this foundation, and news of its huge budget, which is nearly as much as Hungary’s entire research budget, caused a stir in the media following the recent elections. Another issue is that, as with the foundation boards of the institutes banned from Horizon Europe, there was little-to-no oversight of decisions led by Krausz. “It was an excellent idea but an unacceptable execution,” Horváth said of the foundation. “The fact that this is out of the Hungarian funding scheme, mostly concentrating on one person who decides on the budget is unacceptable for us.”The government plans to merge the centre with the National Research, Development and Innovation Office, the country’s R&D funding agency, with a reduced budget. Horváth is hopeful that Krausz will still be involved. The new government’s R&D goalsA phrase that crops up regularly during the discussion with Horváth is “democratic process.” The new state secretary is determined to involve Hungary’s research community in shaping future policies. This marks a departure from the previous government’s approach, and several people in Hungary’s research community have commented on the openness of the new government. In terms of concrete goals, Horváth and his team already have plans. He wants to create a new science fund in Hungary, based on the best practices of other European countries. The fund would not be tied to annual government budgets and would provide long-term, stable financing. “If we were to succeed in creating this fund, then I think it would be one of the biggest achievements for me in this period of government,” Horváth said. On the innovation side, he is looking into how best to bring in the private sector. “We want to make sure that we are working with the private sector to support innovation,” Horváth said. One of his big aims is to introduce entrepreneurship teaching into high schools. Hungary already has a reputable national academy offering research and innovation training in the field of natural sciences, and Horváth wants to expand this to all disciplines and across the whole country. “One of the main ways to elevate our innovative businesses is to teach our children to be innovative,” he said. “This will probably need ten years to pay off, but this is what we should do. Our aim is to make Hungary strong in our region, and this is what is needed.” Related articlesHungary’s Horizon Europe performance in numbersCommission unlocks Erasmus+ cash for Hungary, Horizon could be next‘Academic Huxit.’ Hungarian researchers speak out on impact of EU ban A more difficult task will be funding. The new government is aiming to increase research spending to 2% of the GDP by 2030, and then increase it to 3% in line with EU objectives. Currently, spending sits around 1.3%. But according to Horváth, the current budget, inherited from the previous government, is “heavily in the negative,” so any plans to increase research spending will have to start next year. Achieving 2% by 2030 already needs a big push, almost doubling the research budget. “This is something we’d definitely like to reach, and something I can see us achieving,” he said. “From the 2030s, I’d like to see an innovative generation growing up that can help us reach the 3% target.” Positivity in the new governmentDespite the many challenges facing Horváth and his team, the mood is positive. “It feels a bit like a start-up right now. Everyone is working 24/7, day and night, trying to do as much as they can. There is a lot of energy,” he said. It is a big change for the state secretary who, like many in his cabinet, is coming from a background in research or business, and not in politics. “Six weeks ago, I was sitting with my microscope and my research PhDs, so it’s been a big change for me,” said the computer scientist, who was previously the director of the Institute of Biochemistry at the Hun-Ren Biological Research Centre in Hungary and worked at the Institute for AI for Health at Helmholtz Munich. But he is relishing the task to transform the country’s R&D landscape. “We feel enormous support from the Hungarian people, but also from Europe,” he said. “We’ve received a lot of letters of support from around Europe. There is big trust there, and huge responsibility on our side. We want to get everything back on track, and there’s a lot to do.”
Founder/CEO and Clinical President of Digital Health Company Sentenced
The founder and former Chief Executive Officer (CEO) Ruthia He of Done Global Inc., a California-based digital mental health company, was sentenced today to six years in prison and a $1 million fine for orchestrating a scheme that used her company’s technology platform, compensation structure, and clinical protocols to unlawfully distribute over 37 million pills of Adderall,
Former DraftKings trader charged in Fresno State hoops betting plot
A former DraftKings sportsbook employee faces felony charges related to a betting scheme involving a Fresno State basketball player who allegedly manipulated his performance in a 2025 game, according to law enforcement records.
Things older than America: Inventions, food, institutions
The United States turns 250 this year — but in the grand scheme of things, that's still quite young.
Jon Prosser responds to Apple lawsuit by blaming the other guy
Prosser denies participating in a “coordinated scheme.”
NHS to reward people who walk 30 minutes a day
The "marathon a month" scheme, developed with former Olympic medallist Sir Brendan Foster, will launch early next year.
Richmond mental health agency operator charged in $49.6M Medicaid fraud scheme
The operator of a Richmond mental health agency faces federal charges after prosecutors say she ran a years-long Medicaid fraud scheme that targeted low-income and homeless Virginians.
UNC basketball champion arrested after illegal sports betting scheme
Former Tar Heel Ed Davis was one of six arrested in the latest betting sting.
'Roadworks rip your business apart - through no fault of your own'
The £10.4m scheme at Hyde Park is throttling trade as well as traffic, say local businesses.
Malik Beasley reportedly indicted as part of sports-betting scheme involving point shaving, prop bets
Malik Beasley was first announced as part of a federal investigation last June.
Nine-year NBA veteran indicted on federal sports gambling charges
Veteran NBA shooting guard Malik Beasley has been indicted on federal charges for gambling related to a sports betting scheme, such as point shaving and prop bets, his attorney Steve Haney told ESPN. on June 29. According to Shams Charania,…
Prescott, Parker present Cowboys with an 'iron sharpens iron' dynamic
Cowboys quarterback Dak Prescott has had issues solving two defensive schemes. With Christian Parker in the building, he may finally figure it out.
Former Washington health care executive pleads guilty to $24 million wire fraud scheme
A former health care executive in North Central Washington has pleaded guilty to wire fraud after prosecutors say he siphoned tens of millions of dollars.
Illinois financial adviser charged with operating Ponzi scheme
Prosecutors allege Paaris Kopsaftis of Des Plaines-based Blackwater Assets took more than $150,000 from clients in a Ponzi-like scheme.
4 charged in Nebraska as part of DOJ national health care fraud takedown
Criminal charges announced today are tied to alleged schemes to defraud Medicare and Medicaid, according to the U.S. Attorney’s Office for the District of Nebraska.
Louisville doctor, nurse and nonprofit founder charged in federal health care fraud crackdown
Federal prosecutors in the Western District of Kentucky announced charges in four separate cases involving alleged schemes to defraud Medicare and Medicaid, misuse medical credentials and controlled substances, and submit
South Korea arrests Shincheonji church leader for meddling in politics, media report
A South Korean court ordered the arrest of Lee Man-hee, the founder of the Shincheonji Church of Jesus, over allegations he orchestrated an illegal scheme for followers to join a political party, news reports said.
Las Vegas woman accused of running illegal multi-million-dollar healthcare scheme in Pearland, prosecutors say
Marizel Yukee is accused of providing medically unnecessary allografts to patients while receiving kickbacks, according to the U.S. Attorney’s Office. Her case is one prosecutors are citing as part of a national crackdown on health care fraud.
455 people including doctors charged in historic $6.5B health care schemes
Over 450 people, including 90 medical professionals, are facing charges in global health care fraud schemes totaling $6.5 billion.
Hong Kong Digital Entertainment Association Presents the 3rd "Future Animation - AI-Assisted Animation Production Support Scheme"
/PRNewswire/ -- Organised by the Hong Kong Digital Entertainment Association (HKDEA) and sponsored by the Cultural and Creative Industries Development Agency...
Two in Hawaii charged in nationwide health care fraud, opioid crackdown
The Department of Justice charged 455 health care professionals nationwide — including two in Hawaiʻi — in alleged fraud and opioid schemes totaling $6.5 billion.
Massachusetts man among 455 charged in nationwide crackdown on health care fraud
A Massachusetts man is among 455 people charged in a nationwide crackdown on health care fraud, with the Stoughton man allegedly carrying out an over $5 million Medicare fraud scheme.
DOJ announces $6.5B healthcare fraud takedown with record Medicaid enforcement
The Department of Justice unveiled charges against 455 people, including 90 doctors and other licensed medical professionals, for their alleged participation in healthcare schemes that involved mor | Law enforcement unveiled charges against 455 defendants for their alleged participation in healthcare schemes, among which fraudulent amniotic wound allografts and undelivered Medicaid services were spotlighted.
Trump administration charges 455 people, including doctors, with $6.5 billion in healthcare fraud
In the Trump administration’s latest effort to crack down on fraud, the Justice Department on Tuesday unveiled charges against 455 people for their alleged participation in healthcare fraud and opioid abuse schemes.
DOJ unveils charges for $6.5 billion in health fraud schemes
The Department of Justice (DOJ) unveiled on Tuesday charges against more than 450 defendants for alleged health care fraud totaling over $6.5 billion in false claims, as part of the Trump administr…
Texas doctor charged in $89M fraud case as administration pushes health care crackdown
The Justice Department has charged a Texas doctor in an $89 million health care fraud scheme, accusing him of billing insurers for medically unnecessary cardiovascular screening tests.
455 people charged in alleged $6.5B health care fraud schemes: DOJ
The DOJ announced criminal charges against 455 people accused of participating in health care fraud schemes involving more than $6.5 billion in false claims.
Texas doctor charged in $89M fraud case as administration pushes healthcare crackdown
The Justice Department says it has charged a Texas doctor in an $89 million healthcare fraud scheme, accusing him of billing insurers for medically unnecessary cardiovascular screening tests for college student-athletes and then rubber-stamping the res...
Man accused of embezzling thousands from Gwinn business with gift card scheme
Jonathan A. Barnes was arraigned in Marquette County District Court on one count of embezzlement of $20,000 to $50,000.
AI-powered healthcare fraud has insurers on their toes
Pulling off health insurance fraud used to take time and skill. Until a few years ago, criminals couldn’t fabricate health records without knowing medical terminology and billing codes. If the scheme involved fooling a call center worker, the fraudster would have to pick up the phone and pose as a
Justice Department sues New York over Medicaid home care ‘fraud scheme’
The Justice Department is suing the New York State Department of Health, the state’s Medicaid director and a company operating a $10 billion home health prog…
Michigan Lawmakers Take Up Bill To Cap Marijuana Business Licenses As Industry Reels From Tax Increase
“We are doing our best to create the right regulatory scheme to be able to adequately enforce the market.” By Ben Solis, Michigan Advance The Michigan Senate is refocusing its marijuana industry license cap legislation to include new barriers to obtaining a license for growers, processors or dispensary operators with outstanding industry-related tax debt—a move […]
'Rich Kids of Beverly Hills' star Brendan Fitzpatrick sued over alleged $80M Ponzi-style scheme
Brendan Fitzpatrick, former star of E!'s 'Rich Kids of Beverly Hills,' is being sued over an alleged $80M Ponzi scheme involving his Sri Lanka-based global mining and commodities company.
US Sues New York Health Officials Over Alleged Fraud in Medicaid Homecare Program
By Jonathan Stempel NEW YORK, June 16 (Reuters) - The Trump administration sued top New York health officials on Tuesday over an alleged scheme to rig the bidding process for managing the state's estimated $10 billion Medicaid homecare program, harming patients and caregivers as well as ...
Same-name candidate disqualified from key Senate race over alleged Dem scheme to confuse voters
Alaska election official disqualified a same-name Republican challenger to Sen. Dan Sullivan, ruling the candidacy was designed to confuse voters.
More Galaxy Z Fold 8 ‘Ultra’ leaks confirm it looks just like a normal Samsung foldable
Previous reports indicated that Samsung has reassigned the standard naming scheme to a shorter, wider foldable. The latest leaks from...
Science, Natural Resources Committee Democrats Demand Trump Administration Cease Illegal and Expensive Scheme to Dismantle NSF Ocean Observation System
The House Committee on Science, Space and Technology
NFL Analyst Makes Prediction for Bucs' Season
Former Super Bowl champion Logan Ryan envisions a dominant NFC South run for Tampa Bay, forecasting a double-digit win season fueled by Todd Bowles’ sophisticated defensive schemes.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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