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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Prime Healthcare says it’s saving a Maine health system. Many question its tactics.
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Lowering New York's high energy costs key platform ahead of Election Day
Both the Democrat and Republican candidates say they’ve got a plan.
Lowering New York's high energy costs key platform ahead of Election Day
Both the Democrat and Republican candidates say they’ve got a plan.
Lowering New York's high energy costs key platform ahead of Election Day
Both the Democrat and Republican candidates say they’ve got a plan.
American Express Now Offers High-Yield Business Savings Account
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Golden 1 Credit Union Expands Business Services Offerings to Support Communities and Economic Opportunity Across California
/PRNewswire/ -- Golden 1 Credit Union (Golden 1) today announced the expansion of its Business Services offerings, with business checking, savings and money...
Golden 1 Credit Union Expands Business Services Offerings to Support Communities and Economic Opportunity Across California
Golden 1 Credit Union (Golden 1) today announced the expansion of its Business Services offerings, with business checking, savings and money market accounts at the core of a growing suite of services designed to support California businesses. The expansion deepens Golden 1's commitment to entrepreneurs, sole proprietors, micro and small businesses, nonprofits and community builders across California, while broadening the resources available to businesses throughout the state.
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Verizon Wireless, T-Mobile resolve lawsuits over ad campaigns
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Cancer advocates join physician groups to defend Florida vaccine mandates
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Laredo Public Health hosting Get Ready Day workshops
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I've spent 20 years caring for 5 loved ones. It cost me my career
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Palestinian Brand Recalls Olivia Rodrigo Saving Their Business
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Intermountain Health Primary Children's Hospital Behavioral Health Campus in Taylorsville Marks One Year Anniversary This Week
One year after opening its doors, the Intermountain Health Primary Children’s Hospital Behavioral Health Taylorsville Campus is marking a milestone year of expanding access to lifesaving mental health care for Utah children, teens, and families.Since opening in September 2025, the 90,000-square-foot campus at 5770 South 1500 West in Taylorsv...
New Playbook Reveals Health Systems Are Saving Millions on EHR Training
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He Poured His Retirement Savings into a Business — and It Failed Spectacularly: 'I'm Working Harder Than Ever.'
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Save 40% on Autodesk’s Media and Entertainment Collection — thousands of dollars worth of software in a single bundle
Big savings for big ideas
Meet a Health Hero Finalist: Sharon Pervez-Khan
After her daughter Elora was diagnosed with an incurable, cancerous brain tumor, the Villanova mom made it her mission to accelerate research, funding, and life-saving treatment.
She is my hero’: UT Health East Texas EMS honors 3-year-old girl’s bravery during mother’s seizure
UT Health East Texas EMS recognized three-year-old Naomi “Emi” Vatavuk Tuesday for her lifesaving actions during a medical emergency her mother suffered earlier this year.
Years before Nepal floods, scientists pitched a seismic warning system
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He lost $180K in retirement savings, now drives Uber and Lyft at 58
Bill Lewis, a former Wall Street broker, now drives for Uber and Lyft after losing his retirement savings in a failed franchise venture.
Alabama Department of Mental Health highlights life-saving resources for Prevention, Recovery Months
This September, the Alabama Department of Mental Health and statewide partners are working to raise awareness, fight stigma, and share life-saving resources.
Alabama Department of Mental Health highlights life-saving resources for Prevention, Recovery Months
This September, the Alabama Department of Mental Health and statewide partners are working to raise awareness, fight stigma, and share life-saving resources.
Alabama Department of Mental Health highlights life-saving resources for Prevention, Recovery Months
This September, the Alabama Department of Mental Health and statewide partners are working to raise awareness, fight stigma, and share life-saving resources.
Alabama Department of Mental Health highlights life-saving resources for Prevention and Recovery Months
This September, the Alabama Department of Mental Health and statewide partners are working to raise awareness, fight stigma, and share life-saving resources.
Red Cell Partners lands Pentagon contract that could generate $100M for its portfolio startups
Red Cell Partners, a McLean venture firm, won a Pentagon contract worth up to $100 million to identify cost-saving opportunities using AI technology from its portfolio startups.
"Austerity measures on humanitarian aid worsen severe health crisis in Sudan"
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Doctors reunite with one-year-old after saving her life
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UK business group urges smaller state pension increases ahead of budget
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After 'Lake America,' Trump suggests a new name for the state of New Mexico
The White House reposted Trump's Truth Social image showing New Mexico crossed out and rebranded as "America" days after the Lake America order.
Qinwen Zheng Shocks Madison Keys in US Open Third Round
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This Samsung TV deal stopped me mid-scroll. Save $1,200 right now
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Long-term allies and verifiable reality must make way for Saving Private Nige
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‘You Haven’t Got a Business Yet, You’ve Got a Theory’: Dave Ramsey to 25-Year-Old Working 3 Jobs
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3 Stocks Tied To Rising HSA Use Including CVS Health Stock
Health Savings Accounts are quietly becoming a core part of how Americans pay for care, with more employers auto enrolling workers and pairing HSAs with high deductible health plans. That shift channels more money through platforms that handle contributions, custody, and investments. For investors, the question is which stocks may benefit most from this structural change. This article walks through three HSA exposed stocks from our screener and what the news could mean for each. The three...
The 4% rule creator thinks you should ditch popular kind of retirement fund
"I don't believe in the target-date concept," says Bill Bengen, who created one of the golden rules of retirement savings.
15 discouraging hours with Onimusha: Way of the Sword, and 10 brilliant ones with He Who Watches
In the last few weeks, while playing some video games that I might review, I emailed two cries for help. I sent the first to a rep for Capcom, confessing that the company’s samurai game Onimusha Way of the Sword (out today for PC and console) was crushing me. “Feels like I’m playing ‘hard’ mode, not ‘normal,’” I wrote. “And I don’t want to have to knock it down to “story”. I’m exploring, trying to level my gear, but these two-phase boss fights with no mid-fight checkpoints are brutal.” I wagered I was only about halfway through the game, if that. I wasn’t sure I could keep up with the steepening difficulty curve. Was I missing something? Then, on Monday, I took some photos of some puzzles that were baffling me in the mind-bending He Who Watches (out now on PC), wrote out lengthy descriptions of how I’d been trying to solve them and asked Bobby Vanden, the game’s solo developer, for a nudge in the right direction. I told Vanden I’d spent hours on these puzzles. “I’m stuck in triplicate,” I told him. Could he tell me if the solutions I was attempting were even on the right track? I didn’t mention that the puzzles—coupled with major time pressures from other work—were stressing me out so much that playing the game was giving me headaches. This double dose of panic was unusual. I’m used to managing a workload full of reporting and reviewing, used to a crowded schedule and the need to stay calm amid the bustle. But I was stressed about these games. No one was forcing me to review them, nor even play them. I’d simply found them interesting enough to start, hoped they’d be interesting enough to write about and I’d sunk hours into them assuming I’d made the right call. Suddenly, however, I felt trapped. I was emailing for a way out. Above: This guy took me about an hour to beat. The feedback I got from Capcom confirmed my fears. They didn’t say it, but I will: Onimusha Way of the Sword is not for me. It’s a brutally hard game in need of a normal difficulty level. It’s a game that spikes so severely during its abundant boss fights—yet offers such flawed ways to improve when outside of them—that it feels like a bait-and-switch. In the new Onimusha, you play as famed samurai Musashi Miyamoto, aided by a magical soul-absorbing gauntlet that is possessed by a lady who offers advice. (Way of the Sword is a continuation of Capcom’s long-dormant Onimusha series, but that set-up had me wondering if the company was cribbing from their ill-fated Bionic Commando reboot; read about “wife-arm” when you get a chance). Way of the Sword is partially set in 17th century Kyoto, an explorable city where Miyamoto can fight demons, help civilians and eventually rescue ghostly dogs. The city evolves over time, with new mini adventures and obtainable loot on offer, all feeding into systems that promise to upgrade your gear and sword-fighting skills. Upgrades, however, are so incremental as to be imperceptible, causing the exploration of Kyoto to feel like inconsequential busywork. From that hub, players can go on linear missions into forests and old temples, where they will encounter many of the game’s tough bosses. Combat in Way of the Sword is akin to many modern melee games. Players are asked to mix attacks with dodges and parries. They’re encouraged to deplete an enemy’s stamina bar in order to do greater damage to its health bar. The old Onimusha games’ signature move was the issen, a counter-attack so sudden it’s all but pre-emptive. You strike just as they begin to strike toward you, beating them to the cut. By definition, the issen is a high risk move, leaving you wide open to pain. It feels risky in the game, especially against bosses, who can maul you in just a few blows. A game might train you to perform an issen well by offering a variety of lesser enemies who are not as tough as the boss but get close. Or it might offer a toehold against bosses by saving or checkpointing the player’s progress when a boss’ first health bar has been destroyed and before the second health bar appears. It might offer the less skilled player a chance to over-level their character, should the player simply commit to playing through its optional sidequests. Way of the Sword does none of this. Fighting its trivially easy grunt enemies and then its ferociously adept bosses is like playing a game of chess where I’ve got a rook, while the opposing side is all pawns and five queens. Bosses simply don’t checkpoint. You may be able to clear a boss’ first phase without taking much damage. Good for you. Do it again, every time you fail the second phase. As for the the central Kyoto hub, I kept pace with all of its added side activities and never felt like I was overpowered. Bosses could still easily buckle me. The new Onimusha, I concluded, is just too discouraging to keep playing. The advice I got from Capcom had been well-intentioned. They reminded me of the game’s various systems. They alerted me to an optional assist that flashes recommended button inputs (basically: counter this move; dodge that move). It was a little helpful. So was dropping down to “story mode,” which I tried last night. Story mode turns on those button prompts by default. It makes countering and dodging way too easy, nearly automatic. I don’t consider myself a master of action games like these, but I’ve cleared the likes of God of War, Stellar Blade, Star Wars Jedi and others of sub-Sekiro difficulty and had a fun time doing so. Not here. Not yet. Unless they patch Onimusha: Way of the Sword and add a middle difficulty or just checkpoint the damn bosses when they’re between health bars, my streak of loving Capcom games released in 2026 will likely end at two. It’s a shame, because I was having a good time finding those ghostly dogs. And then there’s He Who Watches, a phenomenal first person puzzle game with Portal vibes, except instead of a portal gun you’ve got a magical bow that shoots one arrow that can activate switches or be used to drag blocks. The twist is an actual twist: you can also walk on walls and the ceiling, reorienting gravity as you do, thereby placing blocks onto those other surfaces. Walking on walls and ceilings to solve problems is really the best thing. Would that I could in reality. He Who Watches consists of locked-room challenges, each brief enough to only require about a minute to actually solving, though it will take five, 10, eventually 30 minutes to figure out said solutions. They are not obvious! It’s a game of layered mechanics and shocking solutions. For example, see if you can follow this: You can drag a block to a wall. Then you can walk on the wall, which now feels like the floor, and drag that block across the wall. Later, back on the floor, you might realize you can look up. The block is still on the wall, stuck to it. You can shoot your magic arrow to its underside. Doing so creates a tether, so that you can yank the block off the wall and carry it, as if it were a balloon, into the spot where you need it to be to solve the puzzle. Here, watch Vanden explain some of the game’s basics in this launch trailer: As with any great puzzle game, the solutions to He Who Watches’ puzzles elicit relief and amazement. Oh my god, that worked! I didn’t even think that could be possible! Learning to solve the game’s puzzles feels like learning magic. But, oh, does the game get hard. Its Steam reviews, mostly glowing, are full of players remarking how quickly He Who Watches made them sweat. Wrote one: “loving this one already although my brain is hurting!” Wrote another: “As you get further in the game it feels like you need an IQ level of at least 120+.” Vanden has shown some mercy. Each locked room puzzle includes an optional junior version of the puzzle, meant to teach you. Difficulty nevertheless ramps severely. By the time I was emailing Vanden for help, I was struggling to even clear one of the hint puzzles. When I messaged him, my stress was exacerbated by strange things I’d found in the game’s various hubs: suspicious passageways, odd blocks and some intriguing locked doors. These were hints of secrets, I realized, yet I sensed I needed to play further into the game to understand them. I was stuck, but I wanted to see the rest. Vanden offered to give me the exact solutions, to solve those three puzzles for me, but first he gave four nudges. Three were for the specific puzzles, but his best hint was for all and ultimately proved to be a terrific life lesson: go back a bit, he suggested. Do the puzzles right before those. They were teaching you something. Focus on what their lesson was. Don’t rush, in other words. Recognize what you’ve accomplished. Build off of that. I did so. I absorbed the lessons. I saw those three tough puzzles in a new light. I solved one the night after he wrote back, another the morning after. I left a third for another time. I didn’t need it and I wanted to plunge deeper into the game, closer to the moment when I was sure I could start unlocking those secret doors. My head stopped hurting, too. He Who Watches feels special. It’s got more challenges, and I’m undeterred. It’s also nice that its puzzles don’t have a surprise second health bar. Game File is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Item 2: In brief… 🎮 Ilari Kuittinen, co-founder of Helsinki-based Housemarque (Super Stardust HD, Resogun, Returnal) has stepped down from his studio, after a 31-year run, saying he’s “ taking a rare and well-deserved breather.” Sony purchased Housemarque in 2021, and the studio released its newest game, Saros, earlier this year. Trend-watch: Sony-owned Insomniac saw its founder Ted Price retire in early 2025, after a 30-year run. Sony-owned Sucker Punch saw its co-founder Brian Fleming step down in late 2025, after a 28-year run. 👀 Savvy Games Group chief Brian Ward is stepping down from the Saudi-government-backed games conglomerate, Bloomberg reports. No word on a long-term successor yet, nor if this augurs any closer integration between Savvy and Electronic Arts. EA was purchased by a consortium led by Saudi’s sovereign wealth fund, in early August. 💿 Square Enix has denied a Japanese media report that the company was planning to go private. In very different Square Enix news, the company revealed that the physical version of Final Fantasy VII: Revelation, the April 2027 finale of its radical remakes of FFVII, will include just one disc in its case, requiring a download for the rest. The first two FFVII remakes in the trilogy shipped on two discs apiece. While Square hasn’t commented on the reason why, a feature here in Game File last month broke down the processes and costs for physical games. The expense of a second disc comes out of the game publisher’s cut of each copy. Square could be saving in excess of a dollar a copy with this move. 🟥 Grand Theft Auto IV’s 26-minute ’‘extended look” gameplay showcase that premiered on Netflix last week—and was exclusive to the platform for six hours—drew 31.1 million views in its first four days, the streamer announced. (Netflix calculates views as total viewed hours divided by runtime; excludes replays). Compared to YouTube: The version that later premiered on Rockstar Games’ YouTube channel is sitting at 22.6 million views after seven days (YouTube’s more liberal counting system tallies anyone who viewed even just the first few second.) Compared to other Netflix mega-events: Last year, Stranger Things season 5’s first four episodes, which debuted together, drew a record 59.6 million views in their first few days on Netflix. For more of a live event type of comparison, in 2024, the Jake Paul vs. Mike Tyson boxing match drew 65 million concurrent streams as it happened; Netflix didn’t release live numbers for the GTA premiere. ☁️ Microsoft is changing the way it charges for cloud gaming, from an all-you-can-play offer for Xbox Game Pass subscribers, to caps for the subscription’s tiers (15 hours per month at the Ultimate tier), with the option to buy more hours in bulk beyond that. The company also said it will sell batches of cloud gaming time to non-Game Pass subscribers, details TBA. Microsoft does not release figures for cloud game usage, but said its changes would impact 4% of Game Pass subscribers. That implies a small portion of its subscribers exceed the 15-hour monthly mark. Cloud gaming offers the promise of playing games without the need for console or PC hardware, as the graphics, sound and controls are all transmitted via a streaming connection. Microsoft notes that its cloud gaming service can be used for a range of things, including Xbox One players using it to play newer-gen Xbox Series games via streaming; and people playing games via streaming, sans any console, “in markets where consoles are less available or affordable.” (That latter use case could even be relevant in Xbox’s home market soon, as console prices keep rising.) Take Two Interactive chairman Strauss Zelnick recently told investors he expects game-streaming tech, which has been only lightly adopted by gamers for over a decade, to be widely used within three years. 🇺🇸 The Trump administration has published multiple agenda-driven web video games to the White House’s website. One called Build The Wall partially clones Tetris as it asks players to build a wall to stop a “zombie border siege.” While actual Tetris involves clearing lines and basically not building a wall, the Trump-backed game omits the line-clearing aspect (and omits the fun as well). On Instagram, Tetris’ official license holders reacted by stating: “At Tetris we believe in the power of connection and bringing people together, not dividing them. To our fans everywhere: we love you, we see you, and we’re grateful to have you in our community. P.S. The Tetris Company was not involved in the creation of ‘Build the Wall.’ P.P.S.: We take copyright infringement very seriously.” Item 3: The week ahead: Tuesday, September 8 Game releases: Mewgenics (consoles; already out on PC) is an engrossing tactical combat game (with cats). It is getting its console port right after the release of a Star Wars tactics game and ahead of the late September launch of a Fire Emblem–a bumper crop for the genre. Wanderburg (PC) is an auto-shooting game like Vampire Survivors, but you’re a castle on wheels Event: Nintendo airs a 30-minute Nintendo Direct (10am ET) focused on The Legend of Zelda’s 40th Anniversary. A full unveiling of the upcoming remake of The Legend of Zelda Ocarina of Time is expected. Will they also show footage from next year’s live action movie? Tease the next big 3D Zelda? Add Link to Mario Kart World? Shadow-drop a new Tingle game? Wednesday, September 9 Event: Nintendo again! On this day, they’re planning to air a 45-minute Nintendo Direct (10am ET) focused on games heading to Switch 2 this winter. Followed by about an hour of gameplay demoed by the company’s Treehouse team. The September Nintendo Directs are always some of the year’s biggest. The 2025 edition included announcements of several major 2026 Switch/Switch 2 games: Pokémon Pokopia, Mario Tennis Fever, Yoshi and the Mysterious Book, Fire Emblem Fortune’s Weave. Plus the return of the Virtual Boy. Friday, September 11 Game release: EA Sports NHL 27 (PlayStation, Xbox) is a hockey game. There are so few that an indie studio that had been making wacky sci-fi first-person shooters just announced that, hey, we’re going to fill a void and make a hockey game for PC.
100 Years Strong: American Savings Bank’s Century of Community Impact
This year, American Savings Bank (ASB) celebrates 100 years of serving and investing in Hawai‘i’s residents, businesses and communities. To reaffirm its
NY health insurance rate hikes approved. How much you will pay in 2027
NY's Department of Financial Services says it rejected higher rate hikes sought by insurers, saving consumers $1.6B via lower approved rate increases.
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KeikiCo Business Plan Competition offers Hawaiʻi students a chance to win $25,000 for their school
With Hawaiʻi students back in the classroom, American Savings Bank is calling on the state’s next generation of entrepreneurs to put their biggest ideas to the test through the 2026 KeikiCo Business Plan Competition.
Austin will outsource adult sports leagues after backlash
The parks department announced it would cancel city-led adult indoor basketball and volleyball leagues, saving about $400,000 per year.
Miami Hurricanes saving state from total embarrassment
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GoodRx offers health subscription for families, to launch as employee benefit in 2027
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Virtual e-health system safely monitors cardiac devices and cuts costs
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Federal grant cuts hit Colorado studies to make healthcare more efficient
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Amazon Offers Early Savings on 2026 Mac Mini, Plus Record Low on AirTag 2
Apple introduced the M6 and M5 Pro Mac mini this week, and Amazon currently has the first pre-order discounts on these models ahead of their September launch. Below, we're also tracking a new record low price on the AirTag 2 during Amazon's Labor Day event. Note: MacRumors is an affiliate partner with some of these vendors. When you click a link and make a purchase, we may receive a small payment, which helps us keep the site running.
Vandalia Health expands free public access to naloxone at northern region hospitals
Vandalia Health is expanding access to life-saving overdose reversal medication by installing public naloxone distribution boxes at hospital entrances throughout its northern region. The first boxes are being installed at Vandalia Health Mon Medical Center in Morgantown, Vandalia Health Mon Marion Neighborhood Hospital in White Hall, Vandalia Health Mon Preston Memorial Hospital in Kingwood and Vandalia Health Mon Stonewall Jackson Memorial Hospital in Weston. Additional boxes are expected to be install...
Why did Austin axe adult indoor sports leagues for such minimal savings?
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Sophie's double life-saving gift to a stranger and science
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43 Years Ago, Scientists Dropped Gophers Onto a Volcano. Today, They’re Tiny Heroes.
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Boston Scientific hit by cyberattack causing ‘disruptions’ to parts of its business
This year has seen a growing number of medtechs hit by cyberattacks, and now Boston Scientific has become the latest victim. In an SEC filing posted Aug. 26, the medtech giant said it had detected a “cybersecurity incident” the day before. The incident has affected certain parts of its information technology systems, something that “has resulted in a global disruption to the company’s operations.” The incident has hit not just its information systems but also its business applications, which “support aspects of the Company’s operations,” it said in the filing. This includes its ability to process and ship customer orders. Boston Scientific said it is working to restore the systems, but the timeline remains unknown. Related Baylor Genetics hit by cybersecurity attack targeting patient, staff information As the company investigates the incident, it remains unclear how significantly its business will be affected. “Accordingly, the Company has not yet determined whether the incident is reasonably likely to have a material impact.” The company’s shares were down 3.5% in premarket trading as the news broke. This adds another layer of pressure for the medtech, which last month revealed a new global restructuring program that starts this year and is slated to be completed by 2029. The company said at the time that it “does expect some headcount reductions to result from these restructuring activities,” but did not provide any numbers or specify areas where the cuts may be made. It added, however, that new jobs are also set to be “created in areas of growth.” It was also forced to cut its sales guidance in Q2, saying in late July that it now expects full-year 2026 organic revenue growth of 5% to 6%, down from its previous guidance of 6.5% to 8%. Boston Scientific is one of a growing number of life sciences companies, notably medtechs, that have been hit by cyberattacks this year. These include Abbott, iRhythm, Medtronic and Stryker, as well as Big Pharmas Amgen and Novo Nordisk.
Health Savings Account Participation on the Rise, Retirement Strategy Needs Attention, PSCA Finds
ARLINGTON, Va., August 25, 2026--The Plan Sponsor Council of America’s (PSCA) 2026 Health Savings Account Survey shows increased participation as 83% of employees contributed to their Health Savings Account (HSA) in 2025, up from 73.4% in 2024. Despite the growth, only one-quarter of employers position HSAs as part of a long-term retirement savings strategy.
Healthcare saving hacks to consider before November's open enrollment
As insurance costs continue to rise, coupled with recent changes to the Affordable Care Act, some of the subsidies people count on have been rescinded. So how do you save money on healthcare?
'GTA 6' Leak Reveals New Feature Rockstar Was Probably Saving For Netflix
The world of Grand Theft Auto 6 will be impacted by its evolved day and night cycle
Franklin County increases free Narcan access to fight overdoses
Health officials in Franklin County, New York, say overdoses are likely being underreported. Now, they're distributing free Narcan through "red boxes" and partnering with first responders to leave the life-saving drug at homes where it's warranted.
‘Reading Rainbow’ Host Mychal Threets Shares Health Update After ‘5-Day Psychiatric Hold,’ Says Doctors ‘Saved My Life’
Mychal Threets revealed in a video on Threads on Aug. 22 that he was hospitalized for five days on a ‘psychiatric hold’ and thanked medical staff for saving his life.