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Apple Announces iPhone Duo Apps Can Now Be Submitted to App Store
Apple today announced that apps optimized for the iPhone Duo can now be submitted for App Store approval, ahead of the foldable device launching on Friday, October 23. While existing App Store apps will automatically run on the iPhone Duo, only apps built with the iOS 27.1 SDK or later can dynamically resize to fill the entire space of the inner display, whereas unoptimized apps will have black borders.
Dave Portnoy on Fox ‘Big Noon’ Exit: Ryan Day Thinks I ‘Doxxed’ Him
Portnoy tells FOS that Ohio State pushed for his removal.
Congressional candidates discuss expanding executive power and need for political will
Congressional approval ratings are in the tank. By some measures this is one of the least productive sessions of Congress in living memory. WGLT's Charlie Schlenker reports those things may not change much any time soon.
Muchacho comes to Decatur; Kelly’s Market under new ownership
Muchacho, a West Coast-style taco shop with locations in Atlanta, plans to open its third spot in Decatur. The city will consider its alcohol license on Oct. 5, after police approval.
Lilly's Jaypirca approved as first-line CLL therapy
Eli Lilly’s Jaypirca has won FDA approval for previously untreated chronic lymphocytic leukemia and small lymphocytic lymphoma.
Collaborating with Canadian Scientists on Marine Carbon Dioxide Removal Research
I first met Dr. Helen Gurney-Smith in fall 2024, when Dr. Shannon Meseck and I drove just beyond the U.S.-Canada border to the St. Andrews Biological Station in New Brunswick. We went there to study larval sea scallop respiration when exposed to near-future temperature and pH. This past winter, Dr.
Mac Users Reclaim Storage With New Apple Intelligence Removal Tool
A new open-source tool is making waves in the Mac community by helping users reclaim valuable storage space taken up by Apple's AI models. Called "RemoveMacAI," the tool disables Apple Intelligence on macOS 27, removes its downloaded models, and prevents them from being downloaded again. In macOS 27, Apple removed the toggle to disable Apple Intelligence wholesale, and simply disabling individual features doesn't remove the models from your Mac's drive.
King Drive Business Improvement District budget expands for 2027
The Historic King Drive Business Improvement District's 2027 operating plan, which includes a budget increase, will head to the common council for approval.
Ed Sheeran's newest opening act praises Macklemore amid tour drama
After other musical acts quit his tour following Macklemore's removal for pro-Palestinian messaging during a performance, Ed Sheeran found a replacement opening act for a night.
Ed Sheeran's new tour opener speaks out on Macklemore, calls for 'common ground'
After other musical acts quit his tour following Macklemore's removal for pro-Palestinian messaging during a performance, Ed Sheeran has found a replacement opening act.
Editorial: Public input should come before approval
A recent Reno town hall revealed tensions between developer Jacobs Entertainment and residents regarding urban design and public engagement.
Denis Shapovalov retires, Carlos Alcaraz advances to Japan Open semifinals
Denis Shapovalov was playing a high level of tennis against Carlos Alcaraz before suffering the injury that forced him to retire at the Japan Open.
Badenoch returns to Conservative conference much stronger than a year ago
Approval ratings for Tory leader and her party have crept up as she has asserted her style and authority but big challenges lie ahead
Change to bankruptcy law may help speed up, give relief to small biz
Small businesses may get an easier path to restructure their debt faster while offering greater flexibility in negotiating with creditors under a change in law waiting President Trump's approval.
The political walking dead: Germany’s zombie chancellor
A string of poor election results has left Friedrich Merz with unprecedentedly low approval ratings
Portland’s Arts Tax Hike Was Invalid, City Business Group Says
The Portland City Council in Oregon needed to get approval from voters before increasing its arts tax by more than 40% earlier in May and, therefore, the tax hike should be nixed, a city business group said.
Summit County Health Department to host free drive-thru vaccine clinics
The clinics will offer flu and COVID-19 vaccines to anyone, regardless of insurance status. No appointment is necessary, and residents can stay in their vehicles while they receive their vaccines.
ACA fraud crackdown removing 760,000 enrollees is squeezing health insurer profits
Shares of Centene, Molina, Elevance, and UnitedHealth have all fallen since Vice President JD Vance announced the removals last week
Rangers Could Trade Eovaldi to Create Payroll Flexibility
Chris Young must weigh Nathan Eovaldi’s reliability against a looming $25 million salary as the Texas Rangers prioritize financial agility and roster youth after a tough year.
Trump’s Approval Rating On The Economy Hits All-Time Low In 2 Polls This Week
Trump has a 17% approval rating on his handling of the cost of living.
A Heart Valve That Grows Up With The Patient Wins FDA Approval
By Ellyn Vohnoutka HealthDay ReporterFRIDAY, Oct. 2, 2026 (HealthDay News) — Children born with certain heart defects may face fewer open-heart surgeries, thanks to a new replacement valve that grows with them. The U.S. Food and Drug Administration (FDA) on Thursday approved the Autus ...
Analytics vs. players: Red Sox tensions boil over
The Red Sox's wild card sweep exposed a deeper rift between players and management over analytics-driven in-game decisions, most notably the early removal of Sonny Gray in Game 2.
MD Health Department fined $4.7M so far for delayed psychiatric care
Maryland is scheduled to approve a six-figure payment after the Department of Health failed to provide prompt psychiatric care to criminal defendants, an ongoing issue that has racked up a cost of $4.7 million.
Judge blocks Trump from firing Seattle US attorney who had job for an hour
President Donald Trump cannot fire US attorneys who have been appointed by courts, a federal judge in Washington state said Thursday in a first-of-its-kind ruling that tests the scope of a president’s removal power under the Constitution.
Most Americans blame Trump for high prices as his economic approval hits new low, AP-NORC poll shows
A majority, 65%, of U.S. adults now blame Trump’s policies for persistently high costs more than factors outside of his control, signaling growing weariness over his aggressive use of tariffs and continued unhappiness with the war with Iran.
Scientists Found a “Third State” Of Being Between Life and Death
Frog and human cells can reorganize after removal from their host, raising open questions about biological death and potential uses in regenerative medicine.
Video Essayist And YouTuber Jacob Geller Removed From MinnMax Following Sexual Assault Allegations
Jacob Geller has not commented on the allegations or his removal from the games podcasts.
FDA puts aging on its regulatory science agenda
At ARDD 2026, senior FDA officials sketch how a therapy targeting aging might one day reach approval, revealing that longevity is a priority.
Arizona appeals court upholds rejection of Marana data center referenda
The Arizona Court of Appeals, Division Two has upheld the rejection of two referendum petitions challenging zoning approvals for a proposed Marana data center project, ruling that the petitions failed to meet Arizona’s strict legal requirements for referenda. The decision affirms an earlier Pima County Superior Court ruling and leaves the Marana Town Council’s January […]
Trump says Secret Service wants him to ‘take down’ Oval Office
The president also said he is looking into designating the White House room as a “federal landmark,” potentially preserving his changes.
Kennedy to roll out $10 million challenge to encourage Presidential Fitness Test in schools
Since President Trump revived the test last year, the administration has looked for ways to boost participation.
90 Ideas in 90 Minutes: Billy Weathers
Impactful leadership takes removal of ego Leaders can unintentionally halt their own mission. Leadership is servitude. Sometimes the idea outgrows you, or was never about you to begin with. The best leaders are able to remove themselves from the equation to focus on the outcome and betterment of the collective. You can build an organization around…
Inside Larry Ellison's Wide Web of Power, Money and Politics, As Oracle's Data Centers Claim Force Majeure
The $200 billion software titan has suctioned himself to many hubs of influence—from data centers to TikTok to Hollywood studios to the Oval Office itself. Tom Dotan dives deep into Ellison’s kingdom, starting on the island enclave of Lanai.
Brown: Trump’s $15 billion Iowa surprise roils Minnesota politics, but merits skepticism
"On Monday, President Donald Trump welcomed Iowa officials and the Minnesota iron mining company Mesabi Metallics to the Oval Office for an announcement. The news he revealed was stunning," columnist Aaron Brown writes.
Trump’s White House visitor screening center poised for approval
The project, which would revamp how visitors enter the White House grounds, is one Trump construction effort that has drawn wide agreement.
Broward Health Coral Springs Advances Heart Care with First PFO Closure Using the GORE® CARDIOFORM Septal Occluder
Dr. Pablo Rengifo-Moreno with the team that completed the first PFO closure procedure using the GORE® CARDIOFORM Septal Occluder at Broward Health Coral Springs. Broward Health Coral Springs is proud to announce the successful completion of its first PFO (patent foramen ovale) closure procedure using the GORE® CARDIOFORM Septal Occluder, marking a significant milestone in […]
Business Community Signals Openness to Removing Public Vote on Nuclear
PLYMOUTH — Gov. Maura Healey’s mission to restore nuclear power to Massachusetts has put the local business community at odds with nuclear watchdog groups. Advocates worry that the removal of […]
Senate reaches bipartisan deal on permitting bill to speed approvals of new energy projects
Senators from both parties said Wednesday they have reached a bipartisan deal on legislation aimed at speeding up permitting reviews for new energy and infrastructure projects that now face yearslong delays as lawmakers seek to meet growing demand for electricity and other forms of energy.
Samsung's New Smart Glasses Arrive at FCC for Approval
Smart glasses are certainly having their moment, both good and bad. I think it’s obvious that the world has seen the benefits of wearing a pair, but there is also that creepy, privacy nightmare side that has given us the ick. Still, Samsung and Google and their design partners will not be deterred from launching...
Alaska Airlines is moving to join American's transatlantic and transpacific revenue-sharing deals
The carriers plan to file for antitrust immunity with the U.S. Department of Transportation, with approval expected to take months
What's causing health insurance costs to increase more for 170K in RI
Rhode Island Attorney General Peter Neronha calls for "bold" reform just after state announces new rate approvals.
Fewer California Republicans approve of Trump, poll says. That could hurt GOP midterm chances
With gas prices high and an unpopular war dragging on, President Trump’s approval has slipped with California Republicans, a poll shows
'Illegal activity' prompts liquor denial, tobacco hearing for Peoria business
PEORIA - A convenience store situated along Knoxville Avenue will not be allowed to sell alcohol, despite narrowly receiving site approval following weeks of debate at City Council.
Paramount streaming chief Cindy Holland exits studio
The announcement comes as Paramount waits for a judge's approval of its $111-billion purchase of Warner Bros. Discovery.
American Airlines and Alaska Airlines announce plans for Alaska to join the Atlantic and Pacific Joint Businesses
The carriers anticipate filing for approval and antitrust immunity with the U.S. Department of Transportation and seeking other relevant approvals from international regulators in the coming months.
Mike Lee blocks effort to prevent Trump from tearing down memorials
Sen. Mike Lee (R-UT) on Monday night blocked a bipartisan effort to prevent the Trump administration from demolishing the John F. Kennedy Center for the Performing Arts without congressional approval. Sen. Jeff Merkley (D-OR) attempted to pass the Protecting Presidential Memorials Act, a bill he co-led with Sen. Lisa Murkowski (R-AK), by unanimous consent. The […]
EigenQ and Silicon Valley Acquisition Corp. File S-4 for Proposed Business Combination
EigenQ and SVAQ have filed an S-4 with the SEC for their proposed business combination, subject to shareholder and regulatory approvals.
Protect College Sports Act gains Senate approval in bipartisan vote
The Protect College Sports Act took its next step forward on Monday, with the Senate voting overwhelmingly 77-22 in favor of the proposed federal legislation reforming college athletics.
The Senate just passed a historic bill to federally regulate college sports. What happens now?
Senate approval is a massive win for the NCAA and its conferences, but the Protect College Sports Act must pass the House, too.
Toward a post-Trump politics
From the clutter of midterm election poll results, it’s possible sometimes to see new patterns of political support emerging. The overall pattern, as it stands, makes some sense. As in the 2006 and 2018 off-year cycles, the Republican president’s job approval had sagged to well below 50%. Polls at this point in the year showed […]
Ranking Member Markey: SBA Administrator Loeffler, Trump Administration are Refusing to Answer to America’s 36+ Million Small Businesses and Workers, Leaving Main Street Behind
Loeffler canceled her scheduled Sept. 30 appearance before the Senate Small Business Committee, has not appeared before SBC in more than a year (Washington, September 28) – Ranking Member Edward J. Markey (D-Mass.) today released the following statement after Small Business Administration (SBA) Administrator Kelly Loeffler canceled her scheduled Wednesday appearance before the Small Business and Entrepreneurship Committee. Administrator Loeffler has not appeared before the committee in more than a year and has consistently refused to provide substantial answers to committee members in person, in writing, or via requested briefings. In June, Ranking Member Markey led every Democratic member of the committee in calling on Administrator Loeffler to appear before the committee to answer for the Trump administration’s cruel attacks on American small businesses, entrepreneurs, and workers. The Democratic lawmakers still have not received a response from Administrator Loeffler. “It is unacceptable that Administrator Loeffler chose to cancel her appearance before the Senate Small Business and Entrepreneurship Committee. The Trump administration is once again ignoring the more than 36 million American small businesses, entrepreneurs, and workers who drive our economy and enrich our communities by refusing to answer questions about this administration’s reckless economic policies. It has been more than a year since Administrator Loeffler has appeared before our committee and answered questions from both Democrats and Republicans. Since then, the Trump administration’s attacks on Main Street have only worsened. “Small businesses are facing record high gas and diesel prices, skyrocketing healthcare costs, and never-ending uncertainty from Trump’s trade war with the world. Trump has terrorized Main Streets across the country with violent ICE raids, destroying families, communities, and local economies. Meanwhile, Administrator Loeffler and the Trump SBA have been in a Witness Protection Program, ignoring the Pain on Main Street that they have created. They have chosen to make drastic cuts to SBA funding and essential, bipartisan programs, including the closure of the SBA office in Springfield and removal of the SBA office from Boston; directly attacked immigrant small business owners and destroyed the promise of the American Dream; and proposed shortsighted small business size rules that would benefit billion-dollar businesses over actual small businesses. “It’s clear that Administrator Loeffler, President Trump, and their CEO billionaire buddies want to turn the Small Business Administration into the Big Business Administration, tear down our economy, and abandon Main Street. If that is indeed this administration’s goal, Administrator Loeffler must answer to the millions of small businesses, workers, and families in Massachusetts and across the country that this administration is leaving behind.” ###
Doval Wants Giants Reunion to Extend Beyond This Season
After a whirlwind journey, Camilo Doval returns to the Bay Area determined to reclaim his command and anchor the San Francisco Giants’ bullpen next year.
Butler County mental health board eliminates finance department after audits find accounting discrepancies
As the Butler County Mental Health and Addiction Recovery Services Board seeks voter approval of a 1-mill, 10-year renewal levy, the board has voted to eliminate its entire finance department following the discovery of accounting discrepancies dating back more than three years.
OMNIBUS X, a toxic proposal for health and biodiversity. MEPs should not vote for it: ECVC
Omnibus X is a legislative package which, under the usual pretext of simplification to streamline the pesticide approval system, weakens the precautionary principle at the heart of European pesticide regulation.
I had a simple meal-prep idea. My company now makes millions.
David Rabie grew up in an Iranian immigrant family full of entrepreneurs. Their experience shaped his tolerance for risk as he built Tovala.
WELL Health Subsidiary WELLSTAR Announces Conditional Approval for TSXV Listing and Files Filing Statement
WELLSTAR has received conditional approval from the TSX Venture Exchange as a Tier 1 issuer, subject to satisfaction of the TSXV's customary listing conditions, and is expected to commence trading on or around October 1, 2026, under the ticker symbol "WSTR".Vancouver, British Columbia--(Newsfile Corp. - September 28, 2026) - WELL Health Technologies Corp. (TSX: WELL) (OTCQX: WHTCF) ("WELL"), a digital health company focused on positively impacting health outcomes by leveraging technology to...
Attorney General Rob Bonta defends settlement with Paramount as judge delays merger
A federal judge has delayed approval of the settlement in the Paramount-Warner merger case, following concerns raised by critics and New Jersey Sen. Cory Booker about its potential impact on competition, jobs, and media independence.
The GOP keeps caving to Trump, and science has found the surprising reason why
Republicans in Congress have bowed overwhelmingly to President Donald Trump, rarely challenging him and instead forfeiting their legislative prerogatives by allowing him to dictate their agenda. Even as the president's plummeting poll numbers put them at political risk for doing so, most Republicans...
Game 161: Rangers at Twins
First Pitch: 3:10 pm CDTTV: Twins.TVRadio: TIBN / WCCO 830 / The Wolf 102.9 FM / Audacy Last night, you got Joe Ryan and Jacob deGrom. This afternoon, you get Bailey Ober and Nathan Eovaldi. After another full season of Saturday previews, all I can tell you is that after last night’s veteran matchup resulted […]
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
River City Science Academy approved to open a seventh charter school at FSCJ’s Beach Blvd. campus
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UN Declaration On Pandemic Readiness Appears Headed For Approval In December
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NBAA Applauds Approval of Bills to Support Mental Health, Clarify Aerospace Medicine Guidelines and More
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Removal of 760,000 people from ACA marketplace could undermine US health system
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EU science policy wonks debate prospect of stronger ties with Canada
Europe’s research and innovation sector has started asking questions on how European Commission President Ursula von der Leyen’s offer to make Canada “the first associate member of the EU” would actually work in practice, and who will get to shape priorities in a transatlantic relationship that is getting stronger. The Commission says it wants “a new model of association” under which the EU and Canada will aim to develop “a shared space” to face ongoing challenges. “Working in close coordination with our member states and the European Parliament, we will aim to create a new form of partnership that has not existed until now, building the closest imaginable form of association with a partner outside Europe,” a spokesperson told Science|Business.Locked in an escalating trade war with US President Donald Trump, who has repeatedly talked of annexing Canada, Prime Minister Mark Carney has been looking east, but full EU membership was never in play. Taking the floor a day after von der Leyen’s proposal, he agreed to strengthen ties under “an alliance of the future” but reined in enthusiasm on the new label. He also suggested expanding Canada’s involvement in the Erasmus+ student mobility scheme, to which it currently has limited access, and the next iteration of Horizon Europe. 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Nutex Health (NUTX) Could Be 29% Undervalued As Nasdaq Texas Listing Nears
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Hochul leads Blakeman in polls, gets boost from Mamdani
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Trump call for supporters to cheat undermines fraud claims
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APSA Joint Statement on the National Science Foundation’s Graduate Research Fellowship Program -
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Why politicians should pay more attention to the polls (reprise)
Welcome to the 231st edition of The Week in Polls (TWIP), a polling newsletter that always welcomes new readers. So please don’t keep TWIP a secret; share it with your friends and colleagues: Share The Week in Polls With all the stories swirling around Reform, JL Partners and political polling, I am finally tearing myself away from talking about the regulation of polling this week - and instead re-running a previous piece reminding us why the solution to problems with polls isn’t simply to ban or ignore them. Rather, we need them to play a vital role in making our politics - and politicians - better. This is followed by summaries of the latest national voting intention polls, seat projections from MRPs and the most recent party leader ratings. Subscribers who pay for the full edition can also read ten insights from the latest polls and analyses, including: A trio of organisations and a pair of professors have been casting their eyes over the Liberal Democrats ahead of the party’s autumn conference; What impact did the summer heatwave have on views on climate change? and Which wins out between chocolate and cheese? If you are not yet a paid subscriber, you can read all ten by starting a free trial now: Get FREE 7-day trial For more polling news as it comes in ahead of next week’s edition, you can also follow The Week in Polls on Bluesky. Picking up on my doubt last week about whether or not 35% of British train travellers have tried to order a takeaway for delivery to a railway station or carriage, thank you to reader Iain, who has been in touch to say he has done just that… in India. Another quick pair of updates, this time on the controversies around Reform and polling. Politico has a further scoop - “Farage aide caught in donor sting attended Egypt retreat with JL Partners” - and Ian Dunt has written about the problems with polling too: “Seeing the response of many polling experts in the last few weeks suggests that they are nervous about what is happening and keen to mitigate against it. Seeing the response of journalists, which has been basically non-existent, suggests the precise opposite.” My usual reminder as well: please do hit reply if you’ve spotted a poll, focus group or new piece of poll-based research that you think should be in contention for coverage in a future edition. Thank you! And with that, on with the show. How politicians get public opinion wrong I have written before about the benefits that come from widespread availability of high-quality political polling. We need more polls and more good coverage of polls. However, what I’ve not dug into before is the research into how accurately politicians estimate public opinion on issues. Thankfully we have academic research to tell us. First, the bad news: We present results from a study of 866 politicians in four countries.1 Politicians were asked to estimate the percentage of public support for various policy proposals. Comparing more than 10,000 estimations with actual levels of public support, we conclude that politicians are quite inaccurate estimators of people’s preferences. They make large errors and even regularly misperceive what a majority of the voters wants. Politicians are hardly better at estimating public preferences than ordinary citizens. Walgrave, S., Jansen, A., Sevenans, J., Soontjens, K., Pilet, J.B., Brack, N., Varone, F., Helfer, L., Vliegenthart, R., van der Meer, T., Breunig, C., Bailer, S., Sheffer, L. & Loewen, P.J. (2023a), “Inaccurate Politicians: Elected Representatives’ Estimations of Public Opinion in Four Countries”, The Journal of Politics, 85(1): 209-222. The bad news is not quite as bad as that makes it sound because, when asked whether the majority of public opinion was for or against various policies, politicians picked the wrong option ‘only’ 29% of the time. However, this included getting it wrong even when public opinion is far from evenly split on an issue: They do not only get it wrong when the public is divided and hard to read (e.g., when there is a 51%:49% distribution). Seventy percent of the misplacements occur for policies with a relatively clear distribution of at least 60% (dis)agreeing citizens. Moreover, the public scored only slightly worse than politicians, picking the wrong option 2.7 out of 8 times on average, compared with 2.3 times for politicians. Turning to the other measure of accuracy (not which side is in the lead but what the percentage support is for each side), politicians on average were 18 percentage points out in their guesses. Again, this was only slightly better than the public, whose error came in at 21 percentage points.2 Further research, using the same mix of countries, gives a little more comfort about how (in)accurate perceptions are: We show that politicians have a better understanding of public opinion when they think the issue matters to voters. Further, when an issue is personally important to politicians they more accurately estimate their party supporters’ opinions. The results confirm that politicians hold more accurate perceptions of voters’ preferences when they think it is important to do so but not necessarily when the issues actually are important to voters. Butler, C., Walgrave, S., Soontjens, K. & Loewen, P.J. (2024), “Politicians are better at estimating public opinion when they think it is more salient”, Party Politics: 1–13. Even so, it’s not a good picture. The remedy for this? Politicians should spend more time reading the polls. So forward this newsletter to someone you know… Share For a more general argument against banning polls, see my 2024 piece. Is “Let Bartlet Be Bartlet” good advice or not? The latest episode of my Political Fictions podcast heads across the Atlantic for a dip into one of the political TV classics: Mark and Cory talk about a giant of American political drama for the first time this week, as they tackle The West Wing. They talk about Let Bartlet Be Bartlet, the nineteenth episode of series one. In it, Mark wonders if The West Wing is actually the epitome of the “Boris Johnson school of politics”, Cory outmanoeuvres Mark into confirming we will record a Christmas Special about Love, Actually and they debate whether the central message of this episode has been misunderstood. Cory’s email newsletter is Paperback Rioter and Mark has a family of email newsletters. Subscribe to our newsletter for some additional bonus content and to get alerted whenever a new episode comes out. Our theme tune is “Monkeys Spinning Monkeys” by Kevin MacLeod/incompetech.com and licensed under the Creative Commons: By Attribution 4.0 License. You can also listen to our episode on Apple Podcasts, Spotify, the web or YouTube. Elsewhere from me… [ A Lord's Eye View How to fix the problem of money in our politics Welcome to my latest update on work in the House of Lords. This time I am taking a look at how our political system is regulated, and the protections we need to keep democracy safe from becoming simply a contest to see who has the biggest bank account… Read more 5 days ago · 3 likes · 2 comments · Mark Pack ](https://lordseyeview.substack.com/p/how-to-fix-the-problem-of-money-in?utm_source=substack&utm_campaign=post_embed&utm_medium=web&embedding_publication_id=1269283) If you spot a factual error… Borrowing an idea from Stuart Ritchie and others, if you spot a factual error in an edition of this newsletter, I will give you a free 12-month subscription to the paid-for version (or an extra 12 months on your existing one). Factual errors qualify, but grammatical errors or disagreements over interpretation do not, and my decision is final. Messages about both of those are always welcome, though. Voting intention and leadership ratings Here are the latest voting intention polls from different pollsters. It is all pretty static at the moment, with a small and consistent Labour lead in nearly all the polls. The table is also online here, along with explanations about what is included. It is updated regularly throughout the week as new polls are released. Next are the seat projections from MRPs, also sorted by fieldwork dates, listing those which are based on dedicated fieldwork (rather than models based on averages of other polls). Because such MRPs are published infrequently, some of the entries below are quite old. Finally, here is a summary of leadership ratings, with a graph from PollCheck: Detailed numbers from the latest polls are online here, and both that and the graph are updated regularly throughout the week as new data comes out. For historical figures on both voting intention and leader approval stretching back to the 1930s, including Parliamentary by-election polls, see PollBase. Catch up on the previous two editions [ ](https://theweekinpolls.substack.com/p/a-crisis-point-for-political-polling) [ A crisis point for political polling Sep 13 ](https://theweekinpolls.substack.com/p/a-crisis-point-for-political-polling) [ Read full story ](https://theweekinpolls.substack.com/p/a-crisis-point-for-political-polling) [ ](https://theweekinpolls.substack.com/p/extra-questions-about-the-polls-in) [ Extra questions about the polls in Reform’s funding scandal Sep 6 ](https://theweekinpolls.substack.com/p/extra-questions-about-the-polls-in) [ Read full story ](https://theweekinpolls.substack.com/p/extra-questions-about-the-polls-in) My privacy policy and other legal information are available here. Links to purchase books or other items are usually affiliate links which pay a commission for each sale. Quotes from social media messages are occasionally lightly edited for punctuation and clarity. If you are subscribed to other email lists of mine, please note that unsubscribing from this one will not automatically remove you from the others. If you wish to be removed from all my lists, simply reply to this email to let me know. A quintet of Lib Dem polling analyses, and 9 other polling insights you shouldn’t miss The following ten findings from the most recent polls and analyses are only for subscribers who pay for the full edition, but you can sign up for a free trial to read them straight away. Ahead of the start of Liberal Democrat conference, we have a trio of organisations and a pair of professors with pieces out about Ed Davey’s party:
Inside the Fear, Anger, and Hope at Ed Sheeran’s Philadelphia Concert
The latest Loop tour stop drew heightened attention after a week’s worth of statements and fallout following Macklemore's removal from the tour
'I'm so, so sorry': Ed Sheeran speaks out at his first show after Macklemore controversy
Before performing in Philadelphia on Sept. 19, Ed Sheeran addressed the controversy surrounding Macklemore’s removal from the U.S. dates of his Loop Tour following pro-Palestinian remarks made onstage.
Poll: Most voters say Trump has hurt the economy as competitive midterm election looms
Trump’s approval and economic ratings point to a gloomy environment for the GOP, but the race for Congress is closer than in his first midterm, with the Democratic Party still unpopular.
Trump asked budget chief to draft order bringing health research funding under his control
The move came after the NIH director refused Trump’s request to cut Harvard grants in an Oval Office meeting.
EB-2 NIW Green Card Case Study: Approval for Business and Wellness Professional from Venezuela
Business Executive and Wellness Professional Colombo & Hurd secured an EB-2 National Interest Waiver (NIW) green card for a business and wellness professional from Venezuela focused on mental wellness education, early awareness, and prevention. USCIS approved the EB-2 NIW petition without a Request for Evidence, and after the Adjustment of Status (AOS) process, the client received her green card and is now a permanent resident of the United States.
Retire Your Old Towel Rack: The Modern Alternative From Amazon
The Wita semi-oval towel rack is shaped like a large horseshoe with a bottom bar. This metal towel holder features a minimalist design and comes in a pair.
Vought pushes for scrutiny of NIH grants in Oval Office clash
A heated debate took place in the Oval Office on Friday, with some Trump officials accusing the National Institutes of Health of funding grants that conflict with the president’s agenda.
Novant Health drives $4.33B in regional economic impact, study says
Novant Health Coastal Region generates an annual overall economic impact of $4.33 billion in the Wilmington Metropolitan Statistical Area (MSA), according to a new report. Commissioned by Novant Health and conducted by Mouhcine Guettabi, associate professor of economics at the University of North Carolina Wilmington and the area’s regional economist, the report evaluates population growth in New Hanover, Brunswick and Pender counties and whether the area’s healthcare infrastructure is positioned to meet the region’s demand. According to the study, while healthcare employment has kept pace with population growth in New Hanover and Pender counties, it has not kept up with the rapid population growth in Brunswick County, which is skewed toward an older population. “It points very clearly to Brunswick County being the bottleneck, or being the place where investment is most needed,” Guettabi said to the Business Journal Friday, “because the growth is the fastest, the composition of the growth is older (adults) and demand for healthcare is much higher for the subpopulation.” The Novant Health Coastal Region employs 8,295 full-time equivalent workers, according to the report, and is the region’s largest employer. Overall, through direct, indirect and induced impacts, the Novant Health Coastal Region supports 19,573 jobs, the report said. Using data collected from internal payroll, financial and capital reports, the report estimates that Novant Health Coastal Region pays approximately $1.15 billion in total compensation to its employees. According to the study, the provider’s annual operating expenditures, or direct economic impact, total $2.36 billion. That direct impact ripples through the regional economy through spending at its suppliers, or indirect impact, and household spending by staff and its suppliers’ workers, or induced impact. The report estimates the Novant Health Coastal Region’s indirect economic impact is $786 million, reflecting the multiplying effect of the provider’s operating expenses on expenditures like medical supplies, facilities, food, IT and professional services. Because 86.9% of Novant Health Coastal Region employees live within the tri-county region, the report estimates that wages paid by Novant circulate into the regional economy, creating an induced economic impact of $1.17 billion. “That money just doesn’t go into thin air,” Guettabi said of the wages paid to Novant Health Coastal Region employees. “Some of that money is being re-spent, and therefore it’s supporting grocery stores, hiring, restaurants and bars, and there are a lot of other companies or organizations whose employment, whose activity partially depends on that.” The combination of direct ($2.36 billion), indirect ($786 million), and induced ($1.17 billion) impacts totals an estimated $4.33 billion, according to the report. A study commissioned by Novant Health in 2024 and conducted by FTI Consulting’s Center for Healthcare Economics and Policy found that Novant Health generated nearly $2 billion of direct impact, with $628 million in indirect impact and $857 million in induced impact. Healthcare investments in the pipeline for Brunswick County Additionally, the study found that while healthcare employment has kept pace with population growth in New Hanover and Pender counties, it lags in Brunswick County. “Once you go below the metro level and you decompose the three counties that make up the Wilmington Metro,” Guettabi said, “it becomes fairly clear that Brunswick is the standout. And not only that, but clearly the growth there is fully domestic migration and largely retiree-driven migrants.” Using data from the Centers for Medicare and Medicaid Services on per-capita healthcare spending among age groups, Guettabi estimates that adults aged 65 and older demand 2.44 times the healthcare of working-age adults. “The share of the population in Brunswick County that’s over the age of 65 is 33%,” Guettabi said, “which is so much higher than the average share of people over the age of 65 within the state or within the country.” The report emphasizes that Brunswick County is the “strongest candidate” for new healthcare investment, adding that patient discharge records show Brunswick residents rely heavily on facilities in New Hanover County for inpatient care. “Investments in Brunswick County would not only meet the demand for those residents, but it would also relieve pressure for New Hanover County residents,” Guettabi said. Laurie Whalin, president of the Novant Health Coastal Region, told the Business Journal Friday that the provider plans to expand services at Novant Health Brunswick Medical Center, in addition to other investments in the area. In April, the state granted conditional approval to both Novant Health and Columbus Regional Healthcare System to build new hospitals, just miles apart, on either side of the Columbus County and Brunswick County borders. Columbus Regional’s $214 million 30-bed hospital would be located at the former Acme-Delco Middle School in Delco, according to the application. The project’s approved timetable has construction slated to finish in May 2029, with the hospital open for service by October 2029. The Whiteville-based provider, which Atrium Health manages, broke ground on an Advanced Care facility in December 2025 and operates four specialty clinics in Leland. Meanwhile, Novant Health’s proposed $251 million 20-bed hospital would be built just miles from Columbus Regional’s proposed hospital, near the Compass Pointe community in Leland. The provider estimates the hospital will open by 2030. State officials also approved Novant Health in March to build a freestanding emergency department in Carolina Shores, near U.S. 17. The project is estimated to cost $24 million, according to the application, and will operate under the Novant Health Brunswick Medical Center license. Additionally, Novant Health’s 16,000-square-foot ambulatory surgery center is slated to open in Leland by year’s end, officials said.
Spanberger bans by-right approvals, NDAs for data centers
Gov. Abigail Spanberger unveiled a data center accountability plan and and an executive order that includes creating an AI task force.
Updated downtown Greenville design guidelines approved: Design Review Board notes
The board recommended approval of the city’s updated downtown design guidelines to Greenville City Council.