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Highmark Foundation and Buffalo Bills Foundation Unveil “Victory Table” to Expand Access to Healthy Food and Wellness Resources Across Western New York
New mobile initiative will bring free healthy meals, nutrition education and community health support directly to neighborhoods in nee
New behavioral health crisis care and stabilization unit opens in Cleveland
Urgent behavioral health support at The Glick Recovery Campus in Cleveland’s Central Neighborhood opened Monday at 2322 E. 22nd St. See details on services offered below:
Sutter Opens New Urgent Care in San Francisco's Mission Bay
New clinic brings same-day care to one of San Francisco’s fastest-growing neighborhoods SAN FRANCISCO – Residents, workers and visitors in Mission Bay now have a new option for same-day medical care with the opening of Sutter Health’s newest urgent care clinic near Oracle Park. Located at 240 King St., the 2,156-square-foot clinic has four exam […]
Man shot, killed inside Hyde Park business identified
Boston police have identified a man who was shot and killed inside a business in the city's Hyde Park neighborhood.
School of Medicine and Public Health receives grant to investigate links between Alzheimer’s environmental exposures
The Neighborhoods Study from the Center for Health Disparities Research at the University of Wisconsin School of Medicine and Public Health has received funding from the National Institutes of Health on an upcoming nationwide project, according to director of Center for Health Disparities and Associate Dean for Social Health Sciences and Programs, Dr. Amy Kind in...
How Israel’s regional neighbors see its upcoming elections
Israeli Prime Minister Benjamin Netanyahu’s right-wing bloc is squaring off against that of his main opponent, centrist Gadi Eisenkot.
Parent uses humility, service to bring families together at Harmony Science Academy-Euless
Saadia Hassan, the 2026 parent of the year, helped rebuild the PTO and rally neighbors to raise $1,500 for a family displaced by fire.
CID leaders, business owners say public safety must be addressed to help regain footing
As the Chinatown International District (CID) held it's annual Night Market, bringing in thousands throughout the day to the heart of the neighborhood -- busine
VOICE OF BUSINESS: Dayton area businesses have a big stake in election
Dayton area businesses invest capital, time, talent, reputation, and passion in building companies and creating jobs that employ our families, neighbors, and friends. The decisions made by elected officials at the local, state, and federal levels can shape the environment in which our businesses operate, grow and compete. For business leaders, civic engagement is an important part of protecting those investments and helping shape the future of the Dayton region.
Mental health & safety concerns brought up by neighbors after shooting by bar downtown
Local health experts to go door to door and survey Birmingham area
Jefferson County Health experts will visit certain neighborhoods to get health perspectives
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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When ENJOY, An Urban General Store (ENJOY) owner and president Rebecca Wood moved to Chicago in 2002, she lived near Lincoln Square and spent lots of time exploring the small businesses on Lincoln Ave. “The 4700 block fascinated me…and the neighborhood felt like a village inside this big city I was still getting to know,” said Wood. […]
For Your Health
Dementia touches many lives — in many different ways. And most of us likely have some firsthand experience with it, whether it’s with an aging family member or friend or neighbor. …
Valley organizations team up to provide hot food, health care
A Phoenix-based outreach organization is partnering with a mobile medical clinic to bring health services directly to neighborhoods across the city, including HIV testing and health education.
Valley organizations team up to provide hot food, health care
A Phoenix-based outreach organization is partnering with a mobile medical clinic to bring health services directly to neighborhoods across the city, including HIV testing and health education.
Bristol, Blue Star ‘breakup’ has Ivywild hallways abuzz
Bristol Brewing Co. and Blue Star restaurant marked the beginning of a beautiful business partnership almost 30 years ago, inside neighboring operations, in co-owned property near the intersection of South Tejon Street and East Ramona Avenue. When the historic former Ivywild elementary building went on the market just blocks away at 1604 S. Cascade Ave., […]
Q&A: Detroit retail leader on attracting businesses, retail growth
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Phoenix groups team up to bring health care, hot meals to those in need
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Tribes hit hard by wildfires face health effects, cultural losses
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Campaign to combine health care advocacy with civic engagement and voting comes to Philadelphia’s Point Breeze neighborhood
Young people face health care decisions shaped by policy. Vot-ER is working to connect health care experiences with civic engagement and voting.
He Was Known As A Simple Man In The Neighborhood, But Behind His Doors Lay Thousands Of Remains And Ledgers Of Names
For decades, Andrés Mendoza was regarded as a quiet, helpful neighbor. Beneath his home, investigators found thousands of bone fragments and ledgers documenting a homicide spree of dozens of women.
Campobasso puts neighbors before politics
Dear Editor, In today’s world, it seems easier than ever to divide ourselves by politics, opinions and differences. What I appreciate most about John Campobasso is that he refuses to see people through...
Tenderloin Buzz: Small businesses galore!
Coming up in the Tenderloin: two new businesses to visit and weekly neighborhood events.
Louisiana business applications fall, but less sharply than in neighboring states
Louisiana saw a smaller drop in new business applications in August than the nation as a whole and each of its neighboring states, new data shows. Louisiana recorded 6,793 seasonally adjusted busin… Already an INSIDER? Sign in. Already an INSIDER? Sign in
Column: The cruel politics that pit struggling Americans against each other
Whether it’s race, geography, neighborhood … it doesn’t really matter what divides, so long as the poor lack compassion for one another.
Science and technology help Florida golf courses be good neighbors
Before the first golfer tees off each morning at Interlachen Country Club in Winter Park, superintendent Bryce Gibson is already walking the fairways, listening to birdsong, scouting dry spots and preparing 110 acres of maintained turf for the day ahead.
In Your Neighborhood: Dennis House emcees Hartford Business Journal 40 Under 40 awards
PLANTSVILLE, Conn. (WTNH) — News 8 is in your neighborhood in Plantsville at the Aqua Turf for the 30th annual Hartford Business Journal’s 40 Under 40 celebration. The event honors movers and shake…
Birmingham business owners raise concerns over planned Oasis homeless respite center
A center designed to help people experiencing homelessness is planned for Birmingham’s Smithfield area, but some nearby business owners are concerned about how the project could affect the neighborhood.
Business Ins & Outs: Bizzeria, UNIQLO and More Georgetown Openings
Discover the latest Georgetown business openings, including Bizzeria, UNIQLO, and other new restaurants, shops and businesses coming to the neighborhood.
New funding boosts data archive that tracks healthy aging environments
With an $11 million award from the National Institute on Aging, University of Michigan researchers will build and share national data that track how neighborhood conditions change over time, helping scientists study how local environments affect older adults' health.
MDI Health Celebrates Community at 2026 Annual Meeting
BAR HARBOR—MDI Health celebrated the people and partnerships strengthening local healthcare during its 2026 Annual Meeting and Community Celebration, held September 15 at the Bar Harbor Club. The gathering brought together patients, medical staff, employees, trustees, volunteers, supporters, and community partners to recognize the year’s accomplishments and honor those whose contributions make a meaningful difference across the organization and the communities it serves. “This celebration is an opportunity to recognize the extraordinary people who make our work possible,” said Chrissi Maguire, president and CEO of MDI Health. “Their compassion, dedication, and belief in strong local healthcare can be felt throughout our hospital, health centers, Birch Bay Village, and the communities we serve.” During the celebration, MDI Health presented its 2026 Impact Award to Mount Desert Nursing Association (MDNA), recognizing the organization as Community Partner of the Year for providing compassionate, skilled in-home nursing care across Mount Desert Island, Trenton, and Lamoine. “MDNA extends care beyond our walls, helping people remain safely at home, surrounded by the people and places they know and love,” Maguire said. “Its work lies at the intersection of healthcare and community and strengthens our entire healthcare system.” “For 77 years, MDNA has helped our neighbors recover and remain safely at home,” said Amy McVety, MDNA Executive Director. “Our longstanding partnership with MDI Health helps ensure a seamless transition from hospital to home and the continued care patients need. We are grateful for this recognition and especially proud of our talented, hardworking team.” The evening marked a transition in Board leadership. Martha Wagner, PhD, was recognized as she concluded her term as chair of the MDI Health Board of Trustees. Madeleine Braun, PhD, MBA, was introduced as incoming chair. “It is an honor to build on Martha’s leadership and serve an organization so deeply connected to this community,” Braun said. Individual honorees recognized during the evening’s program included Nancy D’Agostino, MDI Health Volunteer of the Year; George Rossi, Birch Bay Village Volunteer of the Year; Marc Woolfolk, Birch Bay Village Employee of the Year; and Beth Applebee, MDI Hospital Employee of the Year. “These honorees represent the very best of who we are,” Maguire said. The program also highlighted new initiatives and honors from the past year. MDI Health launched a free Screening Mammogram Scholarship Program to remove financial barriers to early detection, supported by a generous grant from the Maine Cancer Foundation. An in-hospital food pantry has been opened to meet rising community need and address the link between nutrition and health. MDI Health earned CMS five-star ratings for Patient Experience and Nurse Communication, top marks in the 2026–2027 Lown Institute Hospitals Index, recognition from the American Hospital Association and American Heart Association, and a third consecutive Best Places to Work in Maine designation. The hospital will open its new Main Entrance this fall, as work advances on the expanded Emergency Department and other patient-care spaces. The Building Our Future Campaign has raised more than $56 million in capital and programmatic support to date. “Everything we have accomplished reflects the strength of this community,” Maguire said. “We are grateful to everyone who has contributed their time, talent, leadership, and support to help MDI Health continue meeting the evolving needs of the region.” Subscribe Share Leave a comment
Protect Your Home and Business this National Preparedness Month with Rainbow Restoration®
The U.S. experienced 12 separate billion-dollar weather and climate disasters during the first half of 2026 alone, causing at least $31.9 billion in damage, according to Climate Central's mid-year update. As September marks National Preparedness Month and the transition to cooler weather brings the potential for severe storms, tornadoes, flooding and early winter weather, Rainbow Restoration®, a Neighborly® company with more than 45 years of restoration experience, is encouraging homeowners and
OnMed, Jackson Health System and The Salvation Army Deploy OnMed CareStation™ to Extend Care Beyond Hospital Walls in Miami
WHITE PLAINS, N.Y., September 17, 2026--OnMed, the leader in hybrid healthcare expanding access to care through the CareStation, today announced a new partnership with Jackson Health System, Miami’s only public health system, and The Salvation Army to bring essential medical care closer to home in Miami's Allapattah neighborhood. Sponsored by Jackson, the CareStation will be deployed at The Salvation Army's Miami location at 1907 NW 38th St., providing residents with convenient access to license
Dennis rejects hearing on Foley's as neighbors demand action
Dennis Licensing Board decides against holding a public hearing when faced with neighborhood complaints of noise and nuisance at Backyard by Foley's.
Television Q&A: Can my grandkids still visit 'Mister Rogers’ Neighborhood'?
You have questions. I have some answers. Q: I would love it if my toddler grandchildren could watch reruns of “Mister Rogers’ Neighborhood,” but I can’t find them anywhere. The
Business owner criticizes new Euclid Avenue closure timing ahead of Keeneland
A paving project on Euclid Avenue in Lexington’s Chevy Chase neighborhood has a new timeline, and a local business owner is raising concerns about the timing.
Bridgeport residents urge state stadium authority to oppose proposed Amtrak facility near Rate Field
Bridgeport residents are raising concerns that their neighborhood could lose the White Sox while gaining a proposed $900 million Amtrak maintenance facility near Rate Field.
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A healthy, green lawn can be the envy of any neighborhood, but how does someone cultivate a yard like that? Assistant Professor of Ecosystem Science Amber Churchill has been getting her hands dirty and ...
Dear Abby | Mom doesn't want daughter visiting neighbors
Dear Abby: My next-door neighbors are appropriately friendly, mow their lawn and generally mind their own business. The husband is a leader in a fundamentalist church whose pastor preaches that
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CaroMont Health plans new hospital near Lake Wylie as York County grows
CaroMont Health plans to build a neighborhood hospital in Clover, South Carolina by 2031 to serve the Lake Wylie and York County region.
CaroMont Health plans new hospital near Lake Wylie as York County grows
CaroMont Health plans to build a neighborhood hospital in Clover, South Carolina by 2031 to serve the Lake Wylie and York County region.
The Case for—and Against—Working Out in a Weighted Vest
From ancient Spartan hills to neighborhood walks, carrying extra weight is fitness's favorite trend. Here is what a physical therapist—and a military veteran—say about the actual benefits and overhyped claims.
Griffin Museum of Science and Industry to redevelop historic main entrance with new Welcome Hall
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Living in disadvantaged neighborhoods linked to adverse brain health
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Detroit nonprofits team up to create family services hubs
Starfish Family Services and Brilliant Detroit set up shop next door to each other to build a pipeline of services in Detroit neighborhoods.
NoMa neighborhood transforms for annual mural festival: NoMa in Color
Seventeen artists will paint 16 new murals in NoMa from September 11-18, raising the neighborhood's total to 75 large-scale works.
Meet our new faculty: Jana Hirsch
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House in secluded neighborhood tops sales report at $1M
Here’s a look at the top 10 home sales for the week of Aug. 24 in Minnehaha and Lincoln counties.
Southern Delaware hospitals oppose ChristianaCare’s proposed campuses, arguing they don’t meet state requirements
If approved, the two “neighborhood hospitals” proposed for Camden and Georgetown would open in 2028. Other hospital systems question if they actually comply with state law.
Baltimore proposes new Department of Neighborhood Safety to handle some nonviolent 911 calls
Baltimore leaders are proposing a new Department of Neighborhood Safety that would send trained responders to certain nonviolent 911 calls instead of police officers.
Truth #3: Protecting Small Businesses and Elderly Neighbors
“In moments of crisis, people appreciate you just asking them how you are doing. As someone who has suffered from PTSD [post-traumatic stress disorder], it is important to have moments of humor, cracking a joke, simply talking to somebody that you knew for years. Just doing those things can really
Why Cleveland sends Steelyard TIF grants to businesses in six other neighborhoods
Cleveland’s Steelyard TIF program directs 30% of the fund to commercial districts identified through a retail-impact study, allowing businesses in six neighborhoods outside the shopping center to qualify for grants.
He turned a childhood lawn-mowing gig into a $4.5 million business
Cody Kuebler began by cutting his neighbors' grass for about $25 a lawn. Now, at 25 years old, he oversees a $4.5 million landscaping business.
Businesses are eyeing Germantown opportunities. The neighborhood is proceeding with caution.
The area has a new visitors center and it has welcomed coffee shops and a food co-op. Residents would like restaurants and more retail.
Back up science by adding service for people in need
Residents of Houston’s Fifth Ward live adjacent to documented creosote contamination. The neighborhood is 94 percent non-Hispanic Black. It is a state-designated cancer cluster. Those who live there do not
Neighbors say dead dogs dumped in Atlanta neighborhood, raising health and safety concerns
Home security was able to capture the car accused of dumping the dogs, but not the license plate.
Seattle business leaders show how to stand up for their city
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How Jason Priestley processed the sudden death of “90210 ”costar Luke Perry
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'Hoped to die here': Elon Musk's growing Bastrop County empire yields bittersweet feeling for neighbors
Longtime Bastrop County residents face industrial expansion and environmental concerns as Elon Musk’s business empire acquires thousands of acres of land.
Southern Heritage Classic Parade brings music and fun through Orange Mound
See our best photos from the Southern Heritage Classic Parade through the Orange Mound neighborhood ahead of the SHC at Simmons Bank Liberty Stadium.
A rare “boomerang” earthquake shocks scientists with its bizarre U-turn in Burma - Futura-Sciences
A March Morning That Changed Everything On March 28, 2025, a violent earthquake struck Myanmar (formerly Burma) with an estimated magnitude between 7.7 and 7.9. The epicenter was close to Mandalay, the country’s second-largest city. The quake’s power rippled far—so much so that tremors were even felt in neighboring Thailand,...
How L.L.Bean is navigating the U.S.-Canada trade war
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Business creating unique crochet figures
LEWIS CENTER — Take a quick walk over to The Market at Evans Farm on any Saturday between 9 a.m. and noon, and you’re bound to see a shop which will have you hooked-literally. HooksandChains35, a small business based out of Upper Arlington, is one occupant of the cheery neighborhood market, and it puts a unique spin on cozy crochet items.
The politics and possibilities of ‘AI could kill us all’
I found myself fielding a lot of questions from folks who don’t usually talk much about AI this week. They were mostly along the lines of “do you think AI is going to kill us all?” or “how worried should I be about this human extinction stuff?” Motivating this wave of existential anxiety was the highly dramatic resignation of now-former Anthropic employee Jacob Coxon, who quit his job while publicly sharing his concerns about safety practices at the leading AI companies. More specifically, he declared that almost everyone at OpenAI and Anthropic, the leading AI labs, believes that there’s a decent chance the AI systems they’re producing could “kill us all” by the end of the decade, and the companies aren’t “acting responsibly.” Other AI safety researchers, including those still employed at Anthropic and OpenAI, all confirmed that yes, Coxon is correct, they’re all worried that their company’s products might prove fatal for the entire human race as well. Two more AI employees quit and joined the chorus. Now, the warning shot has been covered everywhere from the Wall Street Journal to Fox News to WIRED to the Guardian. I understand why all this sounds scary, but my response to those who have asked, has generally been: No, you don’t need to worry that AI will kill go rogue and kill us all. But that does not mean we shouldn’t worry, period. Far from it. The companies building AI products are now among the wealthiest and most powerful entities in the world. And they very much are building enormous engines of mass surveillance, extraction, and automation. They can and have allowed their AI systems to carry out felony hacks of other companies, provided the government with autonomously generated kill lists, and sold enterprise technology to firms around the world that is explicitly intended to replace jobs. But “AI” has done these things not because they have all-powerful minds of their own but, ultimately, because people have programmed, calibrated, and directed them to. In other words, it’s not AI we need to worry the most about. It’s the people and corporations working to profit from and gain power by deploying it. The technology is sophisticated, sure, and, especially in cybersecurity contexts, potentially disruptive to plenty of existing systems. But if we want to stop this predatory, profiteering, and extractive form of AI—and it’s worth noting that at this point, most people do—we absolutely can. A quick note/plea: I can only do all of this with the support of readers like you, so if you find value in independent, critical tech journalism and analysis, please consider becoming a paid subscriber. I want to keep as much of this un-paywalled as absolutely possible, and I need your support to do so. Many thanks to all who continue to chip in, it’s very much appreciated. Onward. Subscribe First, some context: AI industry folks like Coxon have been discussing the prospect that AI will destroy humanity for years. Even before the beginning of the AI boom, many working in the industry, from the executive staff to the rank and file researchers, have obsessed over ‘x-risk’, or the possibility that AI will become sentient or semi-sentient and move one way or another to exterminate humanity. This is ostensibly why Elon Musk bankrolled OpenAI in the first place, and is the grounds for his lawsuit alleging OpenAI betrayed its charter by abandoning its nonprofit status to become a commercial enterprise. Many AI engineers and startup founders have calculated their own personal p(doom), or the probability that the tech product they are working on will initiate an actual humanity-extinguishing apocalypse. 10-25% p(doom)s are pretty common. (I wrote about a long weekend I spent among these folks at one of their top conferences here, to give you an idea of their ideas and belief systems.) Sam Altman himself drove the narrative of the imminent rise of a super-powerful AI, or artificial general intelligence, to prominence by declaring that the technology he was building posed an existential risk to humanity. This idea is in other words baked into the DNA of modern AI companies and into the products they engineer. It’s also why the industry is routinely accused, by myself and others, of “doom marketing,” ie, using such proclamations and framings to impart the sheer power of the technology behind your product onto investors, partners, consumers, and the state. Some ambient understanding of this tendency may have helped prevent the press from repeating the claim every time one of the x-risk folks made it over the years, including when they quit their jobs at AI companies while doing so. Yet Coxon’s AI x-risk alarm has broken containment, as they say, and has exposed the idea to the mainstream media once again. This has happened, I think, for a number of reasons. First, when AI CEOs were going around saying AI might kill everyone in 2023, their companies were well-capitalized, but not nearly to the extent they are today. They were more easily dismissed as eccentric geeks of the sort that Silicon Valley is supposed to produce. Now, not only do their products have much greater market saturation, but people are more aware of a) the often unethical ways the executives and companies comport themselves b) the other adverse impacts of AI that have already arrived, and c) the physical cost of building these systems, particularly when it comes to data centers. Finally, toss in the constant stream of headlines in 2026 about AI models going rogue or potentially upending the world’s infrastructure. [ ](https://www.bloodinthemachine.com/p/with-the-backlash-to-data-centers) [ With the backlash to data centers, Flock and AI glasses, a mass opposition to big tech is underway. Silicon Valley is in denial. ](https://www.bloodinthemachine.com/p/with-the-backlash-to-data-centers) Brian Merchant · Aug 27 [ Read full story ](https://www.bloodinthemachine.com/p/with-the-backlash-to-data-centers) As a result, general sentiment was already overwhelmingly skeptical of AI and its overlords, so the table was pretty well set for someone to come along and say ‘just a reminder, the companies that are building the product that promises to take your job and leave a data center in your neighborhood also think that it might exterminate the human race’ and get a strong reaction from the media and the public. The question is: Should we understand this stuff as hype, strategically fanned to feed already swelling valuations? Is it doom marketing? Genuine cause for alarm that the infrastructure that undergirds modern life is facing a novel threat vector? Or reason to be sincerely worried that AI companies are amassing too much power, and that their products are genuinely dangerous? The answer, I’m afraid, is “yes.” Let me try to untangle all of this a bit, because arguments over how to navigate this moment are extremely heated right now, as they are essentially arguments over how to approach the politics of AI at a moment where there may be a unique opening for action. Those sympathetic to AI alignment concerns and x risk arguments—which increasingly includes a faction on the left who want to shut down AI over safety concerns—argue that people who dismiss AI as all hype have their heads in the sand. Meanwhile, critics of the x-risk narrative—which I might note includes a cadre of investors and tech folks on the right, too—argue that it is hype and can be used to further inflate valuations or for pursuing regulatory capture. The challenge is that many feel that dismissing AI as just hype or purely marketing also diminishes the urgency of taking on the AI industry as the novel and threat to labor, civil society, and the public sphere it is; others that by accepting the industry’s own terms, we imbue it with undue power and enable it. But let’s be clear: Declarations that AI is so powerful it might end the world are a kind of marketing, and anyone who says otherwise is just as off base as those who say that’s all that it is. If you don’t think that these sub-trillion dollar companies have higher-ups who noticed that when their founders talked about super-powerful dangerous AI they got spikes in media interest and phone calls from investors, or that those founders didn’t notice that themselves, and lean into certain narratives to advantage their products, then I don’t know what to tell you. Not all marketing is a Pepsi ad campaign with a celebrity spokesperson. Yet confronting the AI industry should certainly be considered an urgent project. Do I share the x-riskers’ fear that out-of-control, super-intelligent AI agents might end the world? I do not. I’ve read a good deal of AI extinction literature over the last couple of years and I have not come across a credible, step-by-step documentation of how exactly AI might move from self-recursively improving AI to killing every single human on the planet. Most of what I’ve read seems predicated on a sort of reverse Ian Malcolmian logic: Eventually, it becomes smart enough and AI, uh, finds a way (to exterminate humanity). Are the AI companies also overstating and dramatizing what their products can do? Yes, pretty much all the time. They’re in a knife fight for market share and are trying to win customers and government contracts before their investors come knocking. And yet. They have concentrated enormous amounts of compute, have extensive data collection and surveillance capacities, have inserted themselves into the state in numerous capacities, including military kill chains, and they are being run by egomaniacal billionaires who are rushing to monopolize an entire new market. The way I think about their most recent frightening-seeming exploits is not as a “swarm of rogue AI agents building a new civilization” or whatever, but as corporations with a hitherto-unimaginable amount of compute at their disposal recklessly experimenting with automation programs, completely unafraid of any repercussions because we have been unwilling or unable to impose any on them. So I think we should welcome any newfound imperative to hold them accountable. I also think that ultimately, the AI critics, Pause AI folks, leftists, doomers, effective altruists, and, honestly, most of the public, want a lot of the same things: legitimate checks and limits on AI companies’ power, actual transparency into what the companies are doing, and for more of AI to be under public control. (Ultimately, a lot of what animates the x-risk fears are rooted in just that: a fear of losing control.) How we move towards all this, exactly, is the question of the day, and while there’s much to be argued over in terms of building a viable political platform to challenge the AI industry’s power, I do want to cast a vote against one particular approach. Not to pick on Chris here, as there are a lot of folks out there proposing stuff like this, and the policy ideas actually stem from AI safety groups. But not only would this be challenging to land politically (I can already hear the ‘China will beat us to AGI’ calls) and all but unworkable in practice, this approach is a) far too limiting, b) fails to address the current harms caused by AI and c) would likely only wind up serving Anthropic and OpenAI; it’s what regulatory capture looks like in action. Full model transparency is the floor for what should be on offer here. If these companies believe their products will kill us, the very least we deserve is to know how. It’s in the public interest. I would also argue we might get a lot of the way to stopping any currently envisioned robot apocalypse simply by forcing AI companies to assume liability, and to submit to the full brunt of the law. If Sam Altman were liable to be charged with a felony for approving the hack on Hugging Face1, if Google was forced to pay defamation fines each time it published a false and injurious AI Overviews, these companies might suddenly find cause to restrain their models’ output, and we might hear less about rogue AI. We would need to introduce new frameworks and available tools for tracking automated lawbreaking, to be sure, but I’d wager that little would frighten the AI companies more than actually being held accountable for what their products enable. To that end, Illinois has passed an AI liability law, which the industry fought tooth and nail, and Florida is considering one. The next steps would be towards moving AI under public control; again, it’s only reasonable, since everyone, not just AI insiders, should get a say over how a technology whose developers say might kill us is developed and deployed. Dismantling the whole industrial project as currently structured should be on the table, too, pending democratic input. But that’s for another post. For now, suffice to say that while I won’t be losing any sleep about an AI-enabled extinction event, Mr. Coxon and co. have given us an opportunity to underscore the urgency of the clear and present damage AI companies are doing, the extreme power they wield and the extent to which they hold themselves unaccountable, and the abundance of political capital there is out there for taking them on. Subscribe 1 Purely speculative! I do not know if he did or not.
Lakewood opens first neighborhood bikeways
For many cyclists, it can be difficult to find a safe, comfortable path on the streets — especially on streets that are frequently traveled by cars. However, the City of
Residential air pollution linked to higher depression scores among 9/11 responders: Study
9/11 first responders' exposure to air pollution and extreme heat in the neighborhoods they live in compounded poor health outcomes, a new study finds.
Putting People Before Politics In The 107th District
To The Editor: I'm writing to introduce myself to the neighbors I hope to represent and to explain why I’m running for State Representative in the 107th District of Newtown. I've called the 107th di...
Neighborhood environments impact long-term health of 9/11 responders
Twenty-five years after the September 11 terrorist attacks, researchers at the Icahn School of Medicine at Mount Sinai have found that environmental conditions where World Trade Center responders live may influence their long-term physical and mental health.
An uplifting season - Illinois Times, the capital city's weekly source of news, politics, arts, entertainment, culture
I’ll be the first to admit, I’m not much of a sports fan. The idea of the Women’s Professional Baseball League playing its inaugural season in Springfield was interesting as a historical happening. But it was not until Lucky Horseshoes Chief Storyteller Jamie Toole spoke at our neighborhood association meeting that I committed to going […]
Jordan's water crisis amid growing tensions with Israel
Jordan is already one of the world's most water-scarce countries. Now, an additional water deal with Israel has lapsed, highlighting Jordan's dependence on its neighbor as political tensions rise.
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Celebrate the start of locals summer with an array of fun festivities. Visit your friends and neighbors at Good Old Days in Somers Point, set sail with