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Pixel Weather gets a fresh look and a handy new forecast detail with the latest update
Google is rolling out the new Pixel Weather icon to older Pixel phones, alongside a forecast timestamp and the new Weather Brief name.
Curiosity Blog, Sols 4975-4981: Happy 14th Landing Anniversary
By Susanne P. Schwenzer, Professor of Planetary Mineralogy at The Open University, UK
Globalinx to purchase Virginia Beach land for colocation data center
The Virginia Beach Development Authority on Tuesday agreed to sell 9 acres of land in Corporate Landing Business Park to Globalinx.
Harrison business cleaning up after being hit hard by flooding
Jake's River Landing is still closed, but crews worked all day Saturday to move everything back into place.
Home-Field Advantage: Why the World’s Biggest Sporting Events Are Coming to the US
The United States is on a streak landing more international events than ever. What’s driving the good fortune for sports fans living in the country?
Raleigh staple Adventure Landing abruptly shuts its doors after 38 years
Known for laser tag and go-kart racing, this business will permanently close its doors after decades on Capital Boulevard.
Section IV Football Media Day ushers in new season
ELMIRA, N.Y. (WETM) – High School football is back and primed for the new season. Wednesday morning, teams from all over Section IV converged for a special media day opportunity at The Links at Hiawatha Landing golf course in Apalachin. The theme was simple, be better this year than the last for players, teams and […]
49ers Called ‘Top Landing Spot’ for Benched 1st-Round QB
Bleacher Report's Alex Kay called the San Francisco 49ers the "Top Landing Spot" for benched Vikings quarterback J.J. McCarthy. The post 49ers Called ‘Top Landing Spot’ for Benched 1st-Round QB appeared first on HEAVY.
49ers Called ‘Top Landing Spot’ for Benched 1st-Round QB
Bleacher Report's Alex Kay called the San Francisco 49ers the "Top Landing Spot" for benched Vikings quarterback J.J. McCarthy. The post 49ers Called ‘Top Landing Spot’ for Benched 1st-Round QB appeared first on HEAVY.
Archer Aviation Exec Says Boeing Deal Will ‘Significantly Change the Profile’ as $200 Million Insitu Business Joins Portfolio
Archer Aviation Inc.‘s (NYSE:ACHR) deal with Boeing Co. (NYSE:BA) could significantly reshape the electric vertical take-off and landing (eVTOL) company. Insitu’s $200 Million Revenue Business During the company’s second-quarter earnings call on Monday, Archer’s Chief Financial Officer Priya Gupta hailed the company’s acquisition of unmanned aircraft systems manufacturer Insitu, as well as autonomous eVTOL maker Wisk Aero and SkyGrid in an all-stock deal. Read Also: Rocket Lab USA, Hims & Hers,
7 Best Tech Gadgets of August 2026
August arrives with a lineup that feels genuinely considered. Not every gadget this month is chasing a headline spec or fighting for shelf space. Some of the most interesting things landing right now are smaller, quieter, and more honest about what they actually do — a folding mouse that disappears into a shirt pocket, a
Michigan company making robots now 1 of many landing defense contracts
Pratt Miller is just one company, in addition to Ford and General Motors, working to gain more business tied to the defense sector.
Clearwater advances talks on $180 million sports complex
The council’s 3-0 vote on the proposal from Sunshine Recreational and Entertainment LLC is not a final approval for the project.
Clearwater moves $180M sports complex plan forward despite neighborhood concerns
A proposal to replace The Landings Golf Course with a massive sports and entertainment complex is moving forward after a unanimous vote from Clearwater City Council.
Entertainment: Eat Your Way Through The State Fair
But don't miss the moon landing in the Historic Third Ward.
11-year-old taken into custody after stabbing at St. Cloud business
Police say an 11-year-old boy stabbed an 18-year-old man at a St. Cloud business on Tuesday, landing him in the hospital.
Brewers among most likely landing spots for Clay Holmes
While other teams are interested, the Brewers are heavily pursuing Holmes, who is expected to be moved by the Deadline.
Developer Eyes Clearwater Golf Course for $180M Sports Complex
Developer proposes replacing Clearwater's municipal golf course with a $180 million sports and entertainment complex.
Yankees Are Reportedly Trading For Nationals 1B Luis Garcia Jr.
The Yankees made a trade on Sunday afternoon, landing Washington Nationals first baseman Luis García Jr.
Patriots Named Trade Landing Spot for Buccaneers Star Vita Vea
Vita Vea on the New England Patriots would be lethal.
Ancient Chinese cosmology comes alive in Jackson Park
Audience members cooled themselves with handmade fans as Amanda Maraist danced through the sultry air among the stainless steel lotus petals of Yoko Ono's “Sky Landing” sculpture in Jackson Park
Aipac’s brand has become toxic. Can its ‘pro-Israel, pro-peace’ rival J Street move in?
J Street’s liberal Zionist politics are landing with the Democratic establishment but the electorate may have moved on
Sugar Land commits to life science
Sugar Land is betting on life science, landing two life sciences expansions this year.
Packers Viewed as Ideal Landing Spot for $71M Star
Tampa Bay Buccaneers defensive tackle Vita Vea has requested a trade if he cannot get a deal done with his team. This has led many fans and media to suggest that the Green Bay Packers trade for Vea. JP Acosta of CBS Sports listed the Packers as one of the few teams that make the […] The post Packers Viewed as Ideal Landing Spot for $71M Star appeared first on HEAVY.
Phoenix Suns’ Starting Lineup Continues To Be Underrated
Despite landing Miles Bridges and boasting Devin Booker’s elite playmaking, critics rank Phoenix’s revamped starting five in the league's bottom third, fueling intense debate over their true potential.
Chargers named potential landing spot for All-Pro wide receiver
This All-Pro wide receiver has been linked to the Chargers.
Humanity's first look at the surface of Mars shared on 50th anniversary of historic NASA landing — Space photo of the week
NASA has unearthed the historic photos its Viking 1 lander sent home just after landing on Mars in July, 1976.
Florida State Grabs 315lbs Run Stopper From Transfer Portal
Mike Norvell bolsters the Seminoles' defensive front with a massive veteran presence, landing the former Texas State standout to fortify the interior ahead of a demanding ACC schedule.
Steelers named top landing spot for All-Pro wide receiver
Steelers tabbed as landing spot for the former All-Pro
Detroit Lions Named as Landing Spot for Diego Pavia
The Detroit Lions have been named as a potential landing spot for former Ravens quarterback Diego Pavia, but there's little reason to believe Brad Holmes will pursue him.
Deebo Samuel, free-agent WR, could land with Bengals, per CBS Sports
A CBS Sports writer identified the Cincinnati Bengals as a potential landing spot for free-agent former all-Pro receiver Deebo Samuel.
Of course Matt Damon told Ben Affleck about landing the lead role in ‘The Odyssey’ before his wife
Matt Damon admitted that he told Ben Affleck about landing the lead role in ‘The Odyssey’ before his wife Luciana Barroso.
New England Patriots Named 'Logical Landing Spot' for Jadeveon Clowney
Could the New England Patriots sign Jadeveon Clowney?
Penguins Interested in Using Connections to Land 44-Point Center
The Pittsburgh Penguins are interested in landing one of the top trade candidates in the market. It was recently revealed that the Seattle Kraken are moving on from Shane Wright this summer. Seattle previously drafted the center with the fourth-overall pick in the 2024 NHL draft. Despite lofty expectations, he regressed during the most recent […] The post Penguins Interested in Using Connections to Land 44-Point Center appeared first on HEAVY.
Tarik Skubal landing spots: Eight teams that could land ace at deadline (and why the Tigers may just keep him)
The Tigers ace is the hottest commodity on the market leading up to Aug. 3, but his availability isn't a sure thing
Science can serve dark as well as light
I’m not sure how many of you are watching “Star City,” Apple TV’s spin-off of its “For All Mankind” program (2019-present), but it’s one of the better sci-fi series I’ve seen in a while, with an impressively dark political message. (Some light spoilers below.) For the uninitiated, “For All Mankind” presented a slightly tweaked history of the U.S. space program in which it was the USSR that landed on the Moon first in 1969, and shortly thereafter put a woman cosmonaut on the lunar surface. This sparks an ongoing space race that, in the original series, yields a lot of benefits for humanity. President Nixon’s insistence on a female astronaut corps to compete with the Soviets boosts the feminist movement of the 1970s and the ERA passes. New fuels generated for the space program create clean and cheap energy around Earth. There are also some darker changes — the USSR is thriving well into the 2000s, there are terrorist counter-technology movements around the globe, laborers on Mars work in nightmarish conditions and organize strikes and riots, etc. the @smotus report is a reader-supported publication. To support this work, please become a paid subscriber. Subscribe That show offers glimpses into the subtle ways this Earth is different. Teddy Kennedy never went to Chappaquidick because he was racing back to Washington to deal with the space program crisis; he gets elected President in 1972. John Lennon survives his early 1980s shooting but Pope John Paul II does not. The Apple Newton succeeded. Pretty much the whole of season 4 is a setup for an Al Gore joke. Again, mostly, the vision that “For All Mankind” presents is a positive one, with technology advancing many human interests. “Star City” goes in a very different direction. This spin-off show is about the same set of events but from the Soviet perspective. As we meet them, the team of scientists and cosmonauts responsible for the lunar landing are still basking in their hero status, but their program is embedded deep in the Soviet security state of the late 1960s. Everyone’s apartment is bugged. Whole teams of clerical staff spend their days transcribing recordings of people’s lives. People in the program, including respected cosmonauts, are regularly arrested. An incredibly menacing Colonel Lyudmilla Raskova (Anna Maxwell Martin) forces confessions and tortures and kills, expressing little more than annoyance in the process. Meanwhile, the space program’s highly respected Chief Designer (Rhys Ifans) has a vision for the program that he knows the government will not approve. He insists that they need to think past the Moon to focus on colonizing the solar system, starting with Venus. (This is a rough parallel to the Americans’ pivot to Mars in the original show.) He essentially builds a secret space program within the space program, calculating that the government will embrace the mission after it has succeeded. (As an aside, I’m not sure why the Venus obsession, as a successful mission can’t produce the biggest public relations payoff: a cosmonaut standing on the surface holding the Soviet flag. Anyone standing on Venus would be immediately crushed by the 92-bar atmosphere and then cremated in the 900°F temperatures. But in a country with no free press perhaps the visual payoff was less valued.) But the overall vision is that the technological advances have only amplified the most fearsome aspects of the Soviet system. The state is paranoid (but not incorrect) about American spies and does monstrous things to protect its secrets. People are terrified to trust each other. Classic banality-of-evil figures order people to harm those they care about; those people comply rather than get shot. Others are forced into criminal behavior to protect loved ones. We’re reminded all the time these days of what happens when a government despises science. It manifests in the defunding of schools, the elevation of fossil fuels as the rest of the world pivots to solar, outbreaks of measles and diarrhea, etc. But “Star City” offers a vision of a bad government that likes science. It’s not encouraging. It’s not yet clear if there will be a season two of this show. But I strongly recommend season one. It’s both thoughtful and gripping. Share
Cowboys Called ‘Logical Landing Spot’ for $118 Million Free Agent
Bleacher Report's Kristopher Knox called the Dallas Cowboys a logical landing spot for free-agent inside linebacker Bobby Wagner. The post Cowboys Called ‘Logical Landing Spot’ for $118 Million Free Agent appeared first on HEAVY.
Anthony Edwards has accepted that LeBron James won't be playing for the Timberwolves
Anthony Edwards knows that LeBron James has not considered the Timberwolves in his preferred landing spots.
LeBron James' Latest Comments Are Great News for Warriors Fans
LeBron James may not have named a team, but his latest comments only fueled speculation that Golden State could be his preferred landing spot.
Pacers Fans Dreaming of LeBron James Get Harsh New Reality
The Indiana Pacers are not going to be the landing spot in free agency for LeBron James.
Reporter doesn’t flinch when cockroach lands on her, crawls around during live report
TV news reporter Rachel Menitoff’s reaction to a cockroach landing on her during a live report is going viral.
NASA selects four new Moon missions to build a permanent lunar base
NASA is ramping up its lunar ambitions by awarding nearly $600 million for four commercial Moon landings planned for late 2028. Each mission will carry the same trio of science instruments to improve lunar navigation, study dangerous dust kicked up during landings, and map the Moon's radiation environment. The agency also revealed plans for new rovers, communication satellites, and additional cargo missions as it lays the groundwork for a permanent Moon Base.
Zooey Deschanel went blonde to play pop star ‘like Britney Spears’ before landing ‘Elf’ role
Zooey Deschanel nearly played a Britney Spears-esque pop star in a film that was ultimately shelved, which nevertheless required her to go blonde, which she kept for her role as Jovie in ‘Elf.’
Warriors now know asking price for Bronny James-Lakers trade
The Golden State Warriors should feel confident about their chances of landing a 21-year-old Los Angeles Lakers guard if need be.
Lakers get game-changing Peyton Watson sign-and-trade news
The Los Angeles Lakers should feel more confident about their chances of landing a 23-year-old Denver Nuggets rising star.
World Cup a winner for local businesses
Bars like Olde Magoun's Saloon and Phoenix Landing have seen unprecedented sales. And businesses that aren't bars are also benefitting.
Electronic Health Record Ehr Systems Market Forecast Points Higher Toward 2035, Driven by Interoperability Mandates and Cloud Migration
World EHR systems market forecast to 2035: 6-8% CAGR, cloud adoption, interoperability mandates, and value-based care drive growth. Key players and regional insights.
Colts A Potential Landing Spot for Versatile Free-Agent Runner
The Indianapolis Colts could feel compelled to bring in a veteran running back this summer.
Tariff refunds landing for Colorado importers, though not without a cost for small business
At least $23.7B in refunds from unlawful tariffs have been refunded to U.S. importers out of an estimated $166B owed, according to court testimony
Bucs' Mayfield Disrespected in New QB Tier Rankings
Despite delivering Pro Bowl performances and stabilizing Tampa Bay post-Brady, Baker Mayfield remains overlooked, landing in a baffling "volatile" tier behind less proven signal-callers and aging stars.
Washington County Quorum Court OKs business permits for HS Studios, Fox Hunter Landing
FAYETTEVILLE -- Washington County's justices of the peace on Tuesday approved a pair of permits for businesses seeking permission to operate in unincorporated areas of the county.
Commanders becoming clear top landing spot for Stefon Diggs
The Washington Commanders could definitely use more wide receiver help, which makes them a prime landing spot for Stefon Diggs.
Bleacher Report Names Ideal Stefon Diggs Landing Spot
The New England Patriots released Stefon Diggs earlier this offseason, and he remains unsigned.
Movies, books, art and music to explore as America turns 250
As America celebrates 250 years, we size up how it’s been portrayed in, and has shaped, what we watch, listen to and read.
Life Science Reagent Market Forecast Points Higher Toward 2035, Driven by Biopharma Scale-Up and Cell Therapy Expansion
World life science reagent market forecast 2026-2035: CAGR 6-8%, index 2035=185. Bioprocessing, cell therapy, and QC drive growth. Key players: Thermo Fisher, Merck, Danaher.
Justin Jefferson lands inside top 10 of CBS Sports Top 100 list
Justin Jefferson represented the Vikings near the top of Pete Prisco’s CBS Sports Top 100 players list, landing at No. 8 overall.
Commitment: Texas lands 2027 three-star IOL Lucas Rhoa
The Texas Longhorns continue a great week of recruiting by landing 2027 three-star interior offensive lineman Lucas Rhoa.
Cavaliers named landing spot for ex-$206 million Lakers disaster
The Cleveland Cavaliers were linked to a former Los Angeles Lakers guard who struggled mightily with the franchise years ago.
Future astronauts could walk across rocks from deep inside the Moon
A colossal ancient collision may have left some of the Moon’s deepest secrets surprisingly close to future Artemis landing sites. By recreating the impact that formed the giant South Pole-Aitken basin—the Moon’s largest and oldest crater—scientists found that a low-angle strike from a large, iron-cored object blasted material from deep inside the Moon, including mantle rocks.
Trump says Meloni 'wants to be friends again' after Italy refused to help US amid Iran war
President Donald Trump said Giorgia Meloni did not let the U.S. use Italy's landing strips in its war against Iran and rejected being friends with her.
Indiana football lands commitment from 2027 linebacker Jalaythan Mayfield
Indiana football’s recruiting momentum carried it past Georgia and Miami on Friday afternoon in landing Mayfield.
Miami Heat or Boston Celtics? Predicting Giannis Antetokounmpo’s Landing Spot
Giannis Antetokounmpo is likely nearing the end of his tenure with the Milwaukee Bucks. Milwaukee’s self-imposed trade deadline for Antetokounmpo […]
Enjoying free entertainment at The Landing
(MASS APPEAL) – The Landing is Downtown Springfield’s newest outdoor event space, 2026 marks the first full summer of programming on The Landing. The space hosts dozens of community eve…
Ready for some vegetable-based entertainment this Father’s Day? | Los Gatan
Who’s ready for a day at the races? The legendary Annual Zucchini Car Races are making a comeback. They’re scheduled to return to the Los Gatos Farmers’ Market Sunday, June 21. Landing on Father’s Day, this will be a fun way to bond with the family and work together to design the perfect race car—out […]
NFC Team Named Most Obvious Brendan Sorsby Landing Spot
Texas Tech QB Brendan Sorsby is going into the NFL Supplemental Draft, and one NFC team is named the most obvious landing spot.
Colorado flips three-star offensive tackle from powerhouse SEC program
Colorado football pulled off an impressive recruiting flip Sunday evening, landing a three-star offensive tackle from a top SEC program.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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The post Power Rankings: Teams With Best Shots at Landing Larkin appeared first on Detroit Hockey Now. Dylan Larkin hasn’t said publicly what is his preference is for a trade destination. All we know is that he […] The post Power Rankings: Teams With Best Shots at Landing Larkin appeared first on Detroit Hockey Now.
Edgewood's Eva Akpandja wins second straight shotput State Title
LA CROSSE, Wis. --- Edgewood High School junior Eva Akpandja saved her best for last. The Crusader star won the D2 Girls shotput state championship on her final launch, landing
D‑day’s secret weapon: How wetland science stopped Normandy landings from getting bogged down
Beneath the roar of gunfire and the chaos of D-day, an unlikely hero played a vital role — wetland science. Often overlooked amid military strategies and troop movements, the study of mud proved critical to the success of the largest amphibious invasion in history.
NFL landing spots for Brendan Sorsby after appeal falls short
A look at six teams that could have interest in Brendan Sorsby if he enters the NFL Supplemental Draft.
Google introduces Search profiles within Google Discover
These are enhanced publisher landing pages, where you can follow the publisher, see the publishers latest articles, videos and social posts all in one place.
Home-Delivered Medical Meals Reduce ER Visits, Save Money
By Dennis Thompson HealthDay ReporterTHURSDAY, June 4, 2026 (HealthDay News) — Providing home-delivered, medically tailored meals to people with chronic health conditions lowers their risk of landing in a hospital, a new study says. Medicaid patients had fewer hospitalizations and ER visits while ...
Warriors get $15 million LeBron James free agent update
The Golden State Warriors should feel more confident about their chances of landing a Los Angeles Lakers aging star this summer.
How Science Works
The 2nd Weather and Climate Livestream is now underway. It is organized by a group of early-career researchers concerned about declining funding for the field and eager to demonstrate how weather and climate research makes a difference in our lives. Last year’s event was a great success, drawing terrific press coverage including a piece in the NY Times. This year features a strong lineup of talks aimed at a general audience — I highly recommend tuning in. Share I gave a talk yesterday about How Science Works in Three Steps. You can see the short presentation here (I’ve appended a transcript below): And please tune into the livestream here. It runs through tomorrow at 6 pm ET. Thanks for reading The Climate Brink! Subscribe for free to receive new posts and support our work. Subscribe Cleaned up transcript: Thank you, and thanks to everyone tuning in. I want to talk about something I think a lot of people don’t really understand: how science actually works. Arguments over any scientific topic — climate change, vaccines, you name it — revolve around competing claims. For climate change, the claims are: Is the Earth warming? Are humans to blame? What will the impacts be? Over the last 150 years, the scientific community has developed a remarkably robust method for sorting out which claims are true and which aren’t. That method is what I want to walk through. So how does science generate knowledge? If you ask a high schooler, they’ll give you the version they learned in ninth grade: an individual scientist forms a hypothesis, runs an experiment, and draws a conclusion. That’s more or less what happens at the individual level, though in practice it’s more iterative — you design, test, and refine all at once, landing on a slightly different idea each time until you reach a conclusion about whatever hypothesis you’ve ended up with. But this isn’t science. It’s only step one. Any individual scientist can make mistakes — scientists are human. Maybe there’s a bug in the code, maybe there’s an error in the experiment. Just because someone ran an experiment and reached a conclusion doesn’t mean it’s right, and scientists don’t treat a single result as settled truth. Step two is peer review, the first layer of quality control. The scientist writes up what they did and submits it to a journal, which sends the paper to other experts in the field. Those experts judge whether the methods are sound, whether it properly references prior work, and whether the conclusions actually follow from the data. Ask any scientist and they’ll tell you peer review is miserable — the comments come back brutal, often harsh, and you have to revise and resubmit, sometimes multiple times, before an editor finally accepts the paper. Peer review catches an immense amount of bad science, but it can’t catch all of it. Reviewers get sloppy or overworked, they miss obvious mistakes, and they can’t catch hidden errors — a bug in the code, a misread instrument. So a peer-reviewed paper making it into a journal doesn’t mean the paper is right. Nobody treats a single paper as the final word. That’s where step three comes in: the crucible of science. Important results get retested by the broader community. If you publish something interesting, it gets dissected. Sometimes people try to reproduce your work directly but more often they test its implications. If someone claims X is true, and that implies that Y is also true, then scientists will go check Y. If a claim survives this gauntlet long enough, it becomes accepted. That’s how we generate knowledge. Let me give an example: the ozone hole. In 1985 — and I doubt many people watching were around then, but I remember it well — Joe Farman and his colleagues published observations from Antarctica showing that a huge chunk of ozone was disappearing every year. This was shocking because most atmospheric chemists had expected ozone loss to occur at mid-latitudes and high altitudes, not over the South Pole. When scientists see something they don’t understand, they rush to explain it, and several competing hypotheses quickly appeared in the peer-reviewed literature. One pointed to chlorine chemistry from chlorofluorocarbons. A second blamed nitrogen chemistry, possibly driven by solar proton events — meaning the sun was responsible. A third argued it wasn’t chemistry at all but dynamics: winds were carrying naturally low-ozone air from the lower atmosphere up into the stratosphere. Then the community went to work testing which theory could survive the crucible. Aircraft flew into the ozone hole and found no nitrogen, ruling out the nitrogen theory. Measurements showed the air in the polar vortex was descending, not rising — which would bring high-ozone air down, eliminating the dynamics theory. Meanwhile, those same flights measured enormous amounts of chlorine, strongly correlated with exactly the regions where ozone was being destroyed. That became known as the “smoking gun” paper, and it established that chlorine chemistry was the cause. Through this process, a consensus emerged. And it’s worth being clear that this consensus is organic. There’s no vote, no poll, no meeting where it gets decided. Scientists go to conferences, talk to one another, and independently arrived at the same answer. It’s the ultimate free market of ideas. After the consensus was established, the peer-reviewed literature doesn’t even mention the rival theories — it simply takes chlorine chemistry as given. That’s what a consensus looks like. It doesn’t mean every single scientist agrees, but it does mean there’s no longer any legitimate debate. So where can you see what scientists actually think? It’s all in the peer-reviewed literature, which contains the entire historical record of the argument: the discovery, the competing theories, the debate, the testing, and finally the community coalescing around one answer. But there’s a lot of room for misrepresentation. You can dig up an old paper claiming the ozone hole was caused by dynamics and wave it around as if there still was a debate about the cause of the ozone hole — without mentioning that the idea was disproven long ago and that even its own authors no longer believe it. There’s a bigger problem, though: the peer-reviewed literature is written in a language I call “nerd.” It’s extremely hard to read — honestly, some of it is hard for me to follow. It takes graduate students years to work through the literature in a single field, so we can’t expect policymakers or ordinary people to do it. This is where scientific assessments come in. The most famous is the IPCC — the Intergovernmental Panel on Climate Change. The job of an assessment is to read and summarize the peer-reviewed literature, synthesizing what’s settled, what’s been disproven, and what remains genuinely debated. To ensure the assessments accurately summarize the peer-reviewed literature, assessments are written by large teams, which are far less prone to bias than individuals and which dilute the influence of any one scientist with an axe to grind. The teams are deliberately assembled to avoid stacking the deck, and the reports themselves go through multiple rounds of peer review. That rigorous process is exactly why you can trust them and why people consider the IPCC to be the gold standard of what we know about the climate system. An assessment produced through a different process may well not be credible. You can even watch the consensus evolve across assessments. Take the attribution of warming. The 1990 IPCC report said the observed warming was broadly consistent with model predictions but also comparable to natural variability — in other words, we don’t know whether humans are responsible. By 1995, it concluded that the balance of evidence suggested a discernible human influence — a sentence only a committee could write, and one that barely commits to anything. By 2001, most of the warming over the previous 50 years was judged “likely” due to greenhouse gases; by 2007, “very likely”; by 2013, “extremely likely.” The 2023 report says essentially the same as 2013 — there’s not much stronger language available. So, to wrap up: science is our ultimate tool for deciphering the universe — the most successful method we’ve ever developed for determining what’s true and what isn’t. Our understanding is written into the peer-reviewed literature, so if you want to know what scientists think, that’s where to look. And for those of us who don’t speak nerd, scientific assessments are the Rosetta Stone — they translate nerd into English. Let me open the floor to questions. Thank you.
Ravens, Raiders among top Deebo Samuel landing spots for 2026 season
Deebo Samuel remains a free agent but could be of interest to several NFL teams ahead of the 2026 season. Here are some of his best landing spots.
31 hours with the spit-shined Mina the Hollower (and 34 with the four games that came before it)
To truly appreciate Mina The Hollower, an extraordinary new throwback of a game, I sent myself to Yacht Club University. That’s not a real institution of higher learning, but it’s the best way I can explain much of the past several weeks as I prepared to play Mina by playing the four biggest game previously made by studio Yacht Club Games. I had expected Mina the Hollower, in development for six years for PC and consoles, to potentially be something special. A demo I tried in March had felt great. Mina the Hollower had an old-school premise: a singular move for its hero that felt so good to control and so rich with possibilities that, in the hands of skilled designers, it could be riffed on in various ways for the length of a full game. Mina’s core maneuver, her hollowing, made her sort of an upside down Super Mario. Nintendo’s hero jumps through the air, discovering power-ups at the apex of his jump by bonking overhead blocks, then defeating enemies by landing on them. Mina essentially jumps into the ground, digging (“hollowing”) into the earth to fetch buried treasure, then burrows for a short distance to emerge on the other side of a wall that hides treasure or an enemy that needs some battering. I wanted to understand how good Yacht Club was at making games. I wanted to see how far they’d come. If Mina was terrific—as I predicted it might be—I wanted to feel how they got there, one button press at a time. On May 6, 21 days before the writing of this review, I checked with Yacht Club Games co-founder and programmer David D’Angelo, to ask which of the studio’s games I should play to truly appreciate the new one’s design. “Hmmm all of them?” he wrote back. “Starting with Shovel Knight definitely is helpful,” he continued, referring to Yacht Club’s first game. He gave me a link to a spreadsheet of over 400 cheat codes that could help me out, if I found the game too tough.1 “Most folks say Specter of Torment is the least difficult and quickest to finish in terms of playtime, and [it] refines much of Shovel Knight,” he told me. “King of Cards is a big celebration of everything we did in [the Shovel Knight compilation] Treasure Trove— might work for you better if you’re a fan of shorter, Mario-style courses. And it’s probably the closest to Mina in terms of polish.” So that was that. Four games, none of which were required. Mina is a whole new game in a whole new world, best I can tell. I’d barely played that first Shovel Knight before and never the other three. I just thought it’d help. It did. It turns out that playing a game studios major works before their latest is very illuminating.
Las Vegas ranks among best summer travel destinations
Las Vegas ranks No. 38 overall in WalletHub’s best summer travel destinations report, while landing near the top for attractions and activities.
This unsealed Apollo 17 photo is the 'most significant evidence' in new UAP release, says doc director
'The Age of Disclosure' director Dan Farah reacts to the new tranche of UAP files released by the Department of War, singling out one image from the Apollo 17 moon landing as the 'most significant evidence.'
Feature: Moore ’26 Keeps Busy with Double Science Major and Music
Luke Moore ’26 came to Kansas Wesleyan on a music scholarship. He’s graduating this weekend (May 16) with a double major in Chemistry and Physics. He’s as active on the music side as he is with his science activities — he’s played the cello for 10 years, including four years at Kansas Wesleyan. It’s common, he said, for scientists and musicians to share those interests. “I’ve spoken to plenty of musicians who would have done science if they weren’t musicians, and I’ve talked to plenty of scientists who would have done music if they weren’t scientists,” Mooresaid. He played the cello in the string orchestra, which he’s done since his first year, and as a junior and senior, sang in the Philharmonic Choir as a bass. He hadn’t sung in a choir since middle schoolin Garden City, but he found he really enjoys that aspect of his college career. Also as a junior, Moore helped re-activate the STEM Club as vice president. For two years, he helped build the club’s battlebot. Last year the bot came home from battles in Kansas City in pieces, lots of pieces. This year it came home with the first-place trophy. He’s helped make frozen nitrogen ice cream at Homecoming and other events and helped organize the STEM Club’s first gingerbread house competition for the holidays. Willing to get his hands – and face – dirty for science, he encouraged fellow musicians and scientists to smash him in the face with whipped cream pies on Pi Day (March 14) as a fundraiser for the STEM Club. His capstone project involved developing a metallic organic framework (MOF) that takes a methylene blue dye out of water. “I’m proud that I was able to design this project, and I was proud that I did end up making the MOF,” Moore said. The professors and attitudes at KWU have made all this possible. “I don’t actually have time for everything,” Moore said. “I have to prioritize things. Things inevitably fall through the cracks, but it’s hard for me to choose one over the other, because I like a lot of things. And I don’t want to not do music, and I don’t want to not do science.” Moore said that Kansas Wesleyan, as a smaller university, gives students the opportunity to try things. “If I were to want to be in a music ensemble, it would probably be a bit harder in a larger school. One nice thing about this school is that everyone’s involved in something,” he said. “Professors know that you have other things going on, and they are flexible and understanding.” Moore has applied to grad schools, with an goal of earning his Ph.D. and landing at a university big enough to allow for a small research team that also gives him an opportunity to teach. He’s off to a good start. Moore is receiving the award for Outstanding Research in the Math, Physics and Computer Studies Department at Commencement this year. Story by Jean Kozubowski
Notre Dame Recruiting Roundup: Irish Stay Hot On The Trail
The Irish bolster their 2027 class by landing two massive offensive tackles, including a crucial flip from UCLA, while aggressively expanding their 2028 board across Florida and California.
Google launches a gorgeous new landing page for the upcoming Googlebook
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Accounts in Transit: Rosen Group Picks Up Kustom Entertainment
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Mars rover snaps a selfie near skyscraper-sized boulders
NASA's Perseverance rover has traveled nearly 26 miles since landing on the Red Planet in 2021.
Steelers linked to former Ravens Pro Bowl edge rusher
The Pittsburgh Steelers have been named a potential landing spot for ex-Baltimore Ravens edge rusher Kyle Van Noy.
Military Spouses, Small Business Owners Lobby Congress on Entrepreneurship
The push for expanded SBA support was timed with National Small Business Week.
NBA Draft Lottery 2026: Which teams could benefit most by landing the No. 1 pick?
Thirteen teams are hoping to win Sunday's NBA Draft Lottery, but who needs that pick the most?
Announcing the global launch of Web of Science Research Intelligence: An AI-powered research intelligence platform for funding, strategy, and impact
Web of Science Research Intelligence unites trusted data and AI to help research offices, library teams, and researchers secure funding and demonstrate impact.
Taco Mundo Kitchen y Cantina hosts eighth annual Cinco de Mayo celebration in North Myrtle Beach
At noon on Tuesday, May 5, Taco Mundo Kitchen y Cantina at Barefoot Landing kicks off the biggest Cinco de Mayo fiesta on the Grand Strand. General Manager Erin Parker said she expects that the celebration, now in its eighth year, will attract between 2,500 and 3,000 attendees.
Melco Resorts & Entertainment (NasdaqGS:MLCO) Margin Rebound Tests Bullish Earnings Narratives
Melco Resorts & Entertainment (NasdaqGS:MLCO) heads into its Q1 2026 update with recent quarterly numbers that put revenue at about US$1.3b in Q4 2025 and basic EPS at US$0.16. This caps off a year where trailing twelve month EPS reached US$0.46 on revenue of roughly US$5.2b. Over the past few quarters, the company has seen revenue range between US$1.2b and US$1.3b per quarter, while basic EPS moved from US$0.08 in Q1 2025 to US$0.19 in Q3 before landing at US$0.16 in Q4. This result comes...