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NFL QB Legend Kurt Warner Has Blunt Message to Sports Critics
Kurt Warner has seen the pressure that comes with professional football from nearly every possible angle, and the NFL legend recently delivered a blunt message to sports critics. The Hall of Fame quarterback expressed frustration with the growing tendency to attack athletes online as though performing under extraordinary pressure should be effortless. Warner acknowledged that […] The post NFL QB Legend Kurt Warner Has Blunt Message to Sports Critics appeared first on Gridiron Heroics.
Cowboys RB Handed First Career Fine in League Discipline
Malik Davis went from an undrafted afterthought to the Dallas Cowboys‘ primary backup running back this summer. He signed with the team in 2022 and built momentum last season by appearing in 10 games, rushing for 250 yards and two touchdowns. He took the next step during this year’s preseason, securing the definitive No. 2 […] The post Cowboys RB Handed First Career Fine in League Discipline appeared first on Gridiron Heroics.
Falcons Join Raiders And Vikings With Striking Season-Opening Trend
The Atlanta Falcons have made it official at quarterback, with the team announcing on Monday that they will be going with veteran Tua Tagovailoa under center for the start of their 2026 NFL season. A new quarterback to start a season has become a familiar sight for Atlanta and its fans. In fact, this is […] The post Falcons Join Raiders And Vikings With Striking Season-Opening Trend appeared first on Gridiron Heroics.
Sen. Jim Justice on breaking Senate gridlock, honoring Medal of Honor veterans, and realities of DC politics
In a wide-ranging interview, Sen. Jim Justice, R-W.Va., details how a private chat saved a national monument bill, shares his candid views on Washington’s partisan gridlock.
New CTE Study Delivers Sobering Reality Check on Long-Term Health Risks for NFL Players
As NFL teams close out the 2026 preseason and turn toward opening weekend, a new medical study is forcing a harder look at what football costs its players long after the final whistle. Dr. Daniel Daneshvar, a Harvard Medical School researcher, has spent years tracing the link between repeated head impacts and brain disease in […] The post New CTE Study Delivers Sobering Reality Check on Long-Term Health Risks for NFL Players appeared first on Gridiron Heroics.
San Francisco 49ers: Place Rotational Piece on Injured Reserve
The San Francisco 49ers’ EDGE rusher room is very thin heading into Week 1. Nick Bosa recently returned to practice at full capacity after recovering from an ACL tear and knee tendinitis, which later followed. Mykel Williams is on the PUP list while recovering from an ACL tear and meniscus damage and will miss at […] The post San Francisco 49ers: Place Rotational Piece on Injured Reserve appeared first on Gridiron Heroics.
Packers TE Tucker Kraft Predicted to Have Major 2026 Season
The Green Bay Packers could be preparing for another breakout campaign from Tucker Kraft, with a bold projection placing the young tight end among the NFL’s most productive pass catchers in 2026. After emerging as a major part of Green Bay’s offense, Kraft enters the new season with expectations that extend well beyond his position. […] The post Packers TE Tucker Kraft Predicted to Have Major 2026 Season appeared first on Gridiron Heroics.
Houston Texans: Rework Contract of Receiver Rehabbing from Injury
Houston Texans wide receiver Tank Dell is not quite ready to play after missing the rest of 2024 and the entire 2025 season while recovering from devastating ACL, MCL, and LCL tears, along with meniscus damage and a dislocated kneecap sustained in December 2024. Dell primarily participated in individual drills during training camp, along with […] The post Houston Texans: Rework Contract of Receiver Rehabbing from Injury appeared first on Gridiron Heroics.
Browns’ Todd Monken Dismisses Heat Complaints With Blunt ‘Blessing’ Message
Todd Monken has a hard job ahead of the 2026 NFL season. He has to lead the Cleveland Browns, a team that had a very poor 2025 campaign. There is a lot of expectations on both him and the team for the coming games. Despite this being his first head coaching role in the league, […] The post Browns’ Todd Monken Dismisses Heat Complaints With Blunt ‘Blessing’ Message appeared first on Gridiron Heroics.
Bold Rams Prediction Will Fire Up Los Angeles Fans
The Los Angeles Rams have been handed one of the boldest predictions heading into the 2026 NFL season, and it should give their fans plenty of reason for excitement. The forecast calls for the team to finish the year with both the league’s No. 1 scoring offense and No. 1 scoring defense, a feat accomplished […] The post Bold Rams Prediction Will Fire Up Los Angeles Fans appeared first on Gridiron Heroics.
Here’s where a massive solar storm could take down the US power grid
New research maps show where a severe solar storm could strike. See if your neighborhood would lose power.
Iran attempted cyberattacks on range of U.S. infrastructure, sources say
The attempts have so far been unsuccessful, but an Iranian hacking group warned that “unexpected and critical events” would soon target American infrastructure.
Skip Bayless Criticizes ‘Outrageously Wrong’ Shedeur Sanders Situation
Skip Bayless believes Shedeur Sanders has been placed in an unfair situation with the Cleveland Browns, and the outspoken sports commentator did not hold back in his latest criticism of the organization. Bayless described the quarterback’s circumstances as outrageously wrong after another development complicated his path to meaningful playing time. Sanders entered the 2026 season […] The post Skip Bayless Criticizes ‘Outrageously Wrong’ Shedeur Sanders Situation appeared first on Gridiron Heroic
August Monthly Review: ChatGPT In Epic
Death, taxes, another frontier lab healthcare launch inspiring truly insane LinkedIn takes. As much as I want to stay away, I repeatedly am the crewman unplugging his ears whenever we pass these sirens. So it’s not the first and probably not the last time we dial up the typewriter rather than tie ourselves to the mast. The full blow-by-blow timeline: Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe The End of the Standalone PHR (Jan 8): ChatGPT Health arrives for consumers, at the time powered by b.well. I was bullish on the approach in that the best way for the PHR to finally solve distribution was to meet consumers were they already are (i.e. When Horizontal Meets Healthcare (Jan 9): OpenAI for Healthcare puts out the shingle for enterprises, with SharePoint ingestion standing in for the EHR integration the product actually needed. Another One: Anthropic’s Healthcare Debut (Jan 16): Claude's version, on HealthEx rails instead of b.well, with Agent Skills for FHIR development as the one true vertical-specific investment. ChatGPT for Clinicians: The Trap Sprung (Apr 24): OpenAI filled in the missing GTM middle with a free product for verified clinicians, effectively peeling the enterprise wrapper off ChatGPT for Healthcare and taking the PLG fight directly to OpenEvidence. OpenAI’s Second Attempt at Health (Jul 31): a relaunch of their patient specific app, now branded Health in ChatGPT, where the privacy partition came out, the connectors thinned, and b.well disappeared in favor of first-party FHIR work against a smaller network Beyond a Shingle So what was announced now? Today, we’re introducing a new electronic health record integration that brings authorized patient context from Epic into ChatGPT for Healthcare, along with the Healthcare Public Data plugin for direct, structured access to official healthcare datasets like PubMed, DailyMed, and CMS Coverage. Together, these capabilities bring ChatGPT closer to the systems and sources healthcare teams trust, while supporting the controls and compliance healthcare work requires. The core portfolio is unchanged from prior announcements we delineated and discussed (aside from the relaunch of patient-facing). Since trade publications still seem to be confusing them by using the wrong names: Enterprise sales motion: ChatGPT for Healthcare Protecting their core product / PLG: ChatGPT for Clinicians Consumer/patient-facing product: Health in ChatGPT So really, this is a feature release (specifically for ChatGPT for Healthcare when it comes to EHR integration). What’s cool about it, though, is that we are moving beyond just putting out a shingle. Everything in the January enterprise launch was horizontalizable: Horizontal tech companies thus generally start verticalization with their “putting out a shingle phase”. Telling the world you’re open for business as a horizontal tech company reliably attracts early inbound interest from buyers who are already trying to force-fit horizontal tools into domain-specific workflows and are eager for any signal that the vendor intends to support their use case more directly. Nothing was really vertical specific, which is exactly what you'd expect from the ultimate hypergrowth horizontal company dipping their toes into specific industries. But eventually you have to stop changing the sign on the door and start changing the product. Can you guess where the horizontal product was going to run out of road? This is the core dilemma writ large: verticalization requires differentiation, while scale economics of consumer and horizontal push toward unification. I’ve buried the lede so deep here it will be painful to some readers, but what should be shocking to no one is that my perspective is that EHR integration is the only path that meaningfully resolves this tension for ChatGPT for Healthcare. Integration with Microsoft Sharepoint is fine, but it is categorically insufficient for any product that hopes to influence clinical decision-making. SMART Money Well here we are, eight months later! Real vertical investment has begun, which surprised a few people. One friend in the industry messaged me: “Absolutely no way Epic gave ChatGPT API access.” Looking forensically at the announcements, the integration is notably read-only across appointment notes, laboratory results, medications, and specialist documentation. So while I’m not a betting man, I'd wager the house this is a SMART on FHIR launch: That sounds a lot like USCDI! The recommended path for the workflow they outline would be SMART on FHIR Their Health AI lead’s post is evocative of both standalone and EHR launch SMART, which another termed “ChartGPT” and “EHR Plugin” The implementation burden for SMART on FHIR is the lowest of the available integrative paths This is the team who literally did patient-facing SMART on FHIR with Epic last month Most importantly, if you’re a horizontal company, you generally still haven’t taken the full plunge and thus (overly) value reusability. SMART on FHIR is the logical compromise: healthcare-specific enough to matter, but standardized enough to reuse. Nobody Asked Judy Another friend asked “I thought they had to go to each health system, or did they go direct to Epic and now health systems opt in?” Given the trust paradigms in healthcare, this functionally cannot be Epic hoovering up all the data for OpenAI and shoving ChatGPT in their customers’ faces (or they would revolt). However, I do believe the aforementioned terrible coverage by TechCrunch and other outlets is probably responsible for that question, given the 325 million reference. When using FHIR as a business associate to an Epic customer, there is no EHR gatekeeping to speak of, as that isn’t how fhir.epic.com works: You register an app You pick your APIs You test against the sandbox APIs You list as “Ready for Production” Hospitals pick your app You test and go live with them Bluntly, nobody had to say yes or no in Verona (nor were they given the chance). Vendor Services (their next developer tier up that I doubt OpenAI is using quite yet in this initial release) certainly has contractual paperwork that some resent, but even there, the twin pressures of mounting antitrust and information blocking make outright gatekeeping increasingly fraught. My friend’s sentiment is, to me, representative of a broader industry neurosis, perhaps a sort of scar tissue of prior eras: people assume the gate is still there and never actually try the door. There are certainly other ways Epic (and any EHR) can put its thumb on the scale, but they are not so dumb as to stand in front of a federally mandated API and play bouncer at this exact moment in time. So I think they can and probably should go deeper, as this release is at best parity and at worst behind vertical-specific competition. OpenEvidence did a basic SMART launch with Sutter Health in February, allowing for more convenient evidence search by providers. They then add patient-context (the equivalent SMART on FHIR flow to what we see here) when Cedars-Sinai went enterprise-wide in May. UpToDate has four distinct applications across deeper workflows like patient engagement listed in Epic Showroom and announced a partnership with Epic to power Art at UGM Abridge and other ambient scribes have invested deeply into the deepest bidirectional clinical copilot workflow with integrations well beyond SMART on FHIR. In that light, the “Who is OpenAI primarily targeting here?” is clear. This release brings them into striking distance of OpenEvidence, but not the others quite yet. They are the only one of the three you can reach without building something truly Epic-specific. When will they go further? Competition is a great motivator to overcome the horizontal demons and start building things that can’t be reused: not across industries, not across EHRs, maybe not past the customer you built them for. That’s the price of actually verticalizing. The question is if and when OpenAI will be willing to pay it. Month in Review Here is the monthly review. As a reminder, this is a regular round-up of the month’s posts and other content to surface things you may have missed across regulation, litigation, interoperability, and beyond. AI assistance is used in these bullet summaries so I can focus on articles. Articles Published: None this month Video Content: The Information Exchange: Standards-based Thruple Edition (Aug 14): Back to school for us too, with Brad reporting in from the CMS Health Tech Ecosystem’s one year anniversary in DC. We get into the January CMS-0057 deadline, the fall rulemaking reading list, and why enrollment still keeps most apps off FHIR. The Information Exchange: Epic Dúnadan Edition (Aug 25): A UGM roundup with Ryan Brickner joining for the first time to check our takes against what the building actually thinks. Rangers, Ergo sitting on top of EHI, and a down-market lineup that needs some cuts. Regulatory: Stacked Deck, Bad Hand (Aug 05): ONC’s website refresh took the entire HIT Policy Committee record with it, so I rebuilt the archive and went looking for the regulatory capture story everyone assumes is buried in there. Stacking the deck and winning the hand turn out to be very different things. The Sixth Generation of Patient Access (Aug 19): A quick catalog of the five generations of patient access we’ve layered on since HIPAA, and the two candidates now competing to be the sixth. One is planned. The other is the market routing around the plan entirely. Court cases: Three Cases Walk Into a Docket (Aug 06): Two surprise settlements cleared the board in a single week, and then Judge Maddox dropped ninety-four pages on Vyne v. Henry Schein. The sleeper is a DMCA holding that makes direct-to-database a considerably riskier business model. Epic v. Health Gorilla: Into the MDL (Aug 10): Nine class actions are headed to Miami, and the Panel signaled it wants to bring the case that spawned them along too. That would leave Epic arguing the requests were obviously fraudulent in one courtroom and unknowable in the other. Amazon v. Perplexity: Agents Are Legalized! (Aug 11): The Ninth Circuit vacated the injunction against Comet, holding that the user is the one accessing the servers rather than the company that built the agent. A real win for agentic access, and a much narrower one than the headline suggests. Veeva v. Epic: Come At Me, Bro (Aug 26): Epic’s response brief wants the dismissal affirmed and, unusually, wants the opinion published as precedent. Buried in it is Epic’s own description of what its non-competes actually prohibit, which current and former employees should read closely. EHRs: The Contract Epic Would Never Sign Today (Aug 04): A 1999 SEC exhibit catches Epic licensing nearly its entire product line, Tapestry included, to the company that became TriZetto. The marketing services menu attached to it is the part that will make you blink. Forecast from Verona (Aug 07): The Epic Almanac makes one argument six different ways: the AI is only as good as the networks behind it. Emmie headlines, Art’s context stack is the most ambitious part, and Penny finally gets an autonomous coding date on the calendar. Works With Epic MyChart (Aug 17): Epic’s first new Showroom category since the death of Workshop certifies hardware instead of software, badge on the box and all. Made for iPhone, but for blood pressure cuffs, and rough news for anyone selling the RPM stack sitting in between. UGM Hot Takes 2026 (Aug 20): Everyone else covered the AI announcements, so I went after Savvy deleting the payment gateway, Rangers as Boost with the timer removed, and a down-market lineup with too many entries. Plus the Health Grid tidbits I cannot help myself on. MyChart Central Grows Up (Aug 24): Device data and Emmie turn Epic’s identity hub into a full consumer platform, which is both a logical answer to ChatGPT and a bit of a mistake. It also happens to be the best scraping target Epic has ever shipped. Industry Analysis: The Wrong Yardstick (Aug 12): Vertical software keeps getting judged against Superhuman and Notion, which is the wrong bar entirely. Your user is comparing your product to a whiteboard and forty phone calls before lunch. Primitives vs. Abstractions (Aug 27): Developers want building blocks, systems of record prefer to hand out business logic, and both sides have a real case. There’s no test from the outside that separates the engineering reason from the competitive one, which is why this keeps ending up in court. Cross-industry Comparisons: The Two Kinds of Platform Power (Aug 18): Attention power and record power are different problems that keep getting handed the same regulatory toolkit. Congress’s latest swing at Big Tech shows both what’s possible and where it falls apart. The Dogs of (Platform) War (Aug 21): A CourtListener alert turned up a property management fight with healthcare’s exact shape and none of the Cures Act. Shell prospects, ghost accounts, a notetaker bot that came back to haunt someone, and a lawyer arguing both sides of the same theory in two states. Fractals All the Way Down (Aug 31): Yardi dominates property management right up until you zoom into one segment, where AppFolio owns it outright and Yardi doesn’t appear at all. Where you draw the line around a B2B software market is about to decide an awful lot of cases. Other News: If Judy Had the Courage (Aug 13): A short eulogy for the era when software was allowed to look insane: WinAMP, bold colors, and everything the grey chatbot era has taken from us. External Media: Portland Monthly Health Tech Meetup: Erin O’Brien channeled my own feelings - maybe it’s just because it’s August and beautiful, but the monthly edition of the PDX Health community meetup was a ripper. Make sure to reach out if interested to join for the next one. STAT’s Coverage of Epic This Month: Brittany Trang of STAT did a fantastic job of breaking the FTC investigation that’s been lurking, as well as UGM related coverage, so I had to give her her wish of a meme. Fall Conferences: I’m pumped to be kicking off my fall conference season in NYC at Nabla Accelerate next month, which Chrissy provided the link to apply for. Here’s the rest of my schedule in case you want to meet up: Commonwell (Redwood Shores, CA): Oct 13-14 Open@Epic (Madison, WI): Oct 21-22 eHealthExchange (Austin, TX): Oct 27 Sequoia Project (Austin, TX): Oct 28-29 HLTH (Vegas): Nov 15-18 RSNA (Chicago): Nov 29-Dec 3 Posts I Liked: HTI-6 Should Unbundle API Certification: Josh Mandel makes the case that HTI-6 should split (g)(10) into separate authorization and data certifications, so a PACS or a genomics platform can certify only the role it actually performs. Imaging is the urgent example, but the structure solves a much bigger problem. On implementing ePrior Auth with Epic: Scott Rossignol’s field notes from a live ePrior Auth build on Epic, including the two app registrations nobody warns you about and the CPT mapping problem waiting at the end. CMS-0057 implementations are going to be such a beast. Healthcare point solutions are starting to look a lot like streaming services: Spencer Dorn runs the cable-to-streaming arc against health IT and lands squarely on the bundling half of the cycle. Bundling can be good! It can also be bad! Life is nuanced. Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Data center growth could outpace power generation
Dominion Energy confronts rising power demand from nearly 650 data centers in Virginia, straining the grid and prompting infrastructure investments.
A temporary COVID-era subsidy helped Americans afford health care. Then it vanished
Congress let enhanced ACA subsidies expire after months of political gridlock. Millions now face premiums they can no longer afford
Cincinnati Bengals: Could Move Underwhelming Ex-2nd-Round Pick
Cincinnati Bengals’ former second-round pick Kris Jenkins has not lived up to the high draft selection of the 2024 NFL Draft. Jenkins had an okay second season, totaling 36 tackles, two tackles for loss, three quarterback hits, 27 stops, 13 pressures, and 1.5 sacks across 14 games, four starts, and 497 defensive snaps, the third […] The post Cincinnati Bengals: Could Move Underwhelming Ex-2nd-Round Pick appeared first on Gridiron Heroics.
Browns Rookie KC Concepcion Draws ‘Worst Case Scenario’ Outlook
The Cleveland Browns have been a magnet of attention in the offseason, largely because of the quarterback battle involving Shedeur Sanders and Deshaun Watson. However, a rookie is also turning heads in Cleveland Nation, and that player is none other than first-year wide receiver KC Concepcion. It remains to be seen whether Concepcion will develop […] The post Browns Rookie KC Concepcion Draws ‘Worst Case Scenario’ Outlook appeared first on Gridiron Heroics.
Browns Rookie Filled With Emotion Ahead of Huge Personal Milestone
The quarterback battle between Deshaun Watson and Shedeur Sanders has mostly been the story to follow in the offseason on the side of the Cleveland Browns. That is now settled, with Cleveland deciding to go with Watson over Sanders, at least for Week 1 of the 2026 NFL season against the Jacksonville Jaguars. But Cleveland’s […] The post Browns Rookie Filled With Emotion Ahead of Huge Personal Milestone appeared first on Gridiron Heroics.
Bipartisan Energy Politics | Reading and Podcast Picks
Reading and Podcast Picks is a collection of what we’ve been reading and listening to over the last week or so about energy topics. In addition to these R&P Picks, paid subscribers receive access to the full archives, Grid Roundups, and select episodes of the Energy Capital Podcast. Please subscribe today. Texans, legislators debate transmission lines at hearing | Texas Tribune “Republican legislators, Democratic statewide candidates, landowners from rural Texas and environmentalists” alike joined together Wednesday to protest the buildout of 765-kV lines across the state. At the protest and nine-hour hearing that followed, lawmakers heard a variety of recommendations, including from local officials arguing for more local control of data center proposals and more time to reform the process behind approving transmission lines across Texas. Though discussed in separate hearings, landowners and protesters said the issues are connected… Regulators have already been working through a new way to decide how much of the cost of building new transmission lines needs to be paid for by individuals and how much needs to be paid for by companies such as data centers. Experts said they believe the new system will lower the burden on residential consumers relative to the industrial groups. Data-Center Backlash Leads to New Land Rush in Texas Oil Patch | The Wall Street Journal While the data center protests rage, investors converge on the Permian Basin to build data centers powered by cheap natural gas. “A lot of places you see all over the country they’re worried about water, they’re worried about power, they’re worried about transmission, and the Permian has all of those things in spades,” said EagleRock Chief Executive Greg Pipkin Jr. Dallas-Fort Worth Dethrones Virginia as the World’s Top Data Center Market | Dallas Innovates Two reports show growth in North Texas data centers despite political concerns about the industry. Boasting five highly ranked data center markets, Texas is experiencing an explosion of data center activity. Long anchored by the DFW market, “the state is growing at a pace that could soon bring total installed capacity in line with — and potentially beyond — that of Virginia,” the Cushman & Wakefield report said. A new report from commercial real estate services provider JLL takes a slightly different view, anointing Texas the top data center market in North America. Texas eclipsed longtime frontrunner Virginia based on the level of existing and under-construction data center inventory in the state as measured by gigawatt capacity. A gigawatt equals 1 billion watts.
Lewis Hamilton Reportedly Renews Ferrari Contract Ahead of Monza
The Formula 1 driver market just received a massive update regarding the grid’s most decorated champion. Lewis Hamilton has reportedly renewed his contract with Scuderia Ferrari, guaranteeing his presence in Maranello well beyond his initial two-year commitment. According to the…
Who are your 5 Most Important Chicago Bears?
The latest @TheRealEvanMac & @RossRead Show talking roster battles, 5 Most Important Bears, and more @2ndCityGridiron is right here!
Baker Institute fall calendar brings global leaders, foreign policy scholars and science innovators to Houston
The Baker Institute’s fall 2026 calendar will bring prominent policymakers, scientists, business leaders and scholars to Houston this fall for a series of public conversations on energy and grid resilience, artificial intelligence and health, global affairs, demographics, science policy and the future of Texas.
Data centers in Texas prove a key topic months away from midterm elections
A recent poll shows the majority of Texans support requiring large AI data centers to disclose water use and fund their own power grid upgrades.
In redrawn FL-23, incumbent Rep. Lois Frankel battles political outsider Victoria Doyle
The 78-year-old from West Palm Beach — who has been in elected office since the mid-1980s and in Congress since 2013 — is facing a progressive challenger, Victoria Doyle, 60, a retired intellectual property attorney and local activist.
Archer Aviation Exec Says Boeing Deal Will ‘Significantly Change the Profile’ as $200 Million Insitu Business Joins Portfolio
Archer Aviation Inc.‘s (NYSE:ACHR) deal with Boeing Co. (NYSE:BA) could significantly reshape the electric vertical take-off and landing (eVTOL) company. Insitu’s $200 Million Revenue Business During the company’s second-quarter earnings call on Monday, Archer’s Chief Financial Officer Priya Gupta hailed the company’s acquisition of unmanned aircraft systems manufacturer Insitu, as well as autonomous eVTOL maker Wisk Aero and SkyGrid in an all-stock deal. Read Also: Rocket Lab USA, Hims & Hers,
Self-flying air taxis and drones: Boeing sells key aviation technology businesses to Archer
Boeing is selling Wisk, SkyGrid and Insitu to Archer in a major deal combining autonomous aircraft, drones, airspace technology and AI.
The Boyz’s Eric signs with Grid Entertainment, continues music career
The singer hopes to “show new sides” of himself with the label, while continuing band activities under another agency.
60,000-year-old ostrich eggshell engravings reveal a surprisingly sophisticated human mind
More than 60,000 years ago, humans in southern Africa were engraving ostrich eggshells with intricate geometric patterns that appear far more organized than previously realized. Researchers found recurring grids, parallel lines, right angles, and repeated shapes, suggesting the designs followed deliberate rules rather than being improvised. The engravers may even have planned entire patterns in their minds before carving them.
National Grid's BioBus brings science lab to Albany's Lincoln Park
WRGB CBS 6 provides local news, weather forecasts, traffic updates, notices of events and items of interest in the community, sports and entertainment programming for Albany, New York and nearby towns and communities in the Capital City area, including Cohoes, Watervliet, Colonie, Bethlehem, Guilderland, New Scotland, Coeymans, Green Island, Knox, Berne, Westerlo, Rensselaerville, Colonie, Menands, Green Island, Ravena, Altamont, Voorheesville.
Morgridge hosts annual science camp for rural high school students
The Morgridge Institute’s Rural Summer Science Camp allows Wisconsin high school students to experiment in the University of Wisconsin-Madison’s world-class bioscience labs.
Former NCCU Director of Athletics Dr. Wicker McCree Named Women Leaders in Sports Nike Lifetime Achievement Honoree
Durham, N.C. - Former North Carolina Central Director of Athletics Dr. Ingrid Wicker McCree, who retired from NC Central after 30 years of service as a coach and administrator in 2021, was announced as a Nike Lifetime Achievement Award honoree by Women Leaders in Sports on Tuesday.
Engineers build world's first portable diamond-powered quantum computer — it works at room temperature and can be plugged into an outlet
The world's first portable, room-temperature quantum computer with more than 10 qubits utilizes flawed lab-made diamonds. The quantum system fits into a standard server rack and connects to a typical power grid.
Data Centers and Politics: Game Changers for FERC?
The AI and data center eruption is transforming the U.S. electric power grid and could also transform FERC, Peter Behr writes.
A milestone year for Morgridge Summer Science Camp
On July 31, the 20th annual Morgridge Summer Science Camp said good-bye to its final group of campers. Over the course of three one-week sessions, 75 students along with their teachers, from 13 districts across the state, envisioned their futures in the biomedical sciences at the Discovery Building and UW–Madison’s campus.
Op-ed: A community banker’s case for New York’s digital infrastructure
Our grid needs modernization whether or not another data center is ever built.
The power plant players unlocking the grid | Investors Lab
History is full of aha moments where an apparent failure was actually the breakthrough people didn't know they needed. Take champagne, discovered when French winemakers kept finding their bottles exploding under pressure. Or sticky notes, developed from a glue that was rejected by leadership at 3M for being too weak, but later redeployed for the purpose we all know and love. Nuclear fusion just experienced another of these serendipitous discoveries. For decades, it wasn't clear how the subatomic particles known as alpha particles would affect the turbulence that drains heat from a reactor's core, preventing the reactor from reaching self-sustaining fusion. Now, new simulations suggest that the particles help. The new research turns what was once viewed as a potential operational hindrance into a critical performance booster. SN's Emily Conover has the info blast.
Pixel Watch 5 shows up early in an official Google app
The Google Health app is already listing the Pixel Watch 5, weeks before the wearable is due to be officially unveiled.
Supreme Court tees up new test of FERC’s political independence
A recent ruling could spell trouble for the agency that oversees gas pipelines and the nation’s grid.
Starting Grid For The 2026 F1 Hungarian Grand Prix
Lando Norris took pole position for the Hungarian Grand Prix while Lewis Hamilton received a grid penalty that dropped him down from second. Here's the full starting grid.
How Free Batteries Help NYC Small Businesses Save on Electric Bills
Power-supplier startup David Energy is giving local businesses like laundromats and pizza shops free batteries to avoid price surges when the grid is tight.
Could the data center moratorium cost New York grid investments?
Hochul says over the next year, a public service commission will consider options including setting up a separate rate system for data centers.
Can a Madison summer camp get teens interested in science careers?
After two decades of hosting a camp, researchers at UW-Madison’s Morgridge Institute are evaluating the program's long-term impact.
Power grid serving Northern Illinois faces breakup risk as feds weigh fate
A frustrated Trump administration wants major changes to the operator of America’s largest power grid as federal regulators meet this week.
Wisconsin Health Executive Thomas Westrick to join Morgridge board
Thomas Westrick, a Milwaukee-based veteran executive who most recently led GE Healthcare’s Patient Care Solutions segment, has been elected to the Morgridge Institute for Research Board of Trustees.
Summer is winding down: Health tips for parents ahead of the school year
Summer break is wrapping up for students across the Piedmont Triad, and many parents may be wondering how to ensure their children have a good start to the school year. Here's what health experts suggest.
A hotter Europe needs Israeli science
The recent heat dome that swept across the continent pushed temperatures to record levels, strained electricity grids, disrupted transport, and forced governments to issue public health warnings.
Discord accidentally banned over 8,000 people for posting grids and other ‘benign’ images
Discord blames a bug affecting its safety system.
CBS Sports Names Alabama the Greatest College Football Program of Three Different Decades, and It's Hard to Argue
Spanning the 1930s to the 2010s, the Crimson Tide outpaced every other powerhouse to claim historic dominance across three distinct eras of gridiron excellence and consistency.
Veteran trucker: AI made job safer but autonomous trucks aren't ready
Ingrid Brown, a trucker of 47 years, said technology like the cellphone and AI has made truck driving safer but autonomous trucks still need work.
British GP Starting Grid | Ferraris look to deny Antonelli victory
Championship leader Kimi Antonelli is set to start the British Grand Prix from pole position, with the two Ferraris hoping to overtake the youngster off the line. Here is the starting grid for today's race at Silverstone.
Scientists Propose ‘StormWall’ To Stop A $2.4 Trillion Solar Storm
A proposed StormWall spacecraft fleet could release gas to weaken solar storms, protecting satellites, power grids and technology, but potentially reducing auroras.
'Cautiously optimistic': Swing voters describe their view of America at 250
As America turns 250, voters from our Swing Shift project talk about the state of the country. Their views ranged from "uncertain" and "concerned" to "excited" and "cautiously optimistic."
'Cautiously optimistic': Swing voters describe their view of America at 250
As America turns 250, voters from our Swing Shift project talk about the state of the country. Their views ranged from "uncertain" and "concerned" to "excited" and "cautiously optimistic."
Former top Bills draft pick find new path in football
A new outfit on the gridiron for a former Bills top-five draft pick.
F1 practice LIVE: British Grand Prix 2026 UK time, start time, grid, radio & updates
Follow live text updates and listen to BBC Radio 5 Sports Extra commentary of practice for the British Grand Prix.
Step Into the Modern Era in EA SPORTS College Football 27 with EA Play
It's time to take the gridiron in EA SPORTS College Football 27. Get game-day ready with an EA Play 10-hour early access trial.
Wisconsin Badgers to add Culver's logo to uniforms for football, 2 other sports
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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