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Politics & Power: From cyberattacks to job losses, what AI means for security & livelihoods worldwide
Nick Allard, dean of the Jacksonville University College of Law, joins News4JAX anchor Bruce Hamilton on this week’s episode of “Politics & Power” to discuss the double-edged sword of AI as both threat and solution and what world leaders must do now.
This Weekend in Gators Sports: Tennis Wins Big, Swim and Dive Stays Perfect
Florida swimming and diving and men’s tennis posted strong results on the road over the weekend. Gators men’s tennis returned to Gainesville stamping 15 wins on the weekend at the three-day Bedford Cup hosted by UCF, while Florida men’s and women’s swim and dive remained undefeated against Kentucky 31-0 all time. Men’s Tennis: Doubles Title […]
'Tacoma isn’t safe’: Downtown businesses call for action after double homicide
Tacoma police are investigating after two men were shot and killed downtown just before 12:30 a.m. Sunday.
Fear is bigger than ever… and Zero Latency VR has the science to prove it
MELBOURNE, Australia — Zero Latency VR, the world’s largest and most innovative immersive VR network, is celebrating a double Halloween anniversary: three years since the launch of Outbreak, …
Mark Cuban offers fix for NJ's health care cost crisis
As New Jersey workers face another double-digit increase in health care premiums, billionaire entrepreneur Mark Cuban is offering to help.
Malick Thiaw’s Clean Sheet Double For Germany Under Klopp
The Newcastle defender solidified his place in Jurgen Klopp’s new-look backline, showcasing elite composure and tactical growth while anchoring two dominant shutouts on the international stage.
How you can watch the Jets-Bears game
CBS has a doubleheader today while FOX will show a single game to each region. If you live in the New York area, you will see: Jets at Bears early on FOX Cardinals at Giants early on CBS Chiefs at Raiders late on CBS Kickoff time for the game between the Jets and the Bears […]
Prisma doubles down on Urgent Care while Novant pivots to virtual visits
Two large South Carolina providers are pursuing opposite strategies. Prisma Health is acquiring 36 Urgent Care Centers from Novant Health, doubling its portfolio. Novant is moving toward virtual offerings.
One last shock twist in the NRL grand final pre-show entertainment debacle
Fans did a double take when they saw this famous face during the tribute to Jai Arrow.
What was Austin Wells thinking on costly Yankees baserunning play?
In a measured tone, Austin Wells talked about his decision to stretch a double into a triple in ALDS Game 1.
'Monty Python' legend John Cleese doubles down after incidiary posts about Islam spark UK compaint
In social post, Trump endorses Cunningham, mispronounces Vasquez’s name and doubles-down on renaming New Mexico
By Pat Davis, New Mexico Political Report — President Donald Trump officially endorsed Republican Greg Cunningham’s bid for Congress in a social media post today where the president once again called on New Mexicans to rename the state “New America” and mispronounced the Hispanic pronunciation of current Democratic Congressman Gabe Vasquez’s name. This story was […]
Dodgers continue quest for World Series three-peat
The Los Angeles Dodgers will begin their MLB play-off campaign on Saturday, with the defending champions playing in a double-header live on the BBC.
'Double-edged sword': Trump blitzes red states amid plunging popularity
Trump is spending precious campaign time and funding in GOP states rather than challenging Democrats in the closest races for control of Congress.
Chicago expanding mental health crisis response program to double available hours
Stage 12 West opens in downtown Mesa
Stage 12 West, a new restaurant that doubles as a live entertainment venue, opened its doors in downtown Mesa on Friday morning.
Bishop’s computer science chair says AI is eliminating ‘grunt work’ and reshaping digital jobs
Dr. Russell Butler, chair of Bishop’s University’s Department of Computer Science, says artificial intelligence is increasingly taking over routine digital “grunt work,” changing the skills students and workers may need in the years ahead. Photo courtesy of Bishop’s University. Click here to read our platform! Get local news like this every morning. Subscribe free below. Subscribe Pulse Newsroom Artificial intelligence is already taking over some of the routine digital work once performed by entry-level employees, according to Bishop’s University Computer Science chair Dr. Russell Butler — a shift he believes will make expertise, judgement and the ability to evaluate AI-generated work increasingly important. Butler described the change as automation reaching what he calls the “bottom of the cognitive pyramid” during an interview with The Pulse about AI, university education and the future of digital work. His argument is not that humans are disappearing from the workplace. Instead, he sees their role changing as AI becomes capable of handling more of the repetitive tasks involved in computer-based work. “Everything’s converging on just AI basically doing all the grunt work,” Butler said. The bottom of the cognitive pyramid Butler is from Lennoxville, completed his undergraduate studies at Bishop’s and later earned his PhD at the Université de Sherbrooke. He joined Bishop’s in 2019 and now chairs its Department of Computer Science. He uses AI in research, teaching and other creative work, and said the technology is increasingly capable of handling routine digital tasks that once required substantial human time. “You’ve got the grunt work, like moving things around in Excel, doing basic programming tasks,” Butler said. “That’s like the bottom grunt work that the entry-level worker would have done two or three years ago.” Butler went further, saying in his view that much of this type of work has already been absorbed by AI tools. He connected that change to a shift he sees taking place in computer science, where entry-level roles have declined while experienced workers can use AI to increase what they can produce. “A senior developer now has access to essentially an unlimited amount of junior developers on demand,” Butler said. He was describing AI systems metaphorically, not literal employees. His point was that one experienced developer can now ask AI tools to produce code or other technical work that might previously have been assigned to more junior workers. That raises a broader question for universities and employers. If some of the simpler work traditionally given to newcomers can now be done by machines, how do people gain the experience needed to become senior workers themselves? Students doing work that once required years of programming Butler said he is already seeing the change inside his classroom. He created a Bishop’s course called CS208, Coding in Plain English, to show students — including those without traditional programming backgrounds — what they can accomplish using AI. Some come from disciplines such as psychology or neuroscience with no previous programming experience. “What I’m finding is that students who have zero programming experience, they come in from another discipline like psychology or neuroscience or something, they are now able to get up and running with real data sets,” Butler said. Butler’s own doctoral work involved neuroimaging, and he said he has assigned students work he considers comparable to the kinds of analysis he performed during his PhD. He described giving students a real dataset, an expected result and instructions to use AI to complete the analysis. Butler said those students have been able to carry out work at a level he associates with tasks he once performed after years of programming experience. That does not mean a student using AI instantly acquires the same knowledge as an experienced computer scientist. But Butler sees it as evidence that AI can dramatically lower the technical barrier between having a problem to solve and producing a working result. The role of the person using the system then changes. They need to know what to ask for, understand enough about the subject to judge the answer and take responsibility for what is ultimately produced. What about AI hallucinations? One persistent concern surrounding generative AI is hallucination — when a system produces information that sounds convincing but is false or unsupported. Butler said that problem has improved substantially in newer systems and is not as severe as it was with earlier models. He pointed in particular to newer AI systems’ ability to search the web, consult scientific databases and return source links rather than simply generating a citation from their internal model. Butler nevertheless said users should verify what AI produces. “You should verify,” he said while discussing citations generated with AI. His position is that hallucinations have become less common in the systems he uses, not that incorrect AI output is impossible. Human checking remains part of the process. Hours of work compressed Butler offered another example from his administrative work at Bishop’s. The university has been comparing CEGEP courses with first-year Bishop’s courses to determine where students may qualify for advanced standing. Traditionally, Butler said, that means reviewing two sets of course descriptions and manually matching one institution’s courses with another’s. As department chair, that could require hours of reading and comparison. He said AI can now be given both sets of material and asked to generate an initial mapping automatically. “It saves me hours and hours of work,” Butler said. Butler said the AI-generated mapping can also produce a better result than he would produce himself. He sees similar opportunities in businesses. A company may receive specifications, drawings, emails or other digital material from customers and then have employees convert that information into an internal format before anything can be manufactured or delivered. AI can increasingly perform parts of that intermediate processing. In Butler’s view, the employee does not necessarily disappear. Instead, the job becomes more about checking the result. “The human is still there,” he said. Judgement could become more valuable That change is central to Butler’s view of where digital work may be headed. If AI can produce a first draft, write basic code, compare documents or process large amounts of information, he argues that knowledge and judgement become increasingly important. “The real scarce resource going forward is going to be domain knowledge, expertise, and… credentials, authority, the ability to work with other people,” Butler said. He is therefore encouraging students not only to learn AI tools but also to broaden their education. He mentioned acting, fine art and photography as examples of courses that can help develop what he described as taste and intuition — the ability to recognize what is good, what is not and what should be changed. “And that’s the skill that they need now because the grunt work has been automated and now it’s about evaluating what the AI produces and telling it how to improve or expand the output,” Butler said. That does not remove the need for technical knowledge. Butler’s argument is that the emphasis may shift away from manually completing every step of a task and toward directing, checking and improving work produced with AI assistance. He also stressed that humans remain responsible for final decisions. “At the end of the day, the human has to make the final call,” Butler said, pointing to the question of accountability. Physical work may be different Butler draws a distinction between digital work and jobs requiring people to manipulate the physical world. He expects AI to continue advancing quickly in tasks performed almost entirely on computers. He is more cautious about claims that humanoid robots will soon be able to replace workers such as plumbers or electricians. Butler said those trades would not be replaced “anytime soon” in his view and described some current robotics demonstrations as overhyped. He described the situation as counterintuitive. “It’s almost like we solved the highest level first,” he said, contrasting advances in digital AI with the harder problem of building robots capable of operating reliably in the physical world. Butler’s argument is that some digital occupations could face automation sooner than trades requiring complex physical work. The wider AI shift in the Townships Butler’s comments come as local institutions are increasingly grappling with how AI should be used. The federal government recently announced up to $162 million over five years for 10,000 AI-related placements through Mitacs. The Université de Sherbrooke told The Pulse that the number of its collaborative research and innovation projects supported through Mitacs has approximately doubled since 2018-19, while the number of placements has approximately tripled. UdeS also said it already has projects involving both AI adoption and the application of AI to other fields. At Bishop’s, Butler said part of his role involves building the Computer Science department’s local presence, connecting students with regional partners and strengthening relationships with the Sherbrooke technology ecosystem. Those developments put universities in a difficult position. They have to prepare students to use the tools employers increasingly have available while also making sure graduates understand enough to recognize when those tools are wrong, incomplete or being applied to the wrong problem. The risk of losing human skills Butler does not see AI as risk-free. Later in the interview, he raised a separate concern: as AI becomes better at reading, writing, programming and other cognitive tasks, people could lose some of the underlying skills that historically helped produce new ideas. “The other danger is that we’re going to lose the human skills,” Butler said. He specifically mentioned reading and writing and argued that people could lose some of the lower-level understanding that contributes to breakthroughs. Butler said AI systems are based on existing human knowledge and argued that they become much more powerful when paired with a capable person. That tension runs through his view of the technology. AI can remove hours of routine work. It can allow beginners to perform tasks that once required substantial technical training. It can give experienced workers significant leverage. But the more capable the technology becomes, the more important it may be for people to develop the judgement needed to decide what should be done in the first place. For Butler, that is where education may have to change. Students still need to understand their field. They still need to know when something is wrong. And they still need to be able to make the final decision. But if AI increasingly handles the bottom of the cognitive pyramid, the value of a worker may depend less on how quickly they can perform the grunt work and more on whether they understand what the work is supposed to accomplish. Don’t miss the next story that affects your community. Join thousands of readers getting The Pulse every morning—plus breaking news alerts when it matters most. If you value this kind of local journalism, consider supporting it. Subscribe, share and like! Subscribe Share
Double-digit health insurance increases will hit individual and small group plans in 2027, again
Hundreds of thousands of Minnesotans are facing significantly more expensive health insurance next year.
Double-digit health insurance increases will hit individual and small group plans in 2027, again
Hundreds of thousands of Minnesotans are facing significantly more expensive health insurance next year.
Ochsner Health doubles the number of operating rooms at Ochsner Medical Complex
Patients across the Baton Rouge region now have greater access to specialized surgical care closer to home following an expansion of the surgical center at Ochsner Medical Complex - The Grove.
Double-digit health insurance increases will hit individual and small group plans in 2027, again
Hundreds of thousands of Minnesotans are facing significantly more expensive health insurance next year. The average increase for individual and small group insurance plans is 17% for 2027, the state’s Department of Commerce announced Thursday, raising costs for the 203,000 and 184,000 Minnesotans covered by individual and small group plans respectively. Individuals and their families […]
FEAR IS BIGGER THAN EVER… AND ZERO LATENCY VR HAS THE SCIENCE TO PROVE IT
/PRNewswire/ -- Zero Latency VR, the world's largest and most innovative immersive VR network, is celebrating a double Halloween anniversary: three years since...
Inseego completes acquisition of Nokia’s Fixed Wireless Access business
Transaction expected to approximately double Inseego’s revenue and expand its global footprint across Europe, the Middle East, Asia, Oceania, and the Americas
Pennsylvania confirms fifth measles-associated death as US outbreak grows
Cases have more than doubled since August as a dispute with federal health officials over the death count continues.
Solo Noi. A Double-winning season
From the Scudetto to the Coppa Italia, the incredible story of the 2025/26 season comes to life in a special film. Solo Noi. A Double-winning season is an Inter Media House production offering an excl...
Detroit Lions Catch Massive DOUBLE BREAK vs. Panthers
The Carolina Panthers placed Jaycee Horn and Mike Jackson Jr. on injured reserve ahead of Sunday's Week 4 matchup against the Detroit Lions.
US troops leave Iraq and Syria, but double down in the region
Why 30 September should be understood less as a US exit from the Middle East than as the end of a particular model of American intervention
Bickley double helps Jersey Bulls draw at Egham Town
Ten-man Jersey Bulls come back from 3-1 down to draw 3-3 at Egham Town in an exciting Isthmian League South Central clash.
Double Success for ISTA at the Lower Austrian Science Awards
3D-printed thermoelectric materials and expansion microscopy of brain tissue—these are the contributions that earned two researchers from the Institute of Science and Technology Austria (ISTA) distinctions at the Lower Austrian Science Awards. Maria Ibáñez and Johann Danzl accepted their awards at a
AMC (AMC) Stock Looks Fully Priced After Its Debt Refinancing Plan
AMC Entertainment Holdings has more than doubled year to date, which puts a spotlight on a simple question for you as a shareholder or watcher: do the cash flows from this cinema business support where the stock now trades? With the share price up 104.3% year to date, a lot now hinges on whether the market is putting too much or too little weight on AMC Entertainment’s future cash generation. The planned US$3.97b debt refinancing can reshape interest costs and repayment schedules, which may...
Princeton Equity Group secures $1.3 billion to fund franchise business
With $1.3 billion in commitments, Princeton Equity Group secured more than double the $575 million raised for its predecessor fund.
Broadcast To Hit A Double, Peacock Going Deep In NBC Sports Coverage Of MLB Wild Card Playoffs
Sports fans of a certain age can readily recall NBC’s coverage of the Major League Baseball playoffs regularly pre-empting the network’s “Must-See TV” primetime lineup in the 1990s. While today’s ratings and programming landscape has changed dramatically in the intervening decades, this year’s playoffs (starting Tuesday) are shaping up as a back-to-the-future milestone for NBC …
The McGraw sisters bring double the trouble
The cast and crew celebrate the film’s Los Angeles premiere at the Warner Bros. Studios lot
Call of Duty: Modern Warfare 4 Is Finally Making Double XP Tokens Only Active During Matches
Call of Duty: Modern Warfare 4 is making a major quality of life change that fans have been wanting to see for years.
Suns Owner Defends Phoenix's Decision To Trade for Miles Bridges
Addressing the moral fallout and roster fit, the Suns governor doubles down on the polarizing trade as Phoenix balances championship aspirations against intense public scrutiny and future contract risks.
John Cusack sets the record straight on longtime rumor he turned down starring in ‘Breaking Bad’ as Walter White
A rumor has long persisted that John Cusack passed on playing Walter White on ‘Breaking Bad,’ and the ‘Say Anything’ actor admits he had to double-check if that was the case.
U.S. Bank Launches New Credit Cards for Small Business Owners with Jessica Alba as Spokesperson
MINNEAPOLIS, September 28, 2026--U.S. Bank doubles down on its commitment to support small business owners with the launch of its U.S. Bank Business EssentialsTM Visa® Card and U.S. Bank Business EssentialsTM Plus Visa Signature® Card. The cards are designed for small business owners looking for straight-forward rewards on their everyday business purchases. Both offer unlimited 2% cash back on eligible purchases, plus the ability to earn higher cash back when paired with qualifying balances in a
AP Top 25: After Week 4
A couple teams had double digit place changes in this week’s poll.
Ex-boss Mancini says City charges 'not my concern'
Roberto Mancini says questions about his contract during his time as Manchester City manager were the club's "issue, not mine", after they were reportedly found guilty of all but one of 115 Premier League charges for breaching financial regulations. "Manchester City has not been found guilty, and the alleged double contract is not my concern.
Why This Regeneron Rival Just Skyrocketed 90%
Kodiak Sciences stock skyrocketed Monday on a double win for its potential rivals to Regeneron Pharmaceuticals' Eylea.
General contractor more than doubles Valley office space
Alston Construction doubles its Phoenix office space to 10,000 square feet in Tempe as major Arizona general contractors expand operations.
Activist Jana pushes Fiserv to accelerate cost cuts and tap Palantir
Activist investor Jana Partners is urging Fiserv to more than double its planned cost cuts and use software firm Palantir's products to speed up its own technology transformation program, according to a letter sent to the payments company that was viewed by Reuters.
Video: Mancini responds to allegations of double Man City contract
Roberto Mancini’s Manchester City contract is among the 115 possible breaches of Premier League financial rules, but the Italy national team coach insists that ‘it’s not an issue that concerns m...
England suffer double injury scare ahead of Czechia clash
Nico O’Reilly and Ezri Konsa are doubts for England’s UEFA Nations League clash against Czechia at Fortuna Arena on Tuesday evening.O’Reilly and Konsa missed group training on Monday morning, wi...
The Healthcare Workforce Gap Is Set to Nearly Double by 2040
CHICAGO--(BUSINESS WIRE)--Sep 28, 2026--
Haredi anti-draft march in Bnei Brak doubled as launch event for a protest political party
"In Netanyahu's Government of Evasion, the deserters are the heroes," Gadi Eisenkot claimed, dubbing the march "Netanyahu's walk of shame."
State officials approve 14.6% rate increase for individual premiums on ACA marketplace
Marylanders who purchase individual health care plans on the state’s insurance marketplace will see a second year of double-digit increases to their monthly healthcare costs.
'Gaming pays me double what I earned as a teacher'
Jarvs Tasker says it would have taken her 20 years as a teacher to make what she earns now.
Maryland officials approve 14.6% rate increase for individual premiums on ACA marketplace
Marylanders who purchase individual health care plans on the state’s insurance marketplace will see a second year of double-digit increases to their monthly healthcare costs.
Justin Verlander’s Final Start Has an Incredible Full-Circle Twist
Justin Verlander’s final start comes against Pirates manager Don Kelly, who was his teammate when he made his Double-A debut in 2005.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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State officials approve 14.6% rate increase for individual premiums on ACA marketplace
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Yankees change roster for doubleheader; Red Sox showdown finally official
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Double Your Impact! Support First-Generation Scholars in the Profession -
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Pioneer of China NewCo model sued in US over trade secret misuse, double-dealing
A legal feud unfolding in New York is putting a spotlight on the work of a business development veteran who is credited for pioneering one of biopharma’s hottest dealmaking mechanism: the China “NewCo” model. In a lawsuit originally filed in New York state court and recently moved to federal court, China’s Lepu Medical Technology has alleged that biopharma business development consultant Su Zhang, who was hired to help shop its GLP-1 weight-loss candidates to Western partners, engaged in corporate double-dealing and trade secret leaks. According to the complaint, while acting as Lepu’s primary dealmaking liaison for a group of obesity and metabolic disease drug candidates, Zhang was secretly double-dipping as the acting chief business officer for a direct competitor, BrightGene Pharmaceutical. “She never adequately disclosed the role, never sought Lepu’s consent, and never proposed any safeguard,” Lepu alleged in its complaint, which was filed in July after Zhang’s consulting firm, CoDevCo, sought certain transaction-based success fees from its angry customer through an arbitration process in Singapore. Lepu, the parent company of Lepu Biopharma, has asked Zhang to pay back its $500,000 retainer and disgorge all benefits she received during the alleged breaches of fiduciary duty, plus other damages and relief. The company has also requested the court grant injunctions to protect Lepu’s trade secrets. The ill-fated partnership officially kicked off in December 2024, when Lepu tapped CoDevCo as its “exclusive business development mechanism” to identify collaborators for the company’s drug candidates. According to Lepu’s complaint, Zhang personally negotiated and signed the agreement as managing director for CoDevCo, which used her home address. Before the Lepu deal, Zhang made a name following a short stint as the global head of business development for Hengrui Pharmaceuticals. It was during her tenure that Hengrui signed a landmark deal granting exclusive rights for a portfolio of GLP-1 assets to Hercules, which was at that time newly established by a group of private equity and venture capital firms. In addition to the regular upfront and milestone payments, Hengrui also gained an equity stake in Hercules, which later became Kailera Therapeutics. The Hengrui-Hercules deal opened a new paradigm, where a Chinese biopharma company spins off certain early-stage assets to investors for further development through the creation of a new company abroad. The “NewCo” model quickly came into vogue as it allows Western investors to access high-potential assets originating from China at an early stage while giving the Chinese licensors an opportunity to reap long-term benefits through equity stakes in the new firms. The NewCo model proved its value when Kailera staged a record-breaking $625 million IPO on Nasdaq this April, merely two years into the Hengrui deal. Related Kailera CEO 'knew we were in a good spot' before obesity biotech's record-breaking $625M IPO On her LinkedIn page, Zhang described her work at Hengrui as “[b]uilding team and capability from the ground up,” forming NewCo and major pharma partnerships worth billions of dollars. Lepu clearly wanted that kind of track record to help boost its own cardiometabolic portfolio, which includes a range of assets for obesity, Type 2 diabetes, fatty liver disease and muscle preservation during weight loss treatment. “Lepu’s pipeline is very valuable, but only if Lepu could secure the right international partner to expand into the overseas market during the available commercial window,” the company argued in its complaint. The Chinese biotech said it had little knowledge of U.S. laws, customs or business practices in the business development field, and therefore “needed to rely entirely” on the expertise of Zhang and her team as the firm’s first engagement of a U.S.-based BD consultant. “Zhang’s dominating influence on the business development strategy is further evidenced by the fact that she personally controlled the business-development communications on behalf of Lepu with potential partners,” Lepu said in its complaint. After entering the deal, Zhang introduced Lepu to her four associates. According to Lepu’s version of events, all of them were allegedly employed at different time points to perform similar jobs at other Chinese companies that Lepu described as its competitors, while having access to Lepu’s confidential information. As such, Lepu described Zhang’s team as “a roster of individuals whose primary professional loyalty, by virtue of their concurrent full-time employment, ran to Lepu’s competitors.” As well as the specific examples set out in the case, a look at Lepu’s deals over the period suggests Zhang may have been involved in at least one transaction. During their partnership, Lepu, through its subsidiary Shanghai Minwei Biotechnology, also out-licensed its GLP-1/GIP/FGF21 agonist MWN105 to a NewCo called Sidera Bio in the fall of 2025. The deal included an upfront and near-term payment of $35 million, up to $1.01 billion in milestones, and a 9.99% stake in the Danish startup. It seems likely that Zhang facilitated the Minwei deal given that Lepu is on record as having used CoDevCo as its “exclusive business development mechanism.” The big shock for Lepu came in the form of a news article on June 25, 2025. The article, reporting on phase 2 data for BrightGene’s GLP-1/GIP receptor agonist BGM0504, identified Zhang as acting chief business officer of the Lepu rival. Blindsided by her association with BrightGene, Lepu confronted Zhang in July 2025. “Lepu was given assurances that there was nothing to be concerned about and told that Zhang would explain the matter to Lepu,” Lepu alleged in its complaint. “Zhang never did.” Lepu claimed that Zhang had the motive and opportunity to steer potential prospective partners toward BrightGene or other competitors. Later, in February 2026, one of Zhang’s associates joined BrightGene as the vice president for global business development, according to the complaint. Around the same time, Lepu sent written demand letters asking Zhang to account for her BrightGene role, identify what confidential data were shared with the rival firm, and provide any conflict-of-interest or firewall policies during the engagement. According to Lepu, neither CoDevCo nor Zhang answered the questions in their responses. Related Novo vs. KBP: How a $1.3B deal turned into a fraud accusation and an international legal fight In a motion to dismiss filed with the U.S. District Court in the Eastern District of New York on Sept. 4, Zhang’s legal team argued that Lepu’s agreement was signed with CoDevCo, and that an employee of the contractor does not owe fiduciary duties to the client. In its complaint, Lepu said: “That CoDevCo was the contracting entity does not insulate Zhang from personal liability for duties she personally undertook and personally breached.” Taking the argument one step further, the defending party argued that the consulting agreement “does not create a fiduciary relationship even between CoDevCo and Lepu; instead, it identifies CoDevCo as an independent contractor retained to market Lepu’s business to potential western partners.” Although CoDevCo was Lepu’s exclusive business-development contractor, there were no terms stipulating that the consulting firm should serve only Lepu, Zhang’s lawyer noted. As to Lepu’s claims that Zhang misappropriated trade secrets, the defendant argued that Lepu authorized the use of the information so Zhang’s team could perform their service per the agreement. In a rebuttal filed on Sept. 11, Lepu’s lawyer set out why they believe the Chinese biotech satisfied New York law’s misappropriation definition by alleging that the defendant used a trade secret “in breach of a duty or through improper means.” As an alternative to dismissing the suit, the defendant suggested the action should be stayed pending outcomes from the arbitration of a separate case in Singapore. While NewCo pioneer Zhang is defending her business arrangements, momentum behind the NewCo trend has continued unabated into 2026. Through August, Chinese biotech assets have spurred 15 NewCo deals this year, according to local trade publication PharmaDJ.
Yankees news: Let’s play two
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Health Care Partnership outlines workforce progress
More local nursing graduates are staying in the region, according to officials offering an update on the progress of the New Hanover Healthcare Career Partnership at a public forum last night. According to Jack Watson, dean of UNCW’s College of Health & Human Services, the number of UNCW nursing graduates choosing to remain in the area after graduation has climbed from 27% to the mid-40% range. The New Hanover Healthcare Career Partnership aims to address the region’s healthcare worker shortage, with a key focus on nursing through strategic partnerships between UNCW, Cape Fear Community College (CFCC), New Hanover County Schools and the Wilmington Chamber of Commerce Foundation. "Each of the partners had pathway programs,” said Watson, “but they were almost at times done in a silo." One of the New Hanover Community Endowment's largest commitments to date, the collaborative received a $22.3 million grant in 2023, to be disbursed over three years, beginning in 2024. At the public forum, leadership addressed the nursing bottleneck created by the pandemic, and Laurie Whalin, president of the Novant Health Coastal Region, acknowledged that Novant Health had relied heavily on travel nurses during that period, with travel nurses making up about 47% of staff and nursing turnover at 35% at the height of the pandemic. "I can say we are in a tremendously different place today,” Whalin said at the forum. The number of travel nurses employed by the Novant Health Coastal Region has dropped to around 100 today, which Whalin says accounts for less than 4% of the workforce. Roughly two years into the grant term, major stakeholders in the collaboration pointed to various accomplishments tied to the initiative. According to Stephen Hill, vice president of talent development with the Greater Wilmington Chamber of Commerce, 250 more nurses live in New Hanover County in 2026 than in 2023. Whalin added that between 2021 and 2025, the Novant Health Coastal Region has hired close to 1,200 registered nurses. Additionally, according to Whalin, over the past two years, hiring and retention of nursing graduates from UNCW increased by 103%, while hiring and retention of nursing graduates from CFCC increased by 70%. Mandy Mills, director of career & technical education at New Hanover County Schools, pointed to the launch of its first Health Sciences Academy program, established across the county's four traditional high schools (Hoggard High School, Laney High School, Ashley High School and New Hanover High School), which started with 38 students last year. Mills also pointed to growth in the district’s Nursing Fundamentals course, which grew from 10 seats in 2023 to 50 in 2025-2026 and is now offered at all four traditional high schools. Watson emphasized the growing nursing class sizes and offered an update on the school’s accelerated nursing degree, which launched last year. Eleven students graduated in the first class, and all passed their boards on the first try, Watson said. This year’s class has 24 students. When the endowment announced its $22.3 million grant for the collaborative in 2023, UNCW and CFCC were each slated to receive the bulk of the funds, at about $10 million each. UNCW’s plans for the grant money included expanding its simulation lab, Watson said. He added that construction is expected to begin on the simulation lab this year and will likely extend through next year. According to Mary Ellen Naylor, dean of Health & Human Services at CFCC, the college has experienced growth in its associate degree nursing retention, rising from 59% in 2023 to 76% for the May 2026 class. CFCC used part of its endowment funding to support wraparound services, including a housing stipend, tuition assistance, exam assistance, emergency assistance, drop-in daycare and clinical and educational supplies. "We have very strong … students, but once they get into the program, there are competing priorities,” Naylor said. “They are working multiple jobs. They have children. They're single parents." According to Naylor, in 2026, 94% of students who used support services are still enrolled or have graduated. Addressing a question from an audience member about an approaching “enrollment cliff,” driven largely by dropping birth rates, Watson and Naylor said demand remains strong at both schools. “Right now … we do have more applicants than we have spots in our nursing program, and it is still a competitive process to get into,” Watson said. “I do not foresee that changing.” "(We've) doubled enrollment in our nursing programs over the last few years, but just as Dean Watson said, we still have very robust applicant pools, so it is still very competitive to get in,” Naylor said. "We have the applicant pool to support that, but again, it's not as easy as just saying, 'Okay … we're going to take another 90 students.' It's making sure all the resources and infrastructure that we need to educate the students outside the classroom is there as well." In response to a question about applying the collaborative model to other healthcare positions besides nursing, Sophie Dagenais, CEO and president of the endowment, said she sees the potential for the model to expand to other healthcare jobs and even other industries, but that the endowment hopes to learn from this model first. “This is a grant that is in year two of three years, and first we wanted to learn what is this going to demonstrate, what will we learn and then how may we scale it possibly,” she said. According to endowment spokesperson Amber Rogerson, funds for the program are set to expire after June 2027. “It's too early to discuss what happens after that,” wrote Rogerson in an email, “though we know the partners are considering the future, and some of the work supported by the grants is now built into their regular operations.”
Health Care Partnership outlines workforce progress
More local nursing graduates are staying in the region, according to officials offering an update on the progress of the New Hanover Healthcare Career Partnership at a public forum last night. According to Jack Watson, dean of UNCW’s College of Health & Human Services, the number of UNCW nursing graduates choosing to remain in the area after graduation has climbed from 27% to the mid-40% range. The New Hanover Healthcare Career Partnership aims to address the region’s healthcare worker shortage, with a key focus on nursing through strategic partnerships between UNCW, Cape Fear Community College (CFCC), New Hanover County Schools and the Wilmington Chamber of Commerce Foundation. "Each of the partners had pathway programs,” said Watson, “but they were almost at times done in a silo." One of the New Hanover Community Endowment's largest commitments to date, the collaborative received a $22.3 million grant in 2023, to be disbursed over three years, beginning in 2024. At the public forum, leadership addressed the nursing bottleneck created by the pandemic, and Laurie Whalin, president of the Novant Health Coastal Region, acknowledged that Novant Health had relied heavily on travel nurses during that period, with travel nurses making up about 47% of staff and nursing turnover at 35% at the height of the pandemic. "I can say we are in a tremendously different place today,” Whalin said at the forum. The number of travel nurses employed by the Novant Health Coastal Region has dropped to around 100 today, which Whalin says accounts for less than 4% of the workforce. Roughly two years into the grant term, major stakeholders in the collaboration pointed to various accomplishments tied to the initiative. According to Stephen Hill, vice president of talent development with the Greater Wilmington Chamber of Commerce, 250 more nurses live in New Hanover County in 2026 than in 2023. Whalin added that between 2021 and 2025, the Novant Health Coastal Region has hired close to 1,200 registered nurses. Additionally, according to Whalin, over the past two years, hiring and retention of nursing graduates from UNCW increased by 103%, while hiring and retention of nursing graduates from CFCC increased by 70%. Mandy Mills, director of career & technical education at New Hanover County Schools, pointed to the launch of its first Health Sciences Academy program, established across the county's four traditional high schools (Hoggard High School, Laney High School, Ashley High School and New Hanover High School), which started with 38 students last year. Mills also pointed to growth in the district’s Nursing Fundamentals course, which grew from 10 seats in 2023 to 50 in 2025-2026 and is now offered at all four traditional high schools. Watson emphasized the growing nursing class sizes and offered an update on the school’s accelerated nursing degree, which launched last year. Eleven students graduated in the first class, and all passed their boards on the first try, Watson said. This year’s class has 24 students. When the endowment announced its $22.3 million grant for the collaborative in 2023, UNCW and CFCC were each slated to receive the bulk of the funds, at about $10 million each. UNCW’s plans for the grant money included expanding its simulation lab, Watson said. He added that construction is expected to begin on the simulation lab this year and will likely extend through next year. According to Mary Ellen Naylor, dean of Health & Human Services at CFCC, the college has experienced growth in its associate degree nursing retention, rising from 59% in 2023 to 76% for the May 2026 class. CFCC used part of its endowment funding to support wraparound services, including a housing stipend, tuition assistance, exam assistance, emergency assistance, drop-in daycare and clinical and educational supplies. "We have very strong … students, but once they get into the program, there are competing priorities,” Naylor said. “They are working multiple jobs. They have children. They're single parents." According to Naylor, in 2026, 94% of students who used support services are still enrolled or have graduated. Addressing a question from an audience member about an approaching “enrollment cliff,” driven largely by dropping birth rates, Watson and Naylor said demand remains strong at both schools. “Right now … we do have more applicants than we have spots in our nursing program, and it is still a competitive process to get into,” Watson said. “I do not foresee that changing.” "(We've) doubled enrollment in our nursing programs over the last few years, but just as Dean Watson said, we still have very robust applicant pools, so it is still very competitive to get in,” Naylor said. "We have the applicant pool to support that, but again, it's not as easy as just saying, 'Okay … we're going to take another 90 students.' It's making sure all the resources and infrastructure that we need to educate the students outside the classroom is there as well." In response to a question about applying the collaborative model to other healthcare positions besides nursing, Sophie Dagenais, CEO and president of the endowment, said she sees the potential for the model to expand to other healthcare jobs and even other industries, but that the endowment hopes to learn from this model first. “This is a grant that is in year two of three years, and first we wanted to learn what is this going to demonstrate, what will we learn and then how may we scale it possibly,” she said. According to endowment spokesperson Amber Rogerson, funds for the program are set to expire after June 2027. “It's too early to discuss what happens after that,” wrote Rogerson in an email, “though we know the partners are considering the future, and some of the work supported by the grants is now built into their regular operations.”
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The administration plans to double down on its contention that it has the right to decide who can step foot in the White House
Trump administration to defend its ban of three news outlets in court hearing
The administration plans to double down on its contention that it has the right to decide who can step foot in the White House
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"The Marissa Mitchell Show" is a live news and lifestyle program with the goal to inform, inspire, and entertain through discussions about a variety of topics, ranging from current events and relationships, to finances, parenting, wellness, and more.
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Is 50 the new 60?
Subscribe TL;DR: Younger generations are showing signs of worse health compared to earlier-born cohorts at the same age This backward “drift” is showing up both in mortality risk and chronic disease Worsening trends in obesity and diabetes are the most consistent signals Taking the long view, we’ve made astonishing gains in health and life expectancy in the last century. Global average life expectancy has more than doubled from 32 years in 1900 to 73 years in 2024. (But don’t forget, there were still old people when life expectancy was 32). As people lived longer, they also generally lived healthier along the way. It turns out that avoiding things that can kill you early, like malnutrition and lots of childhood infections, also keeps you healthier later in life. In a classic 2004 paper, Finch and Crimmins proposed that cohorts of children who benefited from fewer early life infections had less lifetime exposure to inflammation and cardiovascular disease later in life, accelerating mortality improvements at older ages. Poor nutrition in the womb has also been linked to a higher risk of later chronic disease. The upshot is that improvements in childhood health can pay dividends many decades later. The combination of better living conditions (nutrition, sanitation) and medical advances (antibiotics, vaccines, blood pressure meds, etc) meant that people’s healthy lifespan generally expanded, even as they lived longer. Aging researchers call this best-case scenario “compression of morbidity”—meaning we delay the onset of disease and disability even faster than the years of life we are adding. During my 20+ year research career, we could generally bank on the idea that younger generations would not only live longer but also keep getting healthier along the way. “60 is the new 50” as they say… Enter “Generational Health Drift” Sadly, this expectation of steady progress may be changing. You’ve probably heard that US life expectancy gains have slowed to a crawl in the past couple of decades. Mortality improvements are also slowing (though less dramatically) in many other high-income countries (you can read more about that in a review paper I wrote here). Mortality is a very blunt health measure, but it is often a good barometer for the broader population health trends happening underneath. And we are now seeing that younger generations may be in worse health at similar ages compared to earlier born cohorts. My collaborator Prof. George Ploubidis at University College London coined this worsening health in more recently born cohorts “generational health drift.” “Generational health drift” is bad news on multiple fronts. Most obviously, we don’t want our health progress to go backward. But the timing is also bad, since our populations are aging. In demographic terms, “population aging” means that the proportion of the population at older ages (i.e >65 years) is increasing. Fun demography fact: Current population aging is not due to the recent declines in the birth rates making the news, but declines in fertility decades ago, after the “baby boom.” As baby boomers reach older ages, the smaller cohorts behind them mean the percentage of older adults will increase. For example, the share of the population age 65 and older in the US increased from 12.4% in 2004 to 18.0% in 2024. This story of population aging was written long ago. Many worry that population aging will put pressure on health care and pension systems. But if people reach older ages in better health than in years past, those fiscal pressures would be less dire than projected. Healthy older people can also continue to contribute to society in many valuable ways, including paid work, caregiving, community service….even high political office 🤷. On the flip side, if younger generations reach retirement age in worse health and with more disabling conditions, this could magnify the societal challenge of population aging. Evidence for worsening generational health A recent paper that I LOVED in the Proceedings of the National Academy of Sciences by Dr. Leah Abrams and colleagues examined which birth cohorts (aka generations) were behind worsening US mortality. Behold the Lexis diagram (cue swooning demographers). Calendar time is on the x-axis, age on the y-axis. Birth cohorts can be followed over time as they age on the diagonal lines moving up and to the right. This figure plots the year-on-year % change in all-cause mortality at a given age. Green shading indicates mortality improvements over time, white is stagnation, and gray shading indicates worsening mortality. Following the diagonal line for those born in 1950, you can see a noticeable shift from green to gray that follows this cohort for most of their lives. This gray shading shows generally worsening mortality for the 1950 to 1959 birth cohorts compared to their predecessors across all ages. Concerningly for my GenX and elder millennial peeps, there was also a deterioration in mortality for birth cohorts born in the 1970s and 1980s, visible as dark gray areas at ages 30 to 45 during the 2010s. While some of these mortality changes reflect specific shocks such as the opioid epidemic, most deaths still occur from major causes of death such as cardiovascular disease and cancer. For cancer, the gray in the top left corner of the figure below reflects the legacies of smoking for older cohorts, followed by a period of green with improvements in cancer mortality as smoking rates declined. But the white/gray shading in the bottom right corner highlights a stagnation and reversal of the cancer trends, with cohorts born around 1970 to 1985 experiencing worsening cancer mortality. This deterioration was most noticeable for colon cancer mortality, possibly linked to obesity or dietary factors. Not just dying more, but less healthy along the way. A recent paper by Dr. Laura Gimeno of University College London (of which I am a co-author), found evidence that more recently born cohorts in Great Britain have stagnating or worsening health. A stylized picture of what“generational health drift” might look like: The review paper found: Rates of childhood overweight and obesity were highest among Gen Z. Rates of diabetes in the 40s almost doubled from 3.1% among the Baby Boomers to 5.9% in Generation X. Gen Z reported higher rates of poor mental health in adolescence compared to earlier-born groups. These UK results are consistent with studies showing worsening health across generations in the US as well. A 2021 US study found that more recently born cohorts had worse biological markers (like blood pressure and blood sugar) than earlier generations at the same age. A separate 2022 study of Americans aged 50 and over found that more recently born generations had a higher number of chronic diseases, with younger age of disease onset. A 2024 Lancet paper found that in the US, women born in 1945 had 33% obesity prevalence at age 50, rising to 48.2% for women born in 1970 turning 50. So what’s going on, and can we turn it around? We don’t have a definitive answer for what’s causing the deteriorating health of younger cohorts, but circumstantial evidence points to worsening trends in obesity and diabetes in both the US and UK. Remember that cohort trends reflect lagged effects of early environments, and younger generations have faced both earlier onset and more severe obesity across their lifetimes. Despite these very concerning trends, the future is not set in stone. We’ve reversed poor generational health trends before: drops in smoking are a major reason cancer and heart disease deaths fell so dramatically in recent decades. GLP-1 drugs may finally turn the tide against rising rates of obesity and diabetes, though it is still early days. But things could also get worse…for example from a return to higher levels of childhood infectious diseases that can have a lasting impact on health. See for example: [ ](https://jenndowd.substack.com/p/dont-you-forget-about-measles-the) [ Don’t You Forget About Me(asles): The Virus That Erases Immune Memory ](https://jenndowd.substack.com/p/dont-you-forget-about-measles-the) Jenn Dowd, PhD · March 24, 2025 [ Read full story ](https://jenndowd.substack.com/p/dont-you-forget-about-measles-the) Even as an optimist, emerging data on the “generational health drift” has my full attention. For most of my research career, we took it for granted that each generation would be healthier than the last. But if present trends continue, **50 could be the new 60….**and Gen Z celebrities will soon look older than Paul Rudd :). Stay well, Jenn Share the Health! If you found this post useful, please share it with a friend. Share
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