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Pellegrini favored to start in Como-Roma
Gian Piero Gasperini is ready to welcome back the remaining players who have been on international duty, preparing for the trip to Como, scheduled for Sunday at 12:30 PM. Mora, Castro, Soulé, and Bal...
Aspirus Health to offer flu vaccinations at multiple clinics starting this week
The organization says it has seen an uptick in people wanting to be vaccinated over the past few years.
Angus Taylor’s immigration plan misses the target – on politics and on policy
The most surprising aspect of the Coalition’s policy is that in six pages of detail there is not a single mention of the labour market
Bush-Wells Sporting Goods to close its doors at the end of the year
CASPER, Wyo. — After 63 years in business, Bush-Wells Sporting Goods will close at the end of this year. Changing business models in the industry,
Darius Wabbington commits to Indiana
Phoenix Sunnyslope High School star Darius Wabbington chose Indiana over a final group of suitors that included Arizona and Illinois.
ASU's Marcus Arroyo to return to play-calling role
Arroyo spent all of ASU's 2024 season and the 2025 regular season calling plays before Dillingham took over for the Sun Bowl.
Brazil: Lessons from a Disaster
By Antonio Martins (Outras Palavras) Defeats become deeper and more prolonged when we misunderstand what caused them, avoid correcting course, and embrace “solutions” that only compound our mistakes. Lula’s government and the Brazilian left suffered a disaster in Sunday’s election. Contrary to every poll, the president finished the first round 2.2 million votes behind Flávio Bolsonaro—and, more significantly, 3.4 million votes below his total four years ago, when the machinery of the state was working against him and in favor of his opponent. His vote share declined in 98 percent of Brazil’s municipalities. The PL, the main party of the far right, elected 121 deputies and 28 senators, becoming the largest caucus in both houses of Congress. The parties aligned with the Centrão—Brazil’s bloc of transactional center-right parties—were somewhat diminished, but will still hold roughly 250 seats in the Chamber of Deputies and 35 in the Senate. That will make it easier to assemble the majorities needed to amend the Constitution or impeach Supreme Federal Court justices. If elected, Flávio Bolsonaro could appoint four members of the Court, substantially altering its internal balance of power. What produced these results? How can the far right be prevented from consolidating them into a prolonged political hegemony? And what is the essential change of direction the left now needs? Explaining the Disaster Across the commercial media and the exuberant chaos of digital platforms, interpretations are multiplying. Some focus on specific episodes: Lula’s absence from the Globo debate, his very close relationship with Alexandre de Moraes, or his emphasis on issues supposedly remote from most people’s everyday concerns, such as rare earth minerals. Among the more systemic interpretations, three seem especially questionable. One argues that the principal defeat was not the left’s, since its congressional representation declined only slightly. The decisive movement captured at the ballot box, according to this view, was a shift within the right itself—from the more moderate and transactional forces of the Centrão toward the more ideological and radicalized forces of the PL and Novo. A second interpretation holds that the nature of electoral and political processes has changed. The material interests and aspirations of society, it argues, no longer play the central role they once did; they have given way to forms of subjective self-identification that the left has yet to understand. And a third concludes that, because of these two developments, we should expect a political winter: a prolonged period in which the far right and the broader right dominate Brazilian political life. There are important elements in all three interpretations. The problem lies in what they deny or leave out: Lula’s third government was a small-bore government. It offered the majorities that elected it neither a clearly better life nor reasons to believe again in politics and its power to transform society. These failures flowed from two fatal accommodations, which I will examine below. As a result, the government suffered a slow but steady erosion of support. And, as has happened in so many Western countries, it gave the far right the opportunity to present itself as anti-system and to benefit from popular frustration and distress. The interpretation that emphasizes the migration of votes from the center-right and traditional right toward the far right has been advanced, among others, by the courageous journalist Leonardo Sakamoto. In his UOL column on Monday, October 5, he highlights the miserable behavior of the traditional conservative parties. Over the past four years, they repeatedly joined forces with the “neo”-fascists, helping to “normalize” them—a criticism that could equally be directed at almost the entire corporate media. Believing they could use the far right as a stepping stone, they instead ended up partly devoured by it. This was especially true in the Senate, where the PL’s gain of 13 senators and Novo’s gain of two came at the expense of the PSD, which lost nine; the MDB, which lost two; the PSDB, which lost two; and the PP, which lost one. Sakamoto’s observation is accurate and necessary, but it leaves uncomfortable questions unanswered. Why did the erosion of the Centrão benefit the far right rather than, for example, producing growth for the left—as has happened so many times before, both in Brazil and elsewhere? The answer is not difficult. Throughout its four years in office, Lula’s third government was almost invariably associated with the Centrão. Here lies its first accommodation: accepting the limits imposed by conservative institutions; avoiding, as much as possible, any attempt to strain those limits through popular pressure; and believing only in the modest changes that could be squeezed through openings in Congress. The failure of the campaign to end the six-day workweek is emblematic. Lula could have electrified the presidential race by pairing it with a popular campaign for passage of the measure. Instead, he chose to place his hopes in the hands of Senate president Rodrigo Alcolumbre. He generated no mass mobilization, did not force his opponents onto an uncomfortable defensive, and won no victory. In September 2025, the government squandered the greatest of its many opportunities to shake up conservative power in Congress. Popular opposition to the so-called Shielding Amendment—which, if approved, would have restricted criminal proceedings against members of Congress—brought crowds into the streets, mobilized primarily by artists and social movements. This opened the possibility for a broader political education: a campaign that could begin exposing the limits and dysfunctions of Brazil’s political system while putting Bolsonaro’s movement on the defensive for its predictable support of political privilege. The amendment was defeated. But the executive branch then backed away from the fight. It remained associated with an institutional world widely seen as corrupt, elitist, and indifferent to ordinary people’s struggles. In doing so, it forfeited its credibility as a vehicle for the protest vote. On Sunday, it reaped the bitter fruits. Are We Doomed? Taking a different approach from Sakamoto, the philosopher Moysés Pinto Neto and other writers have drawn attention, in their first analyses of October 4, to the fragmentation of the public sphere produced by Big Tech platforms. Through their algorithms, these platforms present each person with a different view of social reality. As a consequence, it becomes much harder to identify common material problems and demands—for example, the fight for labor rights or for a properly funded public health system. Voters no longer embrace such demands, these authors argue, because they no longer see themselves as part of a collective. Instead, they tend to value the identities assigned to them by neoliberal subjectivity—the role of the entrepreneur, for example. On this interpretation, the left’s possible error lies in clinging to outdated illusions. Moysés’s warning is highly relevant and resonates with arguments such as Naomi Klein and Astra Taylor’s “Apocalyptic Fascism and the Billionaires’ Bet.” Unlike a century ago, the far right no longer promises a radiant future. It concentrates instead on resentment—especially that of young men. “They belong to a generation that fears it may never own a home, but compensates with the pleasure it gets from constantly provoking progressives online. Convinced their future has been stolen, they share memes romanticizing historical authoritarian regimes,” the authors write. But Moysés seems to confuse this danger with inevitability. He fails to see that the left’s answer cannot be adaptation. On the contrary, it must strengthen the possibility of politics as collective action. Nor does he recognize that precisely such a reversal is already becoming possible in some of the most promising mobilizations of the twenty-first century: the election, at the end of 2025, of the young Muslim Zohran Mamdani as mayor of New York, on a platform centered on the intensely material fight for an affordable city; the Left Party’s victory in Berlin two weeks ago, built around the demand to expropriate private real-estate corporations; and the very recent wave of demonstrations in Spain—including an occupation of Madrid’s Puerta del Sol—in which tens of thousands of young people mobilized by the Tenants’ Union have demanded limits on rents. By putting itself in the straitjacket of the “fiscal framework” in the first months of 2022, Lula’s third government adopted the second fatal accommodation of its term. Faced with conservative institutions and a country devastated by four years of Bolsonaro, increased public investment was the government’s remaining weapon for offering a more dignified life to the majority and forging an anti-conservative pact with them. The same state that disburses 1 trillion reais a year to enrich a small class of rentiers could instead spend money to extend the Family Health Strategy to every Brazilian, at a cost of 30 billion reais; provide full-day public schooling and childcare to all adolescents and children—and, especially, relief to their mothers; achieve universal sanitation while cleaning up polluted urban rivers; multiply metro systems; begin transforming the urban peripheries; and undertake many other urgently needed projects. In April 2023, an article in Outras Palavras warned that the fiscal framework could “shrink the Lula government and preserve the forces that condemn the country to inequality and regression.” A year later, another article showed that restraints on public spending were strangling policies vital to ordinary people and undermining the president’s popularity. In November 2024 came a reality check, in the form of the government’s humiliating defeat in the municipal elections. Even then, the fiscal lock was neither removed nor loosened. On the contrary: throughout the government’s four years, fiscal restraint remained central to its political narrative. The administration proudly proclaimed that it had “put the state’s accounts in order,” without grasping either how misleading that phrase was—given the payment of 1 trillion reais in interest—or how badly the message was hurting it politically. Lula finally woke up in September 2026. The increase in Bolsa Família benefits, after four years of being frozen; the announcement that anti-obesity drugs would be offered through Brazil’s public health system; and the ban on online betting showed that the state has the power to act decisively on behalf of the majority when those in government are willing to confront obstacles. The huge marches that closed the campaign in Fortaleza, Salvador, Rio de Janeiro, and São Paulo on the eve of October 4 showed how such initiatives can mobilize activists and the broader public. But it was too late—and too little to change the outcome of the first round. History has not ended The possibility of a turnaround in the three weeks leading up to November 25 cannot be ruled out. It will not be simple or easy. Lula must not only make up a deficit of 2.2 million votes; he must also offset the movement of voters who backed other right-wing candidates in the first round, most of whom are likely to move toward Flávio Bolsonaro. Pulling that off will require a broad, grassroots effort to win over voters, potentially reinforced by new initiatives from Lula. The coming hours and days will be decisive. If Bolsonaro’s movement also wins the presidency, the result will create a high-risk situation for Brazilian sovereignty and democracy. The enormous challenges posed by such an outcome would require the left to reexamine, in depth and with a genuine willingness to engage in self-criticism, its political projects—or its lack of them—and its practices. But would that mean we are condemned to the long winter of far-right hegemony that some analyses are beginning to forecast? It is far too early to say, suggests a recent text by Álvaro García Linera, the thinker who served as vice president of Bolivia under Evo Morales. His central hypothesis is that this political current will prove short-lived. At a moment when the entire world is once again talking about sovereignty and protecting national economies, the far right offers a stale, recolonizing neoliberalism. Its submission to the United States is as blatant and pathetic as Flávio and Eduardo Bolsonaro’s overtures to Donald Trump. Its project amounts to something like every man for himself: greater inequality, capitalism without limits, devastation, and supremacism. Will it work? In the United States, just two years into his second term, Trump himself is reaching record levels of unpopularity and may be on the verge of losing Republican control of both the House and Senate in November. Every new beginning is difficult. Whatever the outcome of the second round, the defeats of October 4 show how profoundly the Brazilian left will have to rethink and rebuild. But just as it would be foolish to underestimate the seriousness of its mistakes, it would be equally foolish to conclude that rebuilding a political project is no longer possible. History has not ended. The times are moving faster than ever. Originally published in Portuguese by Outras Palavras. English translation by Eric Blanc; I’ve added the subtitles. More We can’t stop the far right at home or abroad without a revitalized labor movement, which is yet another reason why you should become a sustaining supporter of the Emergency Workplace Organizing Committee (EWOC) — one of US labor’s pivotal bright spots. Relatedly, Jacobin published a short piece of mine reflecting on a decade of Bernie Sanders inspiring a whole new generation of young worker organizers.
NASA Balloon Campaign Concludes with Final Science Flight
The final mission of NASA’s fall balloon campaign successfully concluded, the reflight of the CORSAIR/WASP. The mission launched from the agency’s facility in
De Roon to start alongside Kone vs Como
Roma returns to training today ahead of the trip to Como, scheduled for Sunday at 12:30. Gian Piero Gasperini will gradually reunite all the players who have been on international duty in recent weeks...
Endrick shows interest in working with Gasperini
Roma are looking for a striker to boost their attacking capabilities in January. The Giallorossi made moves for Endrick in the summer, and a significant resurgence could be in the works in the coming ...
CSUN in D.C. Internship Expands Student’s Public Health Career Aspirations
For Josiah Morrow, a three-month internship in Washington, D.C., turned the nation’s capital into a classroom — and helped shape his future in healthcare.
Bladen Community College to host “So You Want to Start a Small Business” class and preview Pitch It Bladen 2027
The Small Business Center at Bladen Community College invites aspiring entrepreneurs to attend “So You Want to Start a Small Business” on Tuesday, Oct. 13, 2026, from 6:00 p.m. to 8:00 p.m. in Building 14, Room 104. This class will help participants explore what it takes to become an entrepreneur and take the first steps toward turning a business idea into reality.Participants will explore the entrepreneurial mindset and consider whether they have the interests, characteristics, motivation and willingness to take on the challenges of business ownership. The class will encourage attendees to examine their personal goals, expectations, strengths and readiness to pursue entrepreneurship.Attendees will also gain insight into the realities of starting and operating a small business, including the commitment, planning, decision-making and perseverance required to build a successful venture. Whether participants are just beginning to consider business ownership or already have an idea they want to pursue, this class will provide a foundation for determining their next steps.In addition to the class instruction, attendees will receive advance information about the upcoming Pitch It Bladen 2027 Business Competition, including the application form and details about the program. Individuals who are ready to move forward may submit their applications early and have the opportunity to receive advance acceptance into the program.Pitch It Bladen helps aspiring and emerging entrepreneurs develop their business ideas through structured instruction in business planning, financial management, cash-flow projections, marketing and operations. Participants work toward completing a business plan and preparing a business pitch, with the opportunity to compete for cash prizes.Last year's Pitch It Bladen program demonstrated the value of investing in local entrepreneurs by helping participants strengthen their business knowledge, develop their business plans and prepare to present their ideas. The competition showcased the creativity and potential of Bladen County's small-business community and provided participants with practical tools to move their business goals forward.Building on that success, Pitch It Bladen 2027 will provide another opportunity for local entrepreneurs to gain knowledge, build confidence and take meaningful steps toward launching or growing a business.“The Small Business Center wants to help individuals make informed decisions about entrepreneurship before they take the leap into business ownership,” said Theresa Dennison, Small Business Center director, in a press release. “This class gives participants an opportunity to evaluate whether entrepreneurship is right for them while also introducing them to Pitch It Bladen 2027 and the resources available to help them succeed.”Registration: Visit www.ncsbc.net and search for the class by name, or contact the Small Business Center at 910-879-5572 for additional information.
Some mental health providers hoping to serve Lane County's Oregon Health Plan members say they’re facing barriers
Aspire is one of a few healthcare providers in Lane County that told KLCC they want to – but haven’t been able to – get a contract with Lane County's Medicaid insurer Trillium. That’s left Aspire without access to its target population, and other providers considering scaling back their services.
Health Agency says now is the time to update raspatory virus Vaccinations
COLDWATER, MI (WTVB) - As fall arrives and respiratory virus season gets underway, the Branch-Hillsdale-St. Jo...
Confirmed: Roma reopen talks with Endrick’s entourage
Roma will continue to strengthen in January. Gian Piero Gasperini, even in the last transfer window, was left without a striker capable of sprinting and raising the team’s level. A promised addition...
3 Most Disappointing Cubs Players In 2026
From high-priced free agents to a botched blockbuster trade, these three struggling stars derailed Chicago's championship aspirations and fueled a premature postseason exit against the Padres.
Rare 1-in-100M ‘Ghost Lobster’ Will Be Put to Work Helping Scientists Crack Genetic Mystery
A ‘ghost’ lobster so rare that the odds of finding it are 1 in 100 million is going to school—a new home at Maine’s Marine Science Center.
Natrona County health and food inspections (9/25/26–10/1/26)
CASPER, Wyo. — The Casper-Natrona County Health Department inspects restaurants, grocery stores, convenience stores, mobile food units, commissaries and
Roma continue to follow Kvernadze ahead of January
Roma are already looking ahead to the January transfer window, and their priority would be to give Gasperini a new attacking winger. As La Stampa reports today, the Giallorossi coach is dreaming of a ...
Miralem Pjanic: “I hope Roma win the Scudetto.”
Gasperini’s Roma wins and impresses, by now, virtually everyone from insiders to former players. The Giallorossi play brilliantly and at breakneck speed, making for a truly spectacular spectacle. Mi...
ASU overwhelmed by Baylor's physicality in blowout loss
ASU entered the game 15th nationally in total yards allowed in first halves (121.3), and the Bears hung 299 yards on the Sun Devils in the first 30 minutes.
Red Wings C Marco Kasper Suffers Injury
Marco Kasper will miss Sunday's Red Wings game against Winnipeg with an upper-body injury, prompting Detroit to move Emmitt Finnie to center.
Gasperini: “The match vs Verona the most exciting of all.”
Gian Piero Gasperini answered a barrage of questions from La Gazzetta dello Sport. The Roma coach looked back on some of his time with the Giallorossi, starting with the most emotional match: “I’d...
America.gov: New AI Tool Streamlines Government Navigation for Small Businesses - Small Business & Entrepreneurship Council
By Karen Kerrigan – For small business owners and those entrepreneurs just launching businesses, a frustrating aspect of dealing with government is often trying to figure out the rules and navigating websites to find the right information. A new federal AI-powered tool, America.gov, could make that process significantly easier. Launched on September 29, America.gov is […]
'Giant tusks from Siberia were thought to be the horns of the mythical unicorn': What medieval people made of fossils before vertebrate paleontology
In this excerpt from "The Story of the Mammals in 25 Discoveries," author Donald R. Prothero looks at a time when the idea of extinction was blasphemous.
Chargers Star Khalil Mack Emerges as Top Trade Candidate
Khalil Mack and the Los Angeles Chargers entered the 2026 season with Super Bowl aspirations. While the defense has been solid, the offense has not held up its end of the bargain.The Chargers sit at 0-3 and are gearing up for a road game against the Seattle Seahawks. This follows a loss in Buffalo in […] The post Chargers Star Khalil Mack Emerges as Top Trade Candidate appeared first on HEAVY.
North Huskies take down Vincennes
EVANSVILLE, Ind. (WEHT) — The North Huskies beat Vincennes, 34-17 on Friday. The Huskies will look to keep the wins coming when they face Jasper next week.
Gasperini: “I came to Roma to build something new.”
Gian Piero Gasperini spoke from the Trento Sports Festival. From individuals to his relationship with the fans, through memories and the future. On his arrival in Rome: “Everyone was eagerly awaitin...
Studying Science in an Anti-Scientific Time
This Chronicle Review Deep Cut was first published in 2025. By Julianne Werlin Thanks for reading The Chronicle Review! Subscribe for free to receive new posts and support my work. Subscribe The last two decades have not been kind to science studies. Already bruised and battered by the “science wars” of the 1990s, by the 2000s sociologists of science — who had long argued that science had to be understood in its human context — were encountering the funhouse-mirror version of their own views in right-wing critiques of climate scientists. It was enough to give some prominent scholars pause. “Was I wrong to participate in the invention of this field known as science studies?” asked Bruno Latour, the most famous sociologist of science in the world, in 2003. “Should we apologize for having been wrong all along? Or should we rather bring the sword of criticism to criticism itself and do a bit of soul-searching here: What were we really after when we were so intent on showing the social construction of scientific facts?” In response, Latour proposed a change of method and attitude. Science studies, now chastened and contrite, would no longer seek to strip facts of their authority, but to enrich and enhance them. What this meant in practice was never fully clear. But his diagnosis of problems resonated, even if his solutions did not. Latour’s exercise in public hand-wringing signaled a shift in mood. By 2016, with the first election of Donald Trump, the idea that skepticism of science was a right-wing position, not a left-wing one, had become a commonplace, discussed eagerly in The New York Times. For liberals, vaccine denial during the Covid era and Trump’s second-term attacks on the funding of scientific research, covered extensively in these pages, added a new urgency to the defense of science on both practical and principled grounds. There was little appetite for a sociology or philosophy of science that emphasized the messiness and missteps of the scientific process rather than its integrity and triumphs. The distinguished historian of science Peter Dear’s new book, The World as We Know It: From Natural Philosophy to Modern Science (Princeton University Press, 2025), which seeks to tell the story of 18th- and 19th-century science for a general public, may seem comfortably remote from these bitter contests. In its 16 short chapters, Dear draws swift, sure sketches of major discoveries from Newton to Einstein, ably guiding the reader through debates on stellar nebulae, animal taxonomy, atomic chemistry, evolution, and other flashpoints in the history of science. But though a work of history, Dear’s book must still negotiate our polarized present. In a blurb on its back cover, the historian of biology Lynn K. Nyhart alludes to the “present moment, when scientific knowledge is being swamped by misinformation and its institutions are under siege.” Dear himself, in his conclusion, refers to the “yard signs” and “bumper stickers” that proclaim “Science Is Real.” One antidote to both anti-science propaganda and to reductive slogans in science’s defense is a robust history and philosophy of science: exactly what Dear’s scholarship has long offered. But his new book illustrates how difficult such work has become. Dear, an emeritus professor of history at Cornell University, is best known as a creative and philosophically minded historian of the Scientific Revolution. His edited volume The Literary Structure of Scientific Argument (1991) analyzed the rhetoric of Galileo’s thought experiments to brilliant effect. Discipline and Experience: The Mathematical Way in the Scientific Revolution (1995) was a major contribution to the analysis of scientific experiments in early modern Europe and beyond, while Revolutionizing the Sciences: European Knowledge in Transition, 1500-1700 (2001), now in its third edition, remains one of the best overviews of the profound epistemological upheavals of 16th- and 17th-century science. But Dear has also ventured into later periods. Nearly two decades ago, in The Intelligibility of Nature: How Science Makes Sense of the World (2006), he turned to the 18th and 19th centuries to sketch a history and theory of scientific knowledge. Aimed at a generalist audience, Dear’s simple prose belied serious philosophical ambitions. Science, Dear argued, has two aspects: “natural philosophy,” the quest to understand the true nature of the universe, and “instrumentality,” the applied skills and technologies that allow us to manipulate the world for human advantage. Both strands are ancient, but the innovation of the phenomenon we call “science” was to yoke them together. As Francis Bacon wrote, “Human knowledge and human power meet in one; for where the cause is not known, the effect cannot be produced,” an insight typically abridged to “knowledge is power.” Or, in Bertrand Russell’s characteristically blunt phrase, science has two functions, “1. to enable us to know things, and 2., to enable us to do things.” So far, so conventional. But Dear took issue with this familiar story in one respect. Bacon’s formula implied that theory and practice could be fused in a single method. In fact, Dear argued, the quest to understand nature and the desire to manipulate it were coupled only loosely. They could come together, but they could also pull apart. Focusing on natural philosophy, the “knowing” half of the scientific circle, he used a series of case studies from cosmology, taxonomy, chemistry, electromagnetism, and quantum theory to show how theories changed over time, in dialogue with practice, but never reducible to it. Take the case of matter, the basic substrate of the physical world. In the 18th and 19th centuries, scientists not only disagreed about what it was, but also about how well it could be known. In 1789, the chemist Antoine Lavoisier dismissed speculation about the atomic composition of chemicals as “discussions entirely of a metaphysical nature,” as he sought to orient chemistry away from philosophical abstraction and toward laboratory results. But in the 19th century, atoms returned with a vengeance in the atomic chemistry of John Dalton, who wanted to explain the underlying structure of nature. It was not just that Dalton and Lavoisier had a different set of experimental results, or even a different theory, Dear showed. What counted as an explanation had changed. In arguing that scientific theories depended on their intelligibility to human beings with complex arrays of beliefs and commitments, Dear was in sympathy with science studies. Key figures such as the sociologist Steven Shapin emphasized the importance of psychological mechanisms like trust in the formation and acceptance of scientific ideas. But in focusing on the scientific pursuit of knowledge, not its politics or economics, Dear resisted the more cynical perspective of some of his colleagues. The Intelligibility of Nature strikes a very different note than Shapin’s collection of a few years later, Never Pure: Historical Studies of Science as If It Was Produced by People With Bodies, Situated in Time, Space, Culture, and Society, and Struggling for Credibility and Authority (2010), to name just one example. Walking a very fine line, Dear depicted science as driven at once by complex social dynamics and by the intellectual power of real discoveries. It was a testament not only to his own acumen but also to the vitality of the field that he was able to do so. Nearly two decades later, The World as We Know It returns to the questions broached in The Intelligibility of Nature. Like Dear’s earlier study, it begins with the Newtonian cosmos and ends with debates between Einstein and Bohr on quantum physics. Beyond its terminal figures, many of the same characters appear in both studies, including the naturalists John Ray and the Comte de Buffon; the chemists Étienne François Geoffroy, Antoine Lavoisier, and John Dalton; as well as Charles Darwin and Michael Faraday, among others. Its subject is nearly identical: As in The Intelligibility of Nature, The World as We Know It considers natural philosophy as opposed to instrumentality, here defined as the “desire to create a picture of what the world is really like — the world as God knows it — rather than simply having instrumental or operational control over it.” The two books also overlap in insights — and sometimes even in language. The reader who has learned in The Intelligibility of Nature that Buffon’s method of classifying animals “reflected his belief in the importance of the senses and empiricism in learning about nature (a doctrine associated with Newton and the philosopher John Locke)” will experience a sense of déjà vu on reading, in The World as We Know It, that the classification “reflects Buffon’s commitment to the epistemological stance of Newton and his philosophical underlaborer John Locke, who stressed the role of the senses in creating natural knowledge.” Later in the passage, we read that, “because of its stress on understanding the ways of life of animals in their environments, Buffon’s approach could almost be labeled (anachronistically) as ‘ecological.’” And again, “an anachronistic way of putting it would be to say that Buffon recommends an ecological mode of understanding.” Likewise, in The Intelligibility of Nature we read of Dalton that he was initially drawn to meteorology, and that: He did a bit of experimental work on these things, especially having to do with the water-holding capacity of gases, but his real interest lay in understanding what, at an underlying natural-philosophical level, was really going on physically.” Whereas, in The World as We Know It: He did experimental work on these things, especially concerning the water-holding capacity of gases — although not at a very refined level quantitatively — but he was continually trying to develop a theoretical conception of what was happening physically. The final full chapter of each book closes on the same resigned note. Intelligibility: These days, most serious work on the natural philosophical underpinnings and implications of quantum mechanics is performed not by physicists but by philosophers of science. Among scientific practitioners themselves, Bohr’s attempt to use instrumentality as sufficient grounds for a respectable science has met with a high degree of success. And again, in The World as We Know It: Bohr’s and Einstein’s concerns are now questions that are mostly discussed by philosophers of science rather than by physicists themselves. The marginalization of these sorts of questions amounts to the demise of natural philosophy, at least in physics, in the 20th century. Quantum mechanics “works,” and that’s good enough for most scientists who encounter it. Examples could be multiplied. When handling the same subject matter, some echoes are inevitable. Scholars should not feel that because they have written “Isaac Newton died in 1727” in one book, in the next they must describe him as perishing, expiring, or meeting his maker. But the repetitions of language and arguments (not to mention six reproduced images) threaded throughout The World as We Know It are more extensive than that. They should have been caught by Princeton University Press or its reviewers, and revised. Because the two books have so much in common, it is easy to see where they diverge. The World as We Know It is a less theoretical work than its predecessor. The sociology of knowledge that organized The Intelligibility of Nature has been reduced in scale and folded into readings and examples. The taut interplay between history and theory, which gave the earlier study so much interest, is there, but it is subtle. In the earlier book, the case studies demonstrated theoretical claims about the character and development of science. In the later work, each narrative of discovery is an end in itself. Insights emerge from the history, but they do not control the organization of the study. With the theory muted, it can be hard to understand the logic uniting Dear’s sprawling history of more than two centuries of scientific knowledge. The 16 brisk chapters cover an enormous amount of material. But the closer the volume edges to comprehensiveness, the more obvious the missing elements become. A chapter on “Institutions and Pedagogy,” describing the birth of the research university, illustrates the problem. Inserted roughly halfway through the book, the unnumbered chapter is designed as an “entr’acte,” in acknowledgement that it does not fit the study’s organization around scientific discoveries. Yet as Dear is well aware, no general history of the development of modern science can bracket its 19th-century institutionalization and professionalization. It was the 19th-century university, after all, that gave us the “scientist,” a term coined by the Cambridge philosopher William Whewell. Dear’s history of scientific discoveries implies a wider social and institutional history, but it remains largely subterranean, only occasionally extruded under the pressure of the narrative. It must be said that the balance is not all on the side of the earlier study. There are some advantages to the more historical, less theoretical organization of The World as We Know It. Dear’s accounts of paradigm shifts are remarkably lucid, no small accomplishment given that they span fields and centuries. He makes excellent use of the wealth of new scholarship on Darwin and his influences, to which he has himself contributed. It is satisfying to see puzzle pieces from Buffon’s natural history, Georges Cuvier’s animal taxonomy, Thomas Robert Malthus’s demography, and Charles Lyell’s geology recombined seamlessly in the Darwinian jigsaw. Likewise, Dear’s discussion of stellar nebulae, divided between chapters two and 15, shows vividly how Newton, Kant, Herschel, and Hubble reimagined insights and observations as they sought to discover whether the diffuse light that filtered through early telescopes was a glowing, gaseous substance or discrete but distant stars. Yet despite such pleasures, the book remains a more modest work than The Intelligibility of Nature. Dear has clearly not changed his views about the history of science. But in the two decades that have elapsed, the discipline and the world around it have changed, making it harder to write a sociologically and philosophically ambitious history of science for the general reader. That is a shame, because in the age of Silicon Valley and biotechnology, both the reciprocity and the tensions Dear identified between the epistemological and instrumental ambitions of science are more evident than ever. In recent years, some of the most exciting new books on the history of science in early modernity have focused precisely on this pressure point. Important studies such as Pamela H. Smith’s From Lived Experience to the Written Word (2022), James Poskett’s Horizons: The Global Origins of Modern Science (2022), and Vera Keller’s The Interlopers: Early Stuart Projects and the Undisciplining of Knowledge (2023) all shed new light on how early modern science negotiated the relationship between its instrumental and epistemological ambitions, or in Russell’s phrase, knowing and doing. There is every opportunity for a philosophically informed approach to draw new insights from this wealth of material. Dear, unfortunately, has not done so in The World as We Know It. But for future scholars of the history of science, his body of work over nearly four decades may provide just the model. Julianne Werlin is an associate professor of English at Duke University. Thanks for reading The Chronicle Review! Subscribe for free to receive new posts and support my work. Subscribe
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Primetime Review: That’s Entertainment?
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Bickley: Hungry Suns exert newfound continuity, camaraderie in 2026
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Art that serves others: How a Harnett County muralist is making a lasting mark in her community
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Natrona County health and food inspections (9/18/26–9/24/26)
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Rogers Tries to Make El-Sayed’s Health Care Plan Scary
_Taylor, Michigan_HERE’S HOW YOU CAN TELL Mike Rogers is anxious to make up ground in the Michigan Senate race: He held a press conference on health care last weekend. Health care is usually a rough issue for Republicans, because voters associate the GOP with attacking cherished programs like Medicare and Medicaid that Democrats have historically supported. It’s a particularly difficult issue in this campaign, because a few months ago Donald Trump and the Republicans refused to extend temporary financial assistance in the Affordable Care Act. As a result of that decision, more than 20 million Americans faced higher insurance prices this year. That’s not a policy choice you want to be defending at a time when voters frequently cite the cost of health care as a top concern. Throw in the fact that Democratic nominee Abdul El-Sayed can draw on his credibility as a doctor and former public health director in Detroit, and it might seem like Rogers’s best bet would be to avoid health care altogether. But Rogers had his reasons to spotlight health care last Saturday. And they became apparent a few minutes before he spoke, when members of his campaign staff There’s a lot happening. Too much, some days. We can’t promise to have all the answers. But we can promise to keep asking the questions, following the facts, and figuring things out alongside people who care about where this country is headed. Read with us. Learn with us. And when it matters, stand with us. Join the side you’re already on. Join Bulwark+
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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