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A new generation of public health students
Public health is often associated with hospitals, disease outbreaks and government agencies. But health also is shaped by architecture — by sidewalks, green space, accessible design and the environments people move through every day. Teddy Basa, a rising junior at Washington University in St. Louis, is seeking to better understand those connections. Basa arrived at […]
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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We can create the future of science right now
Paul Litvak is the founder and Executive Director of the Robyn Dawes Institute and a Visiting Scholar at UC Berkeley. He has a PhD in Behavioral Decision Research from Carnegie Mellon where he studied emotions and the sunk cost bias. Over 15 years in industry, he solved a wide range of challenging technical problems. At Meta he created models optimizing the ad review process. At Google he ran experiments to measure social influence. At Airbnb, he was a product manager leading machine learning teams optimizing search ranking and price suggestions. He also co-founded and led product at Rhythmic Health, a venture-backed biosensing startup, creating an accurate low cost system using a color changing strip and a smart phone to measure salivary lactate. The bottleneck At this point, it is uncontroversial to say that science needs to stop using the PDF article as the unit of knowledge and currency. The unbearable slowness of scientific publishing, the profit motive and margins: I’m not saying anything new. The PDF also sucks because it’s hard to extract structured information, which makes it hard to do evidence synthesis. As a result, we do much less evidence synthesis than is needed. And evidence synthesis ultimately undergirds most policy and medical decision-making. I can see second-by-second real-time odds for any sporting or newsworthy event, but a school board can’t see the best evidence on whether their 8th graders should be taught algebra. As a society, we don’t treat this as an important problem. Again, not controversial. Not only is the problem well understood, but the solution has already been laid out. What we need is AI-assisted living evidence synthesis - (1) an open knowledge graph of atomic claims, (2) claims linked to evidence, (3) assessment and synthesis of each piece of evidence, and (4) continuous updating with new data. What few realize (yet) is that the technical capacity to build this vision for a significant portion of science already exists. Not only that, scientists and startup teams are already building many of these components. I know this because I’ve been surveying the space and talking to many of the builders. There are some missing pieces: for example, evaluations of how well some of the components work. But at this point, most of what’s missing is a fully end-to-end working integration of all of these parts. In the rest of this essay, I’m going to lay out all the parts of a working living evidence layer for science and who is working on them, and propose concrete next steps for building this system. What’s now possible The diagram above outlines the components of a living evidence synthesis platform, including some of the teams working on each component1. Scientific PDFs are processed into claims with associated evidence. The evidence is subjected to a forensic audit, methodological evaluation and robustness and reproducibility checks. Finally it’s given a weight in a continuously updating synthesis. What follows is a description and status of each component and a few of the teams working on them. Document understanding The first thing you need to be able to do is turn an article into structured data. Mostly that means parsing PDFs. There are often multicolumn layouts that confuse non-specialized PDF to text processing libraries. For scientific papers, there is the added complexity of parsing formulas and tables and figures. This is a really hot area - there are startups offering APIs, and it seems like a new open source package gets posted to Github every few weeks. What follows isn’t exhaustive. A package called GROBID was the state of the art for a while, they didn’t update their package for nearly two years until very recently. In the meantime reducto.ai released an AI powered PDF extraction API, PaddleOCR became popular, IBM released a model called Docling, and both Mistral and Gemini created models and libraries. I also know of at least one other well-funded psychology research group working on a paper parser. By contrast, there are few open evals in this space, with no extensive evals for complex table comprehension in particular. Nonetheless, I’m confident this will be a solved problem soon, given the combination of LLM advances and developer interest. Hypothesis level extraction There has been increasing interest in comprehending the extracted text of papers and linking information to evidence for each hypothesis. A lot of work has already been done. Trialstreamer (Marshall et al. 2020) and RobotReviewer LIVE (Marshall et al. 2023) demonstrated automated extraction of trial population, intervention, and outcome at scale on clinical RCTs. PaperQA2 (Skarlinski et al. 2024) and Ai2 ScholarQA (2024) extended this to retrieval-augmented question answering with citation grounding. Elicit, Consensus, and SciSpace operationalized claim-level extraction for end users. OpenEval (Booeshaghi et al. 2026) is the most recent and most ambitious: 1.96 million atomic claims extracted from 16,087 eLife manuscripts using Claude Sonnet 4.5, grouped into ~299,000 results, with LLM evaluations showing 81% agreement with human peer review on a 2,487-paper subset. None of these solutions link claims to test-statistics, as you would need to evaluate randomized controlled trials. This is why I built the evidence.guide API - to extract hypotheses and associated test statistics from behavioral science papers. The best public eval of this kind of extraction I’m aware of comes from the recent SCORE project - they had humans code thousands of psychology papers to extract their claims by hand. It would be extremely helpful to the world if all scientific PDFs were available as structured open data. I’ve been working to make this happen, both directly at Berkeley and through coordination with large entities I can’t yet speak of; as hard as it is to do, I think it’s possible2. Forensic audit A lot of work has been done on forensic audit, but some gaps remain. Of course, for biology papers that rely on images for evidence, there are a variety of tools (notably Proofig and ImageTwin) to spot anomalies. These are still well short of what sleuths like Elizabeth Bik can do on her own, but these tools are constant companions among fraud analysts. There’s someone working on auditing Excel files for anomalies, and a number of teams are automating numerical checks like GRIM and SPRITE, including Scrutiny project, the INSPECT-SR team as well as statcheck. The regcheck team is building a way to use AI to compare preregistrations to analyses in papers, to ensure there aren’t significant deviations. Nonetheless, there are many other kinds of anomalies to screen for, both public and less publicly known. And there are no formal evals for anomaly detection that I’m aware of. Still, there’s a lot to draw from in this space and I’m pretty certain we will be able to scan papers for most kinds of obvious anomalies in the near future. Methodological review This area has been white hot, though I fear for many of the startups in this space, because this capability may become commoditized. There are at least six different AI peer review companies, including Refine.ink, Reviewer3, ReviewerZero.ai, Q.E.D. Science, Paper Wizard, and Isitcredible. Coarse (a pun on refine) was also recently created as an open source alternative. These systems provide qualitative feedback on the content of papers, spotting methodological weaknesses and mathematical errors. They seem to work pretty well, and many academics report bitterly that they exceed the average quality of typical peer reviewers. But there are few evals here either. What evals exist so far involve using LLM-as-judge (circularity problems abound) or comparing against human reviews of questionable quality. What you’d ideally want is an eval that measures capturing known errors in papers3. Reproducibility and robustness Another active area has been using AI agents to automate computational reproducibility4 and robustness5 checks in papers that report numerical results. For more recent papers where data and code are available, AI agents can see whether they can re-run the analyses and produce the numbers reported in the published paper. In addition to a handful of individual academics who have been experimenting using Claude Code for this, the Institute for Replication is a leading group working on building an end to end system. The evals related to this problem are the most mature, with CORE-Bench (Siegel, Kapoor, Narayanan 2024) and PaperBench (OpenAI 2025) available to benchmark agents on this task. There is also work on getting AI agents to test alternative ways of analyzing the data to ensure the results are robust to small analytic design choices. Synthesis This is the most underdeveloped area where significant investment is required. Although some automated evidence synthesis systems exist — for example, otto-sr is building an AI agent to write systematic reviews — none of these incorporate the full range of paper level signals to weight evidence appropriately. Nor is there anything like an eval or a gold standard for a good systematic review. Arguably Cochrane reviews are the closest we have to gold standard human systematic reviews, though I’ve heard academics in the know complain about their uneven quality. A key question for a synthesis platform is how to weight anomalies and methodological issues in assessing the quality of a piece of evidence. This is an unsolved problem and one I’m very keen to work on. Continuous updating There are many pieces of basic infrastructure available for monitoring for new research and initiating updates. OpenAlex is the current open citation graph. Retraction Watch integrated into Crossref in October 2023. Scite tracks how citations support, contrast, or mention prior claims. The Living Evidence Network demonstrated continuous-update workflows in clinical guidelines. Engineering this is a relatively straightforward task. When you look over this technical architecture and all the progress being made, it’s hard not to be optimistic that a living guide to scientific evidence will be built. The stakeholders are ready The social infrastructure for this is starting to coalesce — it’s not just a pie in the sky academic exercise to imagine this coming into existence. Institutions like the Center for Open Science, the Institute for Replication, the INSPECT-SR, the Living Evidence Network and more are all working on scaling work to improve research quality. Funders are also aligned. The Sloan Foundation has funded living evidence work through COS. Coefficient Giving supports the Institute for Replication and COS. The Astera Institute and the Institute for Progress have shown interest in this space. NIH has established an Office for Replication and Reproducibility. Although there are (very unfortunately) serious headwinds in science funding generally, there is an active group of funders interested in metascience. A brief word about what I’ve been doing at RDI. First, as a Visiting Scholar at Berkeley I’ve been actively figuring out how a non-profit and a public university can conduct and make public the results of large-scale academic article data mining. With some of the money I raised from donors, I commissioned a legal analysis of recent case law and publisher text data mining (TDM) agreements in order to understand whether a massive open data mining of academic articles is possible (with caveats, it is). I’ve also been working to bring together stakeholders in this space, and identify gaps. I’ve also been doing some software development in this space, with more to come. A pilot proposal The assumption undergirding all of this is that an AI, given all this information, would make the right judgment about a scientific claim with lots of conflicting evidence, weighing all the factors appropriately. That’s the hypothesis we need to test. Randomized control trial research is the best place to focus on first. RCTs are used to make many of the important decisions in society - from medical trials to public policy changes. And they use a relatively uniform set of inferential statistics with lots of known and available diagnostics. Behavioral science experiments, within the broader realm of RCTs, should be first used as a testbed whose results can be generalized. Because behavioral science is at the vanguard of open science practices, replications abound (there are thousands of them) to serve as ground truth training data. Key Hypothesis Therefore the pilot would test, in behavioral RCTs that have been replicated, whether the quality of evidence for a claim can be used to accurately predict whether that claim will replicate. Secondary Hypotheses Compared to claims that replicated, non-replicated claims demonstrate a greater share of forensic anomalies in their source literatures. Hypothesis level claim and statistic extraction is accurate enough to scale living evidence without onerous human review costs. Replication prediction is more accurate than prediction markets6 or journal prestige. If all the different quality signals we gather do accurately predict which studies will replicate, then we can use that model to score evidence to power the living evidence layer. Why this is informative regardless of outcome If the pilot succeeds, the architecture extends to medical RCTs (where Living Evidence already operates and integration is mostly about claim representation), then to slices of basic biology with stable replication structure. If it fails, the field learns which quality signals are load-bearing and which ones metascience has oversold. Either result is a contribution to knowing what the literature supports. Implications for funders Because this burgeoning ecosystem of builders already exists, a well-informed philanthropic or government funder could play a crucial catalyzing role in bringing this future about. They could play at least three roles: creating open structured datasets, publishing open benchmarks and incentivizing the solving of key technical challenges. First, open archives of papers that the government maintains, like PubMed, could be turned into structured data amenable to large scale metascience and claim aggregation. I know the US government already has an interest in doing this, though some key open questions remain unanswered. How do you determine the best models and systems for accurately extracting information from papers? How can you establish a robust way to allow researchers to flag errors and correct them? And finally, how do you create a legal regime in working with publishers to maximize the scope of available papers? For the latter, a university or a private philanthropy may be better positioned to make structured data publicly available under journal subscription terms or fair use. Philanthropists or government funders could also coordinate to create or commission benchmarks that evaluate whether important problems have been solved. For example, an open benchmark for claim extraction from a range of different scientific article types would be extremely helpful. Ensuring the underlying data are accurate is vital for creating these evaluations. I’ve discussed opportunistically using various human-created datasets for this purpose, but a consistent problem is that errors in human data make it difficult for them to serve as a gold standard. Finally, with structured data and benchmarks available, the government or private philanthropy could use them to incentivize groups to develop machine learning systems that meet these benchmarks. Prizes are one potentially valuable tool for this. For example, you could establish a prize for a system that accurately updates a living meta-analysis for a small set of claims. Prizes are particularly useful as signals of problem importance, and can help create vibrant ecosystems of public and private research—see, for example the role the government played in kickstarting the current work on nuclear fusion. Conclusion The drawbacks of the current scientific publishing system are known. Scientists agree, metascientists agree, philanthropists agree: the published PDF plus citation graph isn’t the right substrate for maintaining a representation of the evidence base in science. The pieces needed to build the alternative either already exist or are rapidly taking shape. The community is forming around exactly this problem, with concrete partnerships and shared infrastructure. A pilot should start on behavioral science RCTs because that’s the slice of empirical science most amenable to legibility, where replication ground truth is richest, and where the failure modes are best documented. What’s been missing is the galvanizing mission to assemble these pieces into something that works. That’s what I’m proposing to build. *** 1 I have a broader field map that I’ll release publicly soon. This is me, building in public! 2 If this is something that you are excited about, please reach out and talk to me. 3 More on this very soon too! 4 This tests whether, given the code and the data, you can get the same statistics as reported in the published paper. 5 This tests whether the results are the same as a paper’s given alternative analytical decisions in conducting the analysis (like outlier omission). Closely related is the idea of a “multiverse” where you come up with many different ways of answering the same underlying research question with the same data, and test whether the results hold in all those alternative methods. There’s been work on the latter as well. 6 Some of the replications, e.g. those from the SCORE project, had paired the experiments with forecasts from prediction markets. So we get to look at this for free.
NYC Health + Hospitals/Bellevue Director of Capital Design and Construction Yunjung Lee Recognized by Crain's New York Business as a 2026 Notable Leader in Architecture
NYC Health + Hospitals today announced that Yunjung Lee, Director of Capital Design and Construction at NYC Health + Hospitals/Bellevue, has been named to
NYC Health + Hospitals/Bellevue Director of Capital Design and Construction Yunjung Lee Recognized by Crain's New York Business as a 2026 Notable Leader in Architecture
NYC Health + Hospitals today announced that Yunjung Lee, Director of Capital Design and Construction at NYC Health + Hospitals/Bellevue, has been named to
Siri in iOS 27: Every New Feature and Change to Expect
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How AWS SMGS uses an AI-powered conversational assistant to transform business management with Amazon Bedrock AgentCore
In this post, we share how we built NarrateAI using Amazon Bedrock AgentCore to deliver business intelligence at scale for the AWS SMGS (Sales, Marketing and Global Services) organization. You will learn about: the two-layer architecture that separates batch processing from real-time interaction, the specialized AI agents that power intelligent routing and validation, key engineering patterns for production deployment, and how to build similar solutions with AWS services.
Advancing high-threat pathogen preparedness in WHO South-East Asia Region: 2025 in review
Effective preparedness for high-threat pathogens demands more than technical tools — it requires a coherent strategy, sustained country engagement, and the institutional infrastructure to translate evidence into action. In 2025, the Pandemic and Epidemic Management (PEM) Unit advanced all three, working across the full spectrum of high threat pathogen (HTP) preparedness: from methodology development and evidence generation to country-level technical support, emergency response, and regional workforce strengthening.At the core of the PEM unit's work is building the regional evidence and policy architecture needed to prioritize and respond to HTPs systematically. A major milestone was the development of the HTP Prioritization Methodology — a structured, multi-criteria approach to ranking pathogens by epidemic potential, severity, and national context — and its national pilot in Bangladesh, where SARS-CoV-2, Nipah, dengue, and cholera emerged as the highest-priority threats, informing the PEM unit's contribution to 2026–27 biennium prioritization and workplan development (Access link here).Underpinning this work, the PEM unit advanced the peer-reviewed evidence base for HTP preparedness in the South-East Asia Region (SEAR), with three publications in international journals in 2025: Development of a zoonotic influenza distribution assessment and ranking system (ZIDAR): Technical application in Nepal to support cross-sectoral risk-based surveillance in One Health; Implications for influenza A virus surveillance in Southeast Asian Region countries: a scoping review of approaches for the surveillance of swine influenza viruses at human-swine interfaces in BMJ Public Health; and Operationalizing multisector partnerships: a Theory of Action and Reflection tool for zoonotic influenzas in Health Policy and Planning. Together, these contributions move the Region’s HTP preparedness agenda from practice to science — generating the transferable methodological foundations that will inform evidence-based capacity strengthening in Member States.Country-level engagement in 2025 reflected the breadth of contexts in which HTP preparedness must function. Technical support was provided for Mpox and cholera events across the Region, including coordination of cholera and acute watery diarrhea prevention and control in Myanmar in the wake of the March 2025 earthquake. In Myanmar, the PEM unit contributed technical leadership to the earthquake emergency response — one of the most complex humanitarian emergencies in the SEAR — as Health Operations and Technical Support lead within the Incident Management Support Team. This included strengthening emergency response planning, supporting operational and after-action reviews, and providing monitoring and evaluation support for both acute and protracted crisis response. The breadth of HTP support provided to emergency operations across the SEAR was documented in the PEM unit’s contribution to the regional report for the Health Security Interface Technical Advisory Group.In Sri Lanka, technical collaboration with the WHO Country Office and the Ministry of Health laid the groundwork for the National Steering Committee's 2026 annual meeting, development of Standard Operating Procedures for specialized emergency response, and a national training programme — all structured around evidence-based risk assessment for specialized hazards including HTPs.Across the SEAR, the unit contributed to strengthening the workforce architecture that underpins HTP response. Technical inputs shaped the WHO South-East Asia Regional Health Emergency Workforce Strategy 2025–2030, and the PEM unit supported conceptual development of the health emergency workforce framework for the Pandemic Fund Round 3 proposal.Alongside this, the unit's sustained engagement on the meningitis agenda culminated in the launch of the Regional Implementation Framework to Defeat Meningitis in South-East Asia by 2030 at the Seventy-eighth Session of the Regional Committee, ensuring the Region's priorities were reflected in the Global Technical Task Force and expanding the unit's HTP engagement beyond outbreak-prone zoonotic pathogens (Regional Implementation Framework to Defeat Meningitis in South-East Asia by 2030).Taken together, 2025 demonstrated that meaningful HTP preparedness is built incrementally — through methodology, engagement, and the steady accumulation of institutional capacity across Member States.Bangladesh piloted the HTP Prioritization Methodology and identified the highest-priority pathogens in the country context (Photo credit: WHO Country Office, Bangladesh).
KernelScript: A Programming Language For Kernel Customization & App Optimizations
Multikernel Technologies Inc has been working on a multi-kernel architecture for the Linux kernel while in addition to that they have been developing KernelScript as a domain-specific language for carrying out Linux kernel customizations and app-specific optimizations.
WHA Advances Global Health Architecture Reform Amidst Questions About Where Process Will Really Lead
The 79th World Health Assembly adopted a widely anticipated Global Health Architecture Reform initiative. While WHO and many member states lauded it as a
Hybrid AI: Combining Deterministic Analytics with LLM Reasoning
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Quality data is key to healthcare AI fulfilling its promise
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Weymouth teen, dad start birdhouse business Chirp
A Weymouth father and daughter turned a backyard project into a growing business inspired by architecture and family time.
College of Architecture's Arts Business Ideas Competition winners announced
The College of Arts and Architecture’s Arts Business Ideas Competition recently announced the 2026 winners.
What Are The Differences Between The Ford And GM 10-Speed Automatic Transmissions?
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The art, science, and safety of human-decision support
John Hancock outlines how AI, architecture, and governance can help drive scalable and responsible transformation
OpenAI Picks MediaTek Over Qualcomm For Its First Smartphone, Customizing The Dimensity 9600 With A Dual-NPU Architecture To Challenge The iPhone
OpenAI's smartphone will use a customized Dimensity 9600 chip, replete with a dual-NPU architecture and enhanced HDR for visual sensing.
Tanzania’s purpose-built Star Homes brighten health outcomes
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Global Health & WASH: May 2026 Funding Opportunities (14 new opportunities!)
The May update for Global Health & WASH brings new calls that cluster around three distinct shifts: LMIC research leadership moving from funder encouragement into a hard eligibility constraint, pharmaceutical and corporate-linked funders running structurally independent education and use-inspired research portfolios at substantial scale, and AI adoption shifting decisively from speculative tool to operational capability across health and WASH systems alike. In LMIC Research Leadership as Eligibility, Not Encouragement, Wellcome anchors the dominant signal of the month with three separate major calls that all require or strongly center LMIC leadership in their basic eligibility architecture. Wellcome’s ESIC Hubs (£1.5-£1.9M per hub over 3-5 years) explicitly requires an LMIC-based lead applicant, treating Global South leadership as a design constraint rather than a participation goal. Wellcome’s Infectious Disease Clinical Trial Development Award funds transdisciplinary teams whose lead must be a mid-career or established researcher based at an organization in Africa, South Asia, or Southeast Asia. Wellcome’s larger Infectious Disease Clinical Trial Award (£1M-£8M for optimizing licensed interventions) requires the administering organization to be in eligible LMIC regions and at least 50% of applicants based there. Around Wellcome, the same pattern shows up at smaller scale and across funders: CHINNOVA channels $1M into West and Central African research institutions for climate-health work; IBRO’s Neuroscience Training Grants explicitly tier ceilings by region of residence with Africa receiving the highest amount ($5,000); IHME’s GBD Emerging Researcher Award reserves at least one of its two annual awards for an LMIC researcher; Sidaction’s HIV Cure call funds research teams across France, the Netherlands, and eligible African countries with a minimum two-country collaboration requirement. Taken together, these calls signal a meaningful shift in how research equity is being operationalized — not as encouragement language at the bottom of a call, but as a structural feature of who can lead, where the work must be administered, and what proportion of the team must be regionally rooted. In Pharma-Funded Independent Medical Education and Use-Inspired Research, the lineup this month is unusually deep. Pfizer alone runs four parallel calls under independent education and quality improvement frameworks: a Migraine and Women’s Health RFP (200K x 2-year, $500K pool), Migraine IME ($200K, $1M pool), JAK Inhibitor evidence-based education ($100K), and Maternal Vaccination HCP Education in Saudi Arabia ($75K), plus a separate Pediatric Pneumococcal Surveillance research call in Saudi Arabia ($400K per project). Novo Nordisk Foundation runs four parallel calls of its own at substantial scale: Infectious Diseases Catalyst Grants (DKK 60M pool, up to DKK 7M collaborative), Non-Diabetic Endocrinology Collaborative Grants (DKK 53M pool, DKK 5-10M per project), Pioneer Innovator Grant Health (DKK 1.1M), and Distinguished Innovator Grant Health (DKK 6.8M). LEO Foundation deploys DKK 2-4M per project for dermatology research excellence. Pfizer’s framing across calls deliberately separates the funding from product promotion, emphasizing measurable practice-relevant change and structural distance between scientific outputs and commercial activity. Novo Nordisk’s “use-inspired” hard filter pushes researchers toward a credible translation pathway from mechanism to deployable tool. The pattern: industry-aligned funders are running structurally independent portfolios at meaningful $ that fund implementation evidence, not promotion. In AI as Operational Capability, Not Speculation, several calls this month explicitly treat AI adoption as a near-term operational question with real evidence and governance requirements, rather than a speculative trend to be watched. Wellcome’s ESIC Hubs frames AI as “the accelerator” for evidence synthesis, asking hubs to translate technical innovation into adoption-ready workflows that can match real-world policy timelines. UNICEF Venture Fund’s new Climate Tech for Children’s Health call funds for-profit startups deploying AI, machine learning, and blockchain in low-resource environments, with a strict requirement that solutions must already have a working prototype with promising pilot results. The Water Research Foundation has launched two simultaneous AI calls treating reproducibility, cybersecurity guardrails, and human-in-the-loop deployments as core design constraints rather than nice-to-haves: one on GenAI and Agentic AI in water utilities ($200K), one on alternatives to water shutoffs that explicitly screens for implementation economics evidence. Nordic Innovation’s quantum technology call (NOK 4.5M) extends the same logic into life science and healthcare, demanding consortium-stage projects mature enough to test with real users. TEF-Health offers €300K in subsidized testing infrastructure for European healthcare AI and robotics SMEs. The pattern: funders are converting AI pilots into playbooks, requiring transfer evidence and risk controls before AI can move from experimentation to sector-wide operational practice. For LMIC-based researchers in infectious disease or evidence synthesis, the three Wellcome calls together represent the deepest concentration of LMIC-led research capital in recent memory — pair the Infectious Disease Clinical Trial Development Award (£200K, deadline May 19) as a strategic pipeline feeder into the larger Infectious Disease Clinical Trial Award (£1-£8M, deadline June 2), since the development award functions explicitly as a track into the larger trial scheme. For Nordic researchers, the four Novo Nordisk Foundation calls plus LEO Foundation and Nordic Innovation Quantum represent ~$30M in regional research capital this cycle, all with deadlines clustered in May-August. For WASH practitioners, the three Water Research Foundation calls together (each up to $200K) are a cluster worth reading across — one on AI deployment, one on shutoff alternatives, one rewarding applied innovation — and the strongest applicants will articulate how their work bridges utility operations to policy-relevant evidence. For US-based clinical researchers and educators, the four Pfizer calls plus the APF Portfolio’s 80+ programs form an unusually accessible recurring pipeline; APF’s prohibition on indirect costs is a meaningful structural feature for early-career applicants whose institutions might otherwise absorb significant overhead. Snapshot of New Opportunities Total Estimated Funding Pool: $100 Million+ USD The grants are organized into three categories: Open Calls: Current grant and opportunities with a deadline. Grants are listed by closing date. 39 open opportunities- 14 new! Rolling Applications: current grant and opportunities with rolling applications (but it’s still best to submit as early as possible). 14 rolling opportunities- 1 new opportunity! Long term planning: Grants that have closed their current rounds, but are expected to open new windows. 4 long term opportunities! A quick tip for returning readers: if you want to jump straight to the newest additions, use CTRL F to search for “New!” and navigate quickly to the latest funding opportunities This post is for paid subscribers. This helps support the time and effort it takes to curate and organize these opportunities. Subscribe To keep this accessible to everyone who needs it, we’re happy to offer pay what you can rates. You can find more details here. Open Calls: Migraine Competitive Grant Program: Migraine and Women’s Health (Quality Improvement and/or Research RFP), Pfizer.*Closing soon!* Pfizer, in collaboration with the American Headache Society, is seeking independent quality improvement and research projects that close persistent gaps in migraine care for women across the United States. The funding logic centers on measurable, practice-relevant change: proposals should generate actionable evidence, tools, or system improvements that can be shared and used widely, not just within a single site. Priority areas span menstrual migraine and screening in women’s health settings, the role of hormonal fluctuations across the lifespan, sex-specific risk factors, comorbidities and quality-of-life burden, and disparities in outcomes by race, ethnicity, and socioeconomic status. The call is structured as a two-step competitive process with an initial Letter of Intent, with the strongest concepts expected to translate scientific insight into implementable improvements in diagnosis, management, and equity. Geographies: United States. Who can apply: U.S.-based organizations (not individuals), including professional schools, healthcare institutions, professional organizations, and other entities focused on healthcare improvement. Funding amount: Up to USD $200,000 total over 2 years; total pool USD $500,000. Targeted Sectors / SDGs: Health; Focus areas: migraine, women’s health, quality improvement, clinical research, menstrual migraine, health disparities. Deadline: LOI: May 5, 2026; Full proposal (by invitation): August 28, 2026. Learn more and apply here. This RFP rewards “shareable impact”: the most competitive submissions will pair rigorous methods with a clear plan for system uptake and dissemination beyond the originating institution. ReSSARC: Strengthening the Health Sector and Food Security in the Central African Republic (AID 013381/01/0) Call for Proposals, Italian Agency for Development Cooperation (AICS). *Closing soon!* AICS is seeking a limited set of high-capacity humanitarian partners to deliver an integrated package that stabilizes essential health services while reducing acute malnutrition and strengthening food security resilience in priority areas of the Central African Republic. The funder’s logic is explicitly nexus-based: proposals should meet urgent, life-saving needs while reinforcing local systems, coordination mechanisms, and community-level capacity so results persist beyond the emergency window. AICS emphasizes inclusion and protection outcomes, expecting gender-sensitive design and explicit measures for groups facing compounded vulnerability, including women, children under five, internally displaced people, and people with disabilities. The call also signals a localization pathway, encouraging stronger collaboration with national NGOs and balanced partnerships, alongside clear coordination with existing cluster and humanitarian actors to minimize duplication and improve coverage. Geographies: Central African Republic (Bangui, Ombella-Mpoko, Ouham, Ouham-Pende, Lim-Pende, Lobaye). Who can apply: Non-profit organizations registered with AICS, plus eligible non-profits without an office in Italy that have a pre-existing collaboration agreement with an AICS-listed organization. Funding amount: Total pool EUR €1,800,000; max EUR €800,000 (single applicant) or EUR €1,000,000 (ATS). Targeted Sectors / SDGs: Health; Focus areas: malnutrition prevention and treatment, maternal and child health, community health services, food security and resilience, localization partnerships Deadline: May 5, 2026. Learn more and apply here. This call is structured to reward partners who can link frontline service delivery to system durability and localization, not just short-term coverage gains. Contracts for Innovation in drug and alcohol addiction healthcare, Innovate UK. *Closing soon!* Innovate UK, on behalf of the Office for Life Sciences Addiction Healthcare Goals program, is procuring R&D to accelerate innovations that can improve treatment outcomes, strengthen recovery, and reduce harm and deaths linked to drug and alcohol addiction. The competition is positioned as a market-facing readiness push: selected projects are expected to advance solutions toward later-stage validation, generate evidence of user acceptability and UK market fit, and map credible routes through regulatory and certification requirements. Innovate UK signals a preference for innovations that can be field-tested in relevant UK settings and progressed to TRL 6 or 7, with practical plans for commercialization after contract completion. This structure favors applicants that can execute most work in-house, co-develop with service providers and people with lived experience, and translate technical progress into deployable tools for addiction healthcare delivery. Geographies: United Kingdom. Who can apply: Single organizations of any size (including EU, EEA, or international) leading delivery, with most work and key deliverables carried out in the UK; subcontractors for specialist skills only. Funding amount: GBP £200,000–1.5 million per project (inclusive of VAT); Total pool: GBP £20 million (across two strands). Targeted Sectors / SDGs: Health; Focus areas: Mental Health, Health Systems Strengthening, Research & Development, Technology Access. Deadline: May 6, 2026 (11:00am). Learn more and apply here. This call uses procurement to pull near-market addiction innovations toward operational proof and adoption pathways in UK services.
Big Tobacco Is No Longer Selling Cigarettes – It Is Engineering Addiction
Europe needs a more precise focus to address the tobacco industry’s “engineered architecture of addiction”, featuring flavoured tobacco and nicotine products
Control Science — a one-sided case against managers
From the inspection towers of 19th-century factories to the data architecture of Amazon warehouses, Henry Snow casts those who surveil workers as capitalism’s villains
Tropical Modernism Beyond Aesthetics: The Politics of Shade and Air
Uncover the interplay of climate and architecture in tropical modernism, revealing its nuanced responses to heat and social structures.
Empowering Veterans: The 2026 Fayetteville Veterans Business Expo aims to close the opportunity gap
This is the first year of the Veteran Business Expo, and it grew out of Fayetteville PWC’s Economic Impact Program, which focuses on expanding access and opportunity in public-sector contracting while strengthening the local economy. It builds off the success of previous events held by PWC, like the 2024 Industry Day (pictured above). Photo provided by PWC. The Fayetteville Public Works Commission (PWC) will host the inaugural 2026 Veterans Business Expo on May 14 at the PWC Main Operations Complex at 955 Old Wilmington Road, seeking to connect former U.S. Military members with vital business opportunities in their community. The event, which will take place from 4 p.m. to 6 p.m., is part of a partnership between PWC and the Veterans Business Outreach Center at Fayetteville State University (VBOC) and Fayetteville-Cumberland Regional Entrepreneur and Business HUB (FSU HUB).Aaron Harris, PWC’s manager of economic inclusion programs, said the event is designed to connect Veteran-owned businesses with partners and decision-makers who can help move opportunities forward.“This event brings together Veteran entrepreneurs alongside government agencies, public entities, contractors and resource partners in one place, creating a purposeful space to build relationships, exploring procurement and contracting possibilities and strengthening our region’s Veteran-owned business community,” Harris said. The Veterans Business Expo was devised to feature, highlight and facilitate direct connections and commerce. “We want to get our Veterans a platform for their businesses,” said Camille Little, the supplier diversity analyst at PWC. “Here at PWC, we have 20 departments, and we procure… I can’t tell you all the goods and services. This is our first expo. We’re looking for general contractors, electricians, landscapers, janitorial, construction suppliers, architecture, farms and engineering firms.” Little said, much like businesses in every industry, Veterans are often in need of assistance getting their foot in the door.“When Veterans are starting up, they have to know what resources are [available],” Little noted. “They have this ample amount of resources, but they need to know how to get started.” Identifying those resources and connecting Veteran business owners with opportunities and business development programs are made possible by the partnership between PWC and VBOC, Little said. The partnership has allowed the expo to flourish, she added.“There are opportunities, there are consultant workshops and different things that we partner with them for all the time,” Little said. “It’s about easing that transition because starting a business is hard. Having the dedication to continue after that first year is even harder right now.” That is why, Little said, the partnership with resources from Fayetteville State University brings decision makers to the table. “If you are a Veteran business owner, you may not know how to do business with PWC or the City of Fayetteville or FSU, or partners,” Little said. “‘Where do I get started?’ ‘How do I get contracts?’ Bringing people to an understanding and then having an opportunity like this, where you’re talking to that person who’s making the decision… that is our goal.”Those meetings between Veteran-owned businesses and other decision-makers will present a chance to showcase products and services directly to organizations seeking qualified vendors and capable partners, Harris said. Agencies and contractors, he added, can meet and engage businesses ready to support upcoming needs. Little said PWC and all of its departments, as well as the City of Fayetteville, and FSU will be on hand. Additionally, there will be procurement officers from the North Carolina Department of Public Safety. “Resource partners who support small business development will also be on hand, helping make introductions and reinforcing pathways that support growth for Veteran entrepreneurs,” Harris said.For Veteran entrepreneurs, Little said she recommends two things: an answer to “why?” and a business plan.“I would ask them, what problem are they solving with their business?” she noted. “Then I would also tell them to start making a business plan. I run into a lot of firms, and it’s like, ‘What is your plan?’ So just knowing where you want to go with your business is important.”Little said it is important to differentiate between a business that helps transition servicemembers away from the U.S. Military versus a business that Veterans consider the next chapter of their lives.“How much dedication are you going to give to this business to make it successful?” Little noted. “So I would always start with what’s your business plan.”For Harris, the event will be able to cover the needs of all types of Veteran-owned businesses.“Another important lesson is the need to meet businesses where they are,” he said. “Veteran-owned businesses are at different stages of development, so offering multiple entry points, networking, education and referrals has proven essential.”Registration information can be found at: www.eventbrite. com/e/2026-veterans-business-expo-connecting-heroes-to-opportunity-tickets-1984308563329?aff=ebdssbdestsearch
HOK Acquires ROSSETTI To Expand Global Sports, Recreation And Entertainment Design Practice
HOK, a global architecture and design firm, has acquired ROSSETTI, a Detroit-based architecture firm with 57 years of sports venue expertise, deepening HOK's sports, recreation, and entertainment design practice and establishing its first office in Detroit. The combined firm will operate as HOK + ROSSETTI during the integration.
HOK Acquires ROSSETTI to Form Expanded Global Sports, Recreation and Entertainment Design Practice
HOK has acquired Detroit-based architecture firm ROSSETTI, expanding its global sports, recreation and entertainment design capabilities and creating a combined... Read More
Stadium architect Rossetti acquired by global giant HOK in sports and entertainment design expansion
A global architecture giant is doubling down on Detroit with a deal that expands its reach in one of the most competitive corners of the design world: sports and entertainment venues.
HOK and ROSSETTI Join Forces to Create Expanded Global Sports, Recreation and Entertainment Design Practice
HOK has acquired ROSSETTI, a Detroit-based architecture firm recognized nationally for its sports venue design and renovation work.
HOK and ROSSETTI Join Forces to Create Expanded Global Sports, Recreation and Entertainment Design Practice
HOK has acquired ROSSETTI, a Detroit-based architecture firm recognized nationally for its sports venue design and renovation work.
Africa CDC Launches African High-Level Ministerial Committee to Shape Global Health Architecture Reform
Nairobi, Kenya | 27 April 2026 — Africa Centres for Disease Control and Prevention (Africa CDC) today launched the African High-Level Ministerial Committee on Global Health Architecture Reform (AHLMC) on the margins of the World Health Summit Regional Meeting 2026 in Nairobi, Kenya. The Committee brings together Ministers of Health and Finance from across the continent to […]
Samsung Galaxy S27 Ultra Might Sport A 5,800mAh Battery – Here’s Why It’ll Be More Than Enough Even As Chinese Rivals Push 6,000mAh+ Batteries
Samsung Galaxy S27 Ultra to sport the uber-efficient M16 OLED screen, with overall efficiency bolstered by Exynos 2700's new architecture.
The Kurdish Bargain: Elite Politics and Federalism in the Kurdistan Region of Iraq
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The medical AI revolution requires rethinking health care's architecture
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Everything to know about David Geffen Galleries as a new LACMA emerges
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‘Aggie docs’ coming to San Antonio’s South Side with new medical collaboration
Texas A&M medical students will begin clinical rotations at University Health’s Palo Alto Hospital and Vida clinic in 2028.
Dimensity 9600 Pro To Bring Desktop-Level Performance To Smartphones With New Architecture & 5GHz Target Speed, At A Significant Trade-Off
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The Future of Brain Health Is Architecture
We’ve long recognized the importance of buildings in meeting a basic human need: shelter. Now, research shows how buildings can improve our overall brain health.
Karpathy shares 'LLM Knowledge Base' architecture that bypasses RAG with an evolving markdown library maintained by AI
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Gemma 4 and what makes an open model succeed
Having written a lot of model release blog posts, there’s something much harder about reviewing open models when they drop relative to closed models, especially in 2026. In recent years, there were so few open models, so when Llama 3 was released most people were still doing research on Llama 2 and super happy to get an update. When Qwen 3 was released, the Llama 4 fiasco had just gone down, and a whole research community was emerging to study RL on Qwen 2.5 — it was a no brainer to upgrade. Today, when an open model releases, it’s competing with Qwen 3.5, Kimi K2.5, GLM 5, MiniMax M2.5, GPT-OSS, Arcee Large, Nemotron 3, Olmo 3, and others. The space is populated, but still feels full of hidden opportunity. The potential of open models feels like a dark matter, a potential we know is huge, but few clear recipes and examples for how to unlock it are out there. Agentic AI, OpenClaw, and everything brewing in that space is going to spur mass experimentation in open models to complement the likes of Claude and Codex, not replace them. Especially with open models, the benchmarks at release are an extremely incomplete story. In some ways this is exciting, as new open models have a much higher variance and ability to surprise, but it also points at some structural reasons that make building businesses and great AI experiences around open models harder than the closed alternatives. When a new Claude Opus or GPT drops, spending a few hours with them in my agentic workflows is genuinely a good vibe test. For open models, putting them through this test is a category error. Something else to be said about open models in the era of agents is that they get out of the debate of integration, harnesses, and tools and let us see close to the ground on what exactly is the ability of just a model. Of course, we can’t test some things like search abilities without some tool, but being able to measure exactly the pace of progress of the model alone is a welcome simplification to a systematically opaque AI space. Share The list of factors I’d use to assess a new open-weight model I’m considering investing in includes: Model performance (and size) — how this model performs on benchmarks I care about and how it compares to other models of a similar size. Country of origin — some businesses care deeply about provenance, and if a model was built in China or not. Model license — if a model needs legal approval for use, uptake will be slower at mid-sized and large companies. Tooling at release — many models release with half-broken, or at least substantially slower, implementations in popular software like vLLM, Transformers, SGLANG, etc due to pushing the envelope of architectures or tools. Model fine-tunability — how easy or hard it is to modify the given model to your use-case when you actually try and use it. The core problem is that some of these are immediately available at release, e.g. general performance, license, origin, etc. but others such as tooling take day(s) to week(s) to stabilize, and others are open research questions — with no group systematically monitoring fine-tunability. In the early era of open models, the days of Llama 2 or 3 and Qwen pre v3.5, the architectures were fairly simple and the models tended to work out of the box. Some of this was due to the extremely hard work of the Llama, Qwen, Mistral, etc. developer teams. Some is due to the new models being genuinely harder to work with. When it comes to something like Qwen 3.5 or Nemotron 3, with hybrid models (either gated delta net or mamba layers), the tooling is very rough at release. Things you would expect to “just work” often don’t. I’ve been following this area closely since we released Olmo Hybrid with a similar architecture, and Qwen 3.5 is just starting to work well in the various open-source tools that need to all play nice together for RL research. That’s 1.5 months after the release date! This is just to start really investing more into understanding the behavior of the models. Of course, others started working on these models sooner by investing more engineering resources or relying on partially closed software. The fully open and distributed ecosystem takes a long time to get going on some new models. All of this is lead-in for the most important question for open models — how easy is it to adapt to specific use-cases? This is a different problem for different model sizes. Large MoE open-weight models may be used by entities like Cursor who need complex capabilities in their domain, e.g. Composer 2 trained on Kimi K2.5. Other applications can be built on much smaller models, such as Chroma’s Context-1 model for agentic search, built on GPT-OSS 20B. The question of “which models are fine-tunable” is largely background knowledge known by engineers across the industry. There should be a thriving research area here to support the open ecosystem model. The first step is to understand characteristics of different base and post-trained models to understand what they look like. The second step is to tune pretraining recipes for open models so they’re more flexible. Interconnects AI is a reader-supported publication. Consider becoming a subscriber. Subscribe For The ATOM Project and other Interconnects endeavors, we’ve put in substantial effort to measuring adoption trends in the open ecosystem. Everything takes a long time to unfold after a model is first publicly available — and adaptability is why. What we know for sure now, when Qwen has been going from strength to strength with its releases, is that technical staff across the industry has gotten comfortable working with Qwen models. Countless research methods and datasets were made to work with Qwen. It’ll take patience for any other model family to get to this point — a patience I’m not sure many open model builders have. This takes us to Gemma 4, Google’s latest open models. Gemma 3 was released more than a year ago, in March of 2025, and is a bit underrated. Gemma 4 comes in 4 sizes for now, with a bigger, MoE model of over 100B total parameters rumored but not released yet. The models we have today come in sizes of ~5B dense, 8B dense, 26B total 4B active MoE, and 31B dense. I’m most excited that they’re finally adopting a standard Apache 2.0 open source license. This’ll massively boost adoption. The standard of better licenses for strong open-weight LLMs was set by mostly Chinese open model labs in the last 1-2 years, and now U.S. companies are following suit. I will personally be so happy if the horrible Llama licenses and Gemma terms of service were an ~18-month transient dynamic of the industry being nervous about releasing strong open models. The Gemma 4 scores look very solid, the small models have incredible benchmark scores (especially in general domains like LMArena) and the 31B model rivals the recent Qwen 3.5 27B, which is the leading member of that class. The ~30B size range is an important one, as it’s accessible both to researchers and to enterprises looking to deploy the model in real use-cases. Where the 7B model scale is the default for tinkering and research, a 30B model is the default for seeing if an open model can unlock substantial value in your specific workflow — a good mix of intelligence, low price, tractability for downstream training, etc. This takes us back to the above adoption criteria I mentioned for open models and the bigger question — do I think Gemma 4 will be an overwhelming success? Previous Gemma models have been plagued by tooling issues and poorer performance when being finetuned. Gemma 4’s success is going to be entirely determined by ease of use, to a point where a 5-10% swing on benchmarks wouldn’t matter at all. It’s strong enough, small enough, with the right license, and from the U.S., so many companies are going to slot it in. I’m cautiously optimistic that Gemma 4 is going to work better here. Winds are shifting for open models built in America. We saw GPT-OSS go through a bumpy launch to become an overwhelming success. There’s a collective energy around the likes of Reflection, Arcee, Nemotron, Gemma, Olmo, and peers that show substantial demand for building new stacks around open models. There’s capital to be spent on AI stacks across the economy by those who want more ownership of everything, including the model. After launching The ATOM Project 240 days ago, the conversation is shifting into the next stage. Summer of 2025 was a crisis moment where the U.S. AI scene realized it can’t wait and figure out open models after building AGI. The two markets will capture different areas and proceed in parallel. Now that more companies in the U.S. are releasing strong models, we need to improve the ecosystem so that these models are easy to use, understand, and build value around. It’s the hard work to build another inflection point in these adoption plots I’ve been updating consistently, but that’s the work to be done. Join me in it. More data coming soon! Here’s a sneak peek:
Designing the human science experience: How architecture shapes collaboration and discovery
Universities are rethinking lab architecture to foster interdisciplinary collaboration, from open "collision zones" at Wisconsin to flexible underground quantum labs at Maryland.
MediaTek Dimensity 9600 Chip To Feature 2 Ultra-Large ARM Cores For The First Time In A 2+3+3 Overall CPU Configuration
MediaTek Dimensity 9600 appears to be emulating the 2+3+3 CPU architecture of Qualcomm's upcoming Snapdragon 8 Elite Gen 6 chip.
Scientists Build Five-in-One “Super Molecule” for Next-Gen Electronics
A hybrid synthesis strategy enables complex molecular architectures to function as a single electronic system.
Is an IDA Health Window the Global Health Financing Solution?
The global health architecture is facing intense scrutiny. There are now an A-Z of initiatives launched to lead the reform, from the Accra Reset to the Lusaka Agenda Secretariat and a WHO-led process. Critics have argued that the current system fails to focus on the poorest countries, fragments national systems, undermines country ownership, and displaces domestic health spending.
Connections: UA dean receives Champion of Construction award - Talk Business & Politics
Peter MacKeith, dean of the Fay Jones School of Architecture and Design at the University of Arkansas, has received the 2026 Champion of Construction Award from the Associated General Contractors...
Connections: UA dean receives Champion of Construction award - Talk Business & Politics
Peter MacKeith, dean of the Fay Jones School of Architecture and Design at the University of Arkansas, has received the 2026 Champion of Construction Award from the Associated General Contractors...
Apple explains why M5 chips have three different core types in new interview
Apple explains M5's three core types: super cores for single-thread tasks, performance cores for multi-threading, and efficiency cores.
Weymouth teen, dad start birdhouse business Chirp
A Weymouth father and daughter turned a backyard project into a growing business inspired by architecture and family time.
Albatross Entertainment takes top spot as Best New Tenpin Center in the U.S.
EDISON, N.J. — Albatross Entertainment (Albatross) in Edison, New Jersey, has been named Best New Tenpin Center in the U.S. in the 41st Annual Bowling Center Architecture and Design Awards, present…
Linux Finally Catches Up to Windows with a Game-Changing Performance Feature
For years, the Linux kernel’s scheduler has been world‑class at balancing loads, yet it missed a crucial, cache‑aware instinct. In modern multi‑core systems, that gap can turn into measurable latency, especially when threads bounce between cores that don’t share the same cache. A new upstream feature, often called Cache Aware Scheduling, is now set to change that equation. A cache‑savvy scheduler arrives At the heart of any OS, the scheduler decides which thread runs where and for how long. In modern CPUs, small private caches (L1 and L2) sit beside each core, while a larger Last Level Cache (LLC, typically L3) is shared among groups of cores. When a task migrates across LLC boundaries, its warm data may vanish from the cache, forcing slower trips to main memory. Cache Aware Scheduling keeps related tasks close to their shared LLC, reducing destructive migrations. By respecting cache topology, the kernel minimizes cold‑start penalties and preserves locality that many workloads desperately need. The result is less thrashing, fewer memory stalls, and more consistent throughput. "Keep tasks close to their data, and the system will keep performance close to its peak." Why this narrows the Windows gap Windows has long leaned on topology‑aware, cache‑sensitive heuristics, especially since the Windows 10 era. That advantage helped Microsoft handle hybrid designs with P‑cores and E‑cores, plus complex cluster and NUMA layouts. With cache awareness integrated upstream, Linux brings parity to this vital dimension, without sacrificing its trademark flexibility. The Linux approach remains deeply configurable, reflecting the ecosystem’s breadth across servers, desktops, and embedded devices. It layers atop existing NUMA‑balancing and energy‑aware logic, refining placement rather than reinventing the wheel. Crucially, it aligns scheduling with the hardware’s real shape, not just with abstract CPU counts. Real‑world gains and who benefits Early tests on Intel Sapphire Rapids platforms point to gains in the 30–45% range for select workloads. Those wins appear in cache‑sensitive tasks like in‑memory analytics, high‑thread compilation, and microservices with tight working‑sets. Games and latency‑bound engines can also feel steadier frame‑times, especially when threads share hot assets. The benefits extend to AMD’s 3D V‑Cache parts, where keeping threads near enlarged cache slices prevents needless misses. Hybrid x86 designs with performance and efficiency cores further profit when cache and core roles are scheduled in concert. Even handhelds running SteamOS can squeeze more out of limited power, translating cache locality into smoother play. Key advantages include: Lower end‑to‑end latency Fewer expensive misses to RAM Better multi‑socket and NUMA behavior Improved energy efficiency More predictable QoS under mixed loads Stronger scaling on dense servers Caveats, tuning, and rollout No scheduler change is purely free, and trade‑offs still exist. Favoring locality can reduce cross‑cluster balance if limits are set too tight. Likewise, fairness and utilization must remain healthy, especially under heterogeneous, bursty workloads. Linux’s implementation is designed to be measured and tunable, not a blunt instrument. It cooperates with energy‑aware scheduling for mobile efficiency, and with NUMA‑balancers on big iron. Expect architecture‑specific refinements as vendors surface richer topology hints and cache‑sharing maps. Upstream integration has begun, with broad distribution adoption likely over the next cycles. Many users will encounter the change through standard kernel updates in 2025–2026, depending on distro cadence. Server‑class kernels may enable or tune it sooner for targeted fleets where cache locality is money in the bank. How to think about performance impact Cache Aware Scheduling amplifies gains when your workload is both CPU‑bound and cache‑sensitive. Think tight inner loops, hot code paths, and datasets that fit snugly in shared LLC. It’s less dramatic for I/O‑bound services or memory‑hungry tasks that blow past cache capacity. Still, even modest locality improvements often translate into smoother tail‑latency, which is where user experience and SLAs typically break. Developers can further help by pinning related threads, batching work, and aligning data to reduce cross‑cluster chatter. The scheduler’s new awareness works best when applications expose good hints. The bottom line By understanding and honoring cache topology, Linux removes a subtle yet costly bottleneck. The kernel’s smarter placement keeps hot data hot and work near where it belongs. That narrows a long‑standing gap with Windows, while preserving the openness and tunability Linux champions. For gamers, creators, and operators, the payoff is practical: more consistent frames, faster builds, and snappier services. For the ecosystem, it’s another step toward hardware‑savvy scheduling that turns transistor complexity into real‑world speed. And for Linux itself, it’s a timely upgrade that matches today’s silicon with tomorrow’s expectations.
M5 Max’s Fusion Architecture Allows For Better Sustained Performance While Running 8 Degrees Celsius Cooler Than M4 Max; Still Gets Uncomfortably Hot
The Fusion Architecture allows the M5 Max to maintain better thermals than the M4 Max while delivering better performance, as shown in the latest comparison
Apple on MacBook Neo Design: 'We're Certainly Not Making Any Compromises'
While the MacBook Neo starts at just $599, or an even lower $499 for college students, Apple has insisted that it did not make any design compromises. "It's undeniably a MacBook, we're certainly not making any compromises on the design and that's really important," said Apple's vice president of industrial design Molly Anderson, in an interview with architecture and design publication Dezeen.
Contributor: Why healthcare is so expensive in America, and what to do about it
People are questioning if the architecture of American healthcare can create any living, breathing incentive for affordability.
College of Arts and Architecture’s Art Business Idea Competition accepting entries
The College of Arts and Architecture's Arts Business Idea Competition — the college’s annual showcase of arts entrepreneurship — is accepting entries through April 1.
After Indiana gambit, Bears signal progress in Illinois
The back and forth comes as the team tries to advance legislation in two states without making public comments that could sour relationships or scuttle talks on either side of the border.
Commission voting on East Wing concept has few members with arts experience, little time for public comment
The Commission of Fine Arts, an independent federal agency that advises the president and Congress on design plans for monuments, memorials, coins and federal buildings, is usually made up of experts in architecture, art and urban and landscape design.
First Core Ultra 7 355 benchmarks are in and they're nowhere near as good as the Core Ultra X7
Panther Lake-H has proven itself to be quite impressive thus far, but the lesser Panther Lake-U series loses a lot of what makes the architecture unique from predecessors.
Record-Breaking One-Off Bugatti Brouillard Could Become the Most Expensive Bugatti Ever
A one-off aimed at a historic record Bugatti’s latest one-off, the Brouillard, steps onto the hypercar stage with the quiet confidence of a record-breaker. The brand’s tradition of bespoke excellence meets a bold new aesthetic, positioning this unique commission to potentially become the marque’s most expensive creation. Built on the proven underpinnings of the Chiron/Mistral architecture, yet transformed by distinctive craft, the Brouillard is both homage and innovation. A name born from equestrian legend More than a century ago, a striking white horse captivated Ettore Bugatti in Molsheim. That equine myth now informs the car’s name and its sensory identity. The result is an automotive portrait of athletic grace—surfaces that read like muscle, curves that suggest motion, and details that quietly speak of discipline and heritage. Embroidered horse motifs on door panels and seat backs echo the story, while a miniature glass sculpture of the steed crowns the shifter. Sculptural design with purpose The Brouillard’s silhouette favors sinuous surfaces over hard creases, allowing light to glide over its form like a tendon under skin. Aerodynamics inform elegance: an integrated ducktail replaces a deployable wing, cleansing the airflow and boosting stability at speed. Its stance is athletic, its volumes taut, and its visual language unmistakably Bugatti. “Sculptural, organic forms—like a tendon beneath the skin—hide immense power behind noble simplicity,” said design chief Frank Heyl, capturing the car’s philosophy in a single stroke. Craft elevated to an art The cabin embraces craftsmanship at an uncommon level. Custom-woven textiles from Paris introduce a discreet tartan pattern, while green-tinted carbon fiber nods to the exterior’s hue. A glazed roof creates a cathedral atmosphere, bathing the cockpit in natural light. A central spine appears to flow from exterior to interior, emphasizing continuity and structure. Highlights include: Custom textiles with subtle tartan motifs Green-tinted carbon fiber matched to the exterior finish A “cathedral” glass roof that elevates cabin ambience A sculptural centerline linking outside to inside Bespoke embroidery and glass equine detail W16 power at its absolute apex Under the sculpted skin, the final evolution of Bugatti’s 8.0‑liter, quad‑turbo W16 delivers a thunderous 1,600 hp at 7,050 rpm and 1,600 Nm of torque. This represents the pinnacle of nearly two decades of Bugatti engineering, honed to an ultimate state. The lightweight monocoque blends carbon fiber with aluminum, holding mass to around 1,900 kg for poise and control. Experts suggest the Brouillard could surpass the 282 mph (454 km/h) achieved by the Mistral, aided by more aerodynamic bodywork and the fixed ducktail. Whether or not it sets a new benchmark, its intent is clear: relentless speed paired with refinement. Exclusivity with an exacting timeline The commissioning process is intensive, with roughly 18 months of development leading to a 2027 delivery. Bugatti’s program limits itself to no more than two creations per year, ensuring focus and rarity. Each example leaves the atelier as a singular vision, shaped to the client’s collection and the brand’s ethos. An unveiling is planned for Monterey Car Week 2025, placing the Brouillard amid the world’s most discerning enthusiasts. Its patron is a European collector deeply invested in the Bugatti universe, from historic and modern cars to Carlo Bugatti furniture and Rembrandt Bugatti bronzes. A valuation poised to make history While Bugatti has not disclosed an official price, informed estimates place the Brouillard between €10 million and €30 million. Context matters: a series Mistral begins near €5 million, while the Brouillard adds profound personalization, sculptural changes, and a pace of production that keeps scarcity front and center. In an arena where uniqueness drives value, the path to a brand record is unmistakably open. What it signals for the marque The Brouillard crystallizes Bugatti’s dual identity: traditional savoir‑faire intertwined with boundary-pushing performance. It exhibits a narrative soul—the white horse of Molsheim—woven into modern materials and world-class aerodynamics. As a rolling statement, it reaffirms that the Bugatti idea is larger than speed alone; it is about story, craft, and the courage to pursue an ideal to its logical limit.
Oklahoma legislators to join STEM panel at Oklahoma State Science and Engineering Fair
Oklahoma legislators to join STEM panel at Oklahoma State Science and Engineering Fair. The 68th annual Oklahoma State Science and Engineering Fair will be hosted at Oklahoma State University in Stillwater on Friday, March 27.
AMD to use RDNA5 for premium iGPU solutions, but RDNA3.5 to remain the core of AMD portfolio until 2029
VEGA RDNA3.5 lives AMD's integrated graphics roadmap has become hard to follow. The current APU lineup keeps circling back to the same iGPU architecture,
What’s Buried by Baghdad’s Construction Boom
The politics of rebuilding in a city of memories.
The Disconnected Present: Neoliberal Fascism and the Politics of Erasure
In this political climate, outrage is incessantly manufactured and then swiftly displaced, replaced by the next shock before the public can assemble the fragments into a coherent political picture. Each incident appears as an isolated rupture rather than as part of an unfolding structure of power, severed from the conditions that produce it and from the larger architecture of domination it sustains. This fragmentation is not accidental. It is a calculated strategy to drain meaning from public life, exhaust critical attention, and foreclose any sustained democratic reckoning or resistance. In the age of escalating fascism and a nihilistic worship of greed and raw power, American politics has devolved into a theater of violence aligned with a ceaseless stream of spectacles severed from history and emptied of systemic meaning.
The Disconnected Present: Neoliberal Fascism and the Politics of Erasure
In this political climate, outrage is incessantly manufactured and then swiftly displaced, replaced by the next shock before the public can assemble the fragments into a coherent political picture. Each incident appears as an isolated rupture rather than as part of an unfolding structure of power, severed from the conditions that produce it and from the larger architecture of domination it sustains. This fragmentation is not accidental. It is a calculated strategy to drain meaning from public life, exhaust critical attention, and foreclose any sustained democratic reckoning or resistance. In the age of escalating fascism and a nihilistic worship of greed and raw power, American politics has devolved into a theater of violence aligned with a ceaseless stream of spectacles severed from history and emptied of systemic meaning.
LANL: Los Alamos To Play Key Role In Renewed Quantum Science Center
The Quantum Science Center will develop hybrid computing architectures that integrate quantum computers with leadership-class HPCs. Image courtesy Adam Malin/ORNL, Dept. of Energy LANL NEWS RELEASE…
Intel Launches Core Ultra Series 3 Mobile Processors – Panther Lake Roars to Life
At CES 2026, Intel launched its latest generation of mobile processors: Core Ultra Series 3. Packing several new architectures and built on Intel's 18A fab node, Series 3 packs a punch
WellSpan Health Announces Comprehensive Migration of Technology Portfolio to AWS
Add to FavoritesWellSpan Health, the leading health care system serving Central Pennsylvania and Northern Maryland, today announced plans for a comprehensive cloud migration of its full technology infrastructure. Together with Amazon Web Services (AWS) as its preferred cloud provider, WellSpan will transition its applications, data and environments from traditional data centers to AWS. This migration will establish the foundation for delivering next-generation, AI-enabled health care solutions that reduce administrative burden and improve outcomes for patients across the region and beyond. Supercharging Innovation, Efficiency and Patient Outcomes WellSpan's migration of systems and clinical applications, which serve 1.2 million patients across nine hospitals and 250+ facilities, is expected to be complete by April 2026, one of the fastest full-scale migrations in the health care industry. This transformation enables WellSpan to unify disparate data systems for care teams and patients alike, achieving operational efficiencies and care improvements that fragmented systems are unable to deliver. “Our comprehensive migration to the cloud accelerates our ability to deploy new clinical capabilities that transform patient care while advancing our overall innovation strategy,” said Roxanna Gapstur, Ph.D., R.N., president and CEO, WellSpan Health. “When a physician can access complete patient imaging in seconds instead of hours, we're not just modernizing technology—we're improving patient outcomes. Our new cloud infrastructure also enables us to quickly implement solutions that will free our clinicians from thousands of hours of administrative work annually so they can focus on what they do best: caring for our communities.” The transition allows WellSpan to move away from a data center-based model and enables the rapid deployment and scale of AI technology. WellSpan’s strategic partner, General Catalyst’s Health Assurance Transformation Company (HATCo), facilitated the collaboration with AWS to support the migration. WellSpan’s transformation journey benefits from HATCo’s specialized technology solutions, as well as General Catalyst and AWS’s significant partnership to improve patient outcomes, which was announced in January 2025. “Our decision to go all-in on AWS will enable insights and innovations impossible in traditional siloed environments,” said Kasey Paulus, executive vice president and chief operating officer, WellSpan Health. “This is the largest health care technology transformation in our region's history, and it positions WellSpan to be a premier partner for technology leaders across the country.” “WellSpan is building a foundation with AWS that will improve care and outcomes for patients across their health system by bringing data together into standardized formats that are optimized for AI applications,” said Dan Sheeran, vice president and general manager, Healthcare and Life Science, AWS. “To do this, it is essential to have the most secure and compliant cloud when handling patient data, along with AWS’s built-in AI governance and responsible AI frameworks that follow the industry’s highest standards to protect patient information. We look forward to continuing to work alongside WellSpan as they unlock the cloud and AI’s full potential to deliver exceptional care to their patients.” Key Benefits of the AWS Collaboration Full Portfolio Migration: WellSpan will transition its applications and data from on-premises data centers to AWS, including full IT environments and specialized applications for functions such as nursing, cardiology, pharmacy and the company’s supply chain systems. This represents approximately 7.5 petabytes of clinical and non-clinical data and more than 300 applications—the most comprehensive health system cloud migration in the Mid-Atlantic region. Approved Architectures: AWS will deliver secure, WellSpan-specific architectures tailored to each build, ensuring compliance and reliability across the health system. Unified, AI-Ready Data: Migrating to AWS enables WellSpan to harmonize data across separate systems, transforming unstructured clinical notes and multi-modal datasets into standardized, AI-ready formats. Accelerated Results and Improved Outcomes: Automated data normalization and processing will enable the deployment of applications that reduce turnaround times for items such as analyzing medical imaging or patient records from days to minutes, helping clinicians get patient results faster and improving overall health outcomes. Reduced Administrative Burden: The transition to AWS will enable swift deployment of AI-powered solutions that reclaim thousands of hours for WellSpan’s clinical and corporate teams, allowing them to focus on patient care rather than paperwork. Elastic Infrastructure: Cloud architecture will enable WellSpan to scale computing resources dynamically, supporting seasonal demand fluctuations without infrastructure investments, as well as the rapid deployment of new services across multiple locations simultaneously. Most Secure, Compliant Cloud: AWS offers the highest network availability of any cloud provider, with more than 166 HIPAA-eligible services and certifications for global compliance standards, including HITRUST CSF. Built-in AI governance and responsible AI frameworks ensure that WellSpan’s data is protected under the industry’s most rigorous standards. Tags:News releaseInnovation and partnerships
Here are the biggest announcements coming out of CES 2026 in Las Vegas
Here are the highlights from the world's largest technology trade show happening in Las Vegas, including a new Nvidia chip architecture.
❝After a year of disruption, global health needs leaders with backbone
Funding shocks, political U-turns and weakened institutions have laid bare the flaws in a global health architecture long overdue for reform – and the need for courageous leadership to stop it from unravelling, writes Priti Patnaik, global health journalist and founder of the Geneva Health Files.
❝After a year of disruption, global health needs leaders with backbone
Funding shocks, political U-turns and weakened institutions have laid bare the flaws in a global health architecture long overdue for reform – and the need for courageous leadership to stop it from unravelling, writes Priti Patnaik, global health journalist and founder of the Geneva Health Files.
Did one line in a Leonardo codex anticipate yakisugi?
The Japanese technique of burning wood surfaces creates a protective carbonized layer in bioarchitecture.
Samsung Exynos 2600 Xclipse 960 GPU said to use AMD RDNA4-derived architecture
Report claims Exynos 2600 uses MGFX4 RDNA4-derived graphics Samsung's Exynos 2600 is the first Exynos chip said to use an AMD RDNA4-based GPU
Scientists build 'most accurate' quantum computing chip ever thanks to new silicon-based computing architecture
Researchers say they have created the world's first scalable atomic quantum processor that achieves record-breaking 99.99% fidelity.
Breakthrough 3D wiring architecture enables 10,000-qubit quantum processors
The novel 3D wiring architecture and chip fabrication method enable quantum processing units containing 10,000 qubits to fit in a smaller space than today's 100-qubit chips.
Scientists capture most detailed look inside DNA droplets
High-resolution imaging has revealed the internal layout of chromatin condensates, showing how DNA fibers fold and interact within these droplet-like structures. The findings connect molecular architecture to the broader behaviors of these droplets in cells.
Palm-sized Mini PC NAS offers four M.2 bays and dual 2.5GbE ports
Youyeetoo has introduced the NestDisk, a compact mini-PC NAS built around Intel’s Alder Lake-N architecture. The system integrates four M.2 NVMe slots in a chassis similar to an external drive enclosure, targeting home lab, soft routing, and media server deployments. The device is powered by the Intel Processor N150, a quad-core CPU within the Alder Lake-N family. The processor reaches…
Google outlines MIRAS and Titans, a possible path toward continuously learning AI
A year after publishing its Titans paper, Google has formally detailed the architecture on its research blog, pairing it with a new framework called MIRAS. Both projects target a major frontier in AI: models that keep learning during use and maintain a functional long-term memory instead of remaining static after pretraining.
Advancing the America First Global Health Strategy Through Landmark Bilateral Agreements on Global Health Cooperation - United States Department of State
In September, I outlined the Trump Administration’s America First Global Health Strategy, which aims to strengthen U.S. leadership and excellence in global health while eliminating dependency, ideology, inefficiency, and waste from our foreign assistance architecture. Today, I welcomed Kenyan President William Samoei Ruto and Prime Cabinet Secretary Musalia Mudavadi to Washington to sign the first […]
The best history and politics books of 2025
The revolutionary spirit in politics and architecture; histories of free speech and civil war; plus how the Tories fell apart and Starmer won