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Intel Core 3 304 gets close to MacBook Neo's Apple A18 Pro in PassMark
Intel’s entry-level Core 3 304 has appeared in PassMark with scores close to Apple’s A18 Pro used in the MacBook Neo.
Citizen science in Japan’s Ogasawara Islands spotlights ties between ships and birds
A recent study has shed new light on seabirds’ tendencies to follow ships near the island chain and highlights the role wildlife enthusiasts can play in research.
France restricts public alcohol consumption and outdoor sports as heat wave bakes parts of Europe
PARIS (AP) — France is putting emergency services and military forces on wildfire alert, restricting public alcohol consumption and canceling some outdoor sports events to cope with a heat wave unfurling across parts of Europe.
France restricts public alcohol consumption and outdoor sports amid heat wave
France is putting emergency services and military forces on wildfire alert because of a heat wave affecting parts of Europe
Top 15 Kentucky sports moments of 2025-26: No. 6 Cam Miller's hustle
We're counting down the top 15 Kentucky Wildcats sports moments of the last year, and at No. 6 is WR Cam Miller and a game-saving hustle.
It's Official: Zelda Is Returning To The Wilds Era One Final Time
The Breath of the Wild era has been an amazing one for Legend of Zelda fans, and it won't go away without a few more timeless releases.
Kentucky Wildcats News: Tyler Fryman Watch
Good morning, BBN! Kentucky Football’s final weekend of official visits is underway, and while the Wildcats have a loaded group of prospects on campus, one visitor stands out above the rest: in-state wide receiver Tyler Fryman. The Fort Mitchell (Ky.) Beechwood standout is someone Kentucky continues to heavily recruit and looks like the team to […]
Weekend PC Game Deals: Cyberpunk 2077, Split Fiction, Sonic Racing, and more
This weekend's PC game deals include two wildly different freebies to grab, a whole lot of demos to try out on Steam's latest festival, and much more.
'I Want Your Sex' review: Olivia Wilde dominates in salacious and silly comedy
Cooper Hoffman, Mason Gooding, and Charli XCX co-star.
Paddling duo take on 1,000-mile wilderness kayak race
Oliver Smee and Ben Watkins are set to become the youngest pair to take on kayaking's longest race.
Series Preview: Padres kick off interleague matchup with Rangers
The San Diego Padres enter a weekend series with the Texas Rangers looking to maintain control of a wild card spot in a crowded National League playoff picture.
Colman Domingo explains his 'wild' theory about Hitchcock classic 'Rear Window'
Colman Domingo doesn't play about his favorite films, but he does hold one playful theory about the best of his best — 'Rear Window,' which blew the mind of TCM host Ben Mankiewicz.
Colman Domingo explains his 'wild' theory about Hitchcock classic “Rear Window”
Plus, the "Disclosure Day" star tells TCM why he considers Jimmy Stewart his "North Star as an actor."
'What a wild ride': Tony Hawk talks video-game resurgence, love for SoCal
The skateboarder spoke to Spectrum News
Political watchdog fines Newsom for failing to report $5.5M in solicited donations on time
The California Fair Political Practices Commission said most of the violations were for failing to report that Gov. Gavin Newsom and his his staff directed inquiries from companies and foundations to offer help after the Los Angeles wildfires to the California Fire Foundation.
Einstein’s “biggest blunder” may finally have an explanation
Scientists have uncovered a surprising connection between quantum gravity and an exotic quantum state of matter that could explain why the universe isn’t expanding wildly fast. The study suggests that the very shape of space-time may protect the cosmological constant from disruptive quantum effects.
Wildlife inside Chernobyl exclusion zone acted differently during Russia's invasion, camera traps reveal
Camera footage in Ukraine's Chernobyl exclusion zone revealed that mammals became less active — especially at night — during the Russian occupation, highlighting the war's immediate impact on wildlife.
What are the health implications of the Everglades wildfires, and will World Cup spectators and players be affected?
Dr. Roberto Lucchini works with first responders exposed to carcinogens in the World Trade Center attacks. He discusses how airborne toxins from South Florida fires could impact residents, visitors.
Viewpoint: Our wild places aren't worth sacrificing to politics
Frank Vitale writes, These wildlands are the source of our clean water, clean air, abundant fish and wildlife. They’re a place where we can experience wild nature and they make us better people.
How sports betting became Colorado’s ticket to funding $140 million in water conservation projects
Supporters say the gambling money is a godsend. Critics say legalized sports betting has come at a cost — fueling an addiction crisis that Colorado is unprepared for.
A Wild Rumor Linked To Sundar Pichai Suggests Google Is “Evaluating” The Procurement Of Memory Chips From China’s CXMT
Google's move might upend the monopolistic dynamics in the memory sphere by opening a floodgate of similar DRAM deals with CXMT.
Olivia Wilde reveals moment she realized Jason Sudeikis romance was over
Olivia Wilde can pinpoint the precise day she realized her relationship with Jason Sudeikis was over.
Olivia Wilde knew her relationship with Jason Sudeikis was over when he asked her this
Filmmaker and actress Olivia Wilde said that she knew her relationship with ex-fiancé Jason Sudeikis was over when he asked her this cutting question.
Kentucky fans can enjoy games at new Walk-On's, KSR sports bar site
Walk-On's Sports Bistreaux, is set to open in Lexington in a partnership with Kentucky Sports Radio as a place for fans to watch UK Wildcats games.
Raccoon in Anne Arundel County tests positive for rabies; health officials seek anyone exposed
The Anne Arundel County Department of Health is looking for anyone who may have come in contact with a raccoon on or near McGill Court and Milburn Circle in Pasadena after the animal tested positive for rabies.
📝 2026 World Cup, overnight round-up
Every morning, OneFootball will bring you a full recap of the night at the World Cup. Get ready, because last night was wild!The can't-miss story of the nightHow could we talk about anything other tha...
Latvia pilots citizen engagement in research grant evaluations
Latvia has introduced an element of citizen engagement to the evaluation of nationally funded research grants. The aim is to both create more connections between science and society, and to improve the quality of its evaluations. The move comes as research funders across Europe are experimenting with ways to improve evaluation processes in the face of a sharpened focus on science’s impact on society. Evaluators of grant applications submitted to Latvia’s Fundamental and Applied Research Programme (FLPP), the country’s main research funder, will this year have the option of consulting citizen feedback on challenges the public thinks science should focus on to inform their decisions. “In recent years, both public discussions and policy-level debates in Latvia have highlighted the importance of demonstrating how publicly funded research contributes to society, the economy and the resolution of real-world challenges,” said a source at the Latvian Council of Science (LCS), which manages the FLPP. “At the same time, research institutions themselves expressed interest in improving the project evaluation framework while continuing to ensure that funding is awarded to the highest-quality projects,” the source added. The citizen input comes from a survey that was conducted between 25 February and 16 March 2025, to which 1,737 people responded. It gathered information on what the public views as problem areas for Latvia, and the role of science and technology in providing solutions to these problems. A summary of these responses has been included as an annex to the FLPP 2026 call for proposals that evaluators can refer to, purely in an advisory manner, when judging proposals. Results from the survey show that the main problem areas identified by the public were in healthcare and public health, followed by the development of new treatment methods and medicines, and then digital technology, data security and cyber security. At the bottom of the list was research aimed at acquiring new knowledge about the universe, matter and the laws of nature. Further analysis looked at the public view of the possible role of science in solving these problems. The survey charted 4,167 individual responses based on open-ended questions that were derived from the participants’ answers. The analysis again found that medical and health sciences topped the scoring, with 788 responses referring to the field. Humanities and the arts were bottom of the list, with 625. Digging further into the details, the survey suggests citizens are aware of and concerned about a number of research areas. This includes technologies and innovation to improve the environment or reduce pollution, the development of modern military technologies and cybersecurity tools, and the development and application of artificial intelligence, among others. “We hope this initiative will help strengthen public trust in science and create a more meaningful dialogue between researchers and society,” the LCS source said, adding that it offers benefits to researchers, evaluators and to the general public. More space for citizen engagement in evaluationsThere is a gradual but increasing use of citizen engagement in research evaluation processes around Europe, especially in healthcare, but it remains relatively rare, said Henry Sauermann, a professor at the European School of Management and Technology in Berlin and an expert in citizen science.“Given that we are at a point where citizen involvement is extremely limited, there is presumably space for more, but it's not that we should do it just because we want to do it,” he told Science|Business. He said some research lends itself better to having citizen input, and this usually tends to be on the applied end of the science spectrum where the public can offer useful feedback based on their experiences. He added that advising scientists on certain topics to study is also a useful approach, in the way that Latvia is doing. “The public does fund a lot of science, there's a lot of tax money going into this. We of course do want to preserve academic freedom, but it's also not unreasonable to incorporate more feedback or input from citizens where possible,” he said. Related articlesCitizen science: where, when, and how to let the public contribute to researchHow can Europe cope with a flood of AI-assisted research grant proposals?Data Corner: Horizon Europe’s AI, digital and data call success rate is 5.2%There are several ways of involving citizens in science funding. The most minimal way is having a few representatives on a panel, such as members of a patient group or union. The most direct way is crowdsourcing funding for specific projects. There is an increasing number of online platforms that allow the public to chip in to support scientific proposals.Sauermann studied this in a recent paper and found that it can have its uses, but it still is not clear if there are benefits to it. There are various assumptions linked to citizen engagement, for example that it increases public trust in science, or that it provides a representative view of what the public thinks about science. These are not necessarily true, Sauermann found. People who participate in engagement activities tend to already be very trusting of science, and, on the whole, it is generally the well-off and well educated who contribute, giving a narrow view of public opinion. On whether citizen input can help manage the increasing number of proposals that are being submitted due to assistance from AI, Sauermann is more sceptical. “The obvious answer to the flood of AI-written proposals is AI-driven evaluation,” he said, adding that it doesn’t mean citizen engagement shouldn’t be a part of evaluations in a well thought-out manner. Southern Denmark’s successful approachOne successful example of citizen engagement in science evaluations was implemented in southern Denmark. Between 2019 and 2025, citizens in the region were invited to vote to fund one of five pre-selected projects in the field of healthcare. The project, called A Healthier Southern Denmark, was a collaboration between regional authorities, the University of Southern Denmark, and two media partners. Over the seven years, there were 75,000 votes and significant public engagement online and on social media. “It was a bit of a wild project, we’d never done something like that before and we were a bit nervous about what would be said in the media about it. But actually, people were very positive,” said Anne Kathrine Overgaard, one of the main organisers of the project from the University of Southern Denmark. The university and its researchers have learned a lot from the experience, particularly about engaging with society and shaping their research to match real-world needs. This is important with Europe’s increasing focus on competitiveness and bringing innovations to market faster, Overgaard said. She hopes to see more citizen engagement in evaluation processes and in science more broadly. “For many years, citizen engagement has been a bit of an add-on to proposals, just to check a box. But I think things are changing,” she said. It’s less about citizens just gathering data and more “about the dialogue between the public and the scientists,” she said. The initiative ended last year as the team wanted to regroup to find fresh momentum. The development of AI and AI-written proposals has made Overgaard reflect on how the project could be reworked to help evaluators. She hopes to bring it back in the future. “It could be a good idea to try this initiative again in a slightly re-worked format,” she said.
Serena and Venus Williams handed Wimbledon doubles wildcard
watch the ATP and WTA Tours live on Sky Sports Tennis and Sky Sports+, streaming service NOW and the Sky Sports app
At a UFC watch party, cheers for the fight and dismay over the war in Iran
The frustration of a young crowd at a Buffalo Wild Wings in Pennsylvania shows why President Donald Trump was under pressure to end the conflict.
Dr. Picklestein’s wild ride: living a dual life of chemistry professor and K-12 science celebrity
Eggs, rubber chickens, liquid nitrogen, boiling water, canning wax, plastic bottles and a very old...
Xbox Game Studios boss Craig Duncan steps down
The head of Xbox Game Studios Craig Duncan has stepped down after more than 18 months in the role. Duncan replaced former Studios boss Alan Hartman in November 2024, and oversaw Halo Studios, The Coalition, Flight Sim, Turn 10, Playground Games, Rare, Obsidian, Ninja Theory, Compulsion Games, The Initiative, Double Fine, InXile, Undead Labs, World’s Edge and XGS Publishing. He departs the organization this week. His studios will report to Xbox Chief Content Officer Matt Booty until a replacement is found. Duncan has been part of the Xbox organization since 2011 and is best known for running highly regarded UK developer Rare for nearly 14 years. He oversaw the developer’s Kinect and Sea of Thieves eras. Prior to that, he held various senior roles at Codemasters, Midway and Sumo Digital, and worked cross titles such as Sonic and Sega All-Stars Racing, Wheelman and Colin McRae. He's also VP of the charity SpecialEffect. Subscribe Meanwhile, Xbox Game Studios chief of staff Louise O’Connor will also be leaving the company. O’Connor joined Rare in 1999 beginning as an animator on cult favourite N64 game Conker’s Bad Fur Day. She’s worked in numerous art and production roles at the UK studio, and even won an AIAS award for voicing the character Leafos in Viva Piñata. She left Rare following the cancellation of Everwild in 2025, before becoming chief of staff in September that year. In an email to staff, Duncan wrote: “When I stepped into the role of leading XGS 20 months ago, my purpose was to serve our studios, our teams, and the people making our games. Together, we set out to deliver high-quality games, strengthen the cultural fabric across our studios, and help shape the future of the business. I’m proud to say we delivered many flawless launches that drove business success for the company.” On O’Connor, he added: “Louise has been a thoughtful, creative, and trusted partner who has consistently championed the craft and supported our studios with clarity and care. I’m grateful for everything she’s brought to XGS, and I’m sure she’ll be successful in whatever comes next for her.”
Xbox Game Studios boss Craig Duncan steps down
The head of Xbox Game Studios Craig Duncan has stepped down after more than 18 months in the role. Duncan replaced former Studios boss Alan Hartman in November 2024, and oversaw Halo Studios, The Coalition, Flight Sim, Turn 10, Playground Games, Rare, Obsidian, Ninja Theory, Compulsion Games, The Initiative, Double Fine, InXile, Undead Labs, World’s Edge and XGS Publishing. He departs the organization this week. His studios will report to Xbox Chief Content Officer Matt Booty until a replacement is found. Duncan has been part of the Xbox organization since 2011 and is best known for running highly regarded UK developer Rare for nearly 14 years. He oversaw the developer’s Kinect and Sea of Thieves eras. Prior to that, he held various senior roles at Codemasters, Midway and Sumo Digital, and worked cross titles such as Sonic and Sega All-Stars Racing, Wheelman and Colin McRae. He's also VP of the charity SpecialEffect. Subscribe Meanwhile, Xbox Game Studios chief of staff Louise O’Connor will also be leaving the company. O’Connor joined Rare in 1999 beginning as an animator on cult favourite N64 game Conker’s Bad Fur Day. She’s worked in numerous art and production roles at the UK studio, and even won an AIAS award for voicing the character Leafos in Viva Piñata. She left Rare following the cancellation of Everwild in 2025, before becoming chief of staff in September that year. In an email to staff, Duncan wrote: “When I stepped into the role of leading XGS 20 months ago, my purpose was to serve our studios, our teams, and the people making our games. Together, we set out to deliver high-quality games, strengthen the cultural fabric across our studios, and help shape the future of the business. I’m proud to say we delivered many flawless launches that drove business success for the company.” On O’Connor, he added: “Louise has been a thoughtful, creative, and trusted partner who has consistently championed the craft and supported our studios with clarity and care. I’m grateful for everything she’s brought to XGS, and I’m sure she’ll be successful in whatever comes next for her.”
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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The DRAM crisis is making entry-level laptops more and more expensive – or forcing manufacturers to use very old components. Intel Wildcat Lake and Project Firefly are set to change this and provide serious competition for the Apple MacBook Neo. Intel now reveals more details about Project Firefly.
Intel’s Project Firefly Takes The Best of Phones To Build Laptops In A Slim 12.9mm Metal Chassis With No Vents
Intel's Project Firefly aims to deliver premium-grade budget laptops with Wildcat Lake SoCs and a metal chassis, targeting affordability.
Pollinators in peril: scientists reveal the hidden human health costs of the world’s disappearing bees
Crops and flowers rely on them for survival, but wild bees are declining – and crucial nutrients will go missing from our diets as a result
NBA legend Charles Barkley makes wild Cardi B joke during Spurs-Knicks playoffs game
NBA legend Charles Barkley made a wild joke about Cardi B at the San Antonio Spurs-New York Knicks playoffs game as the rapper performed at halftime.
Chrome V8 Zero-Day CVE-2026-11645 Exploited in the Wild
Google released security updates for 74 Chrome vulnerabilities, including CVE-2026-11645, a high-severity V8 out-of-bounds memory access flaw.
‘You have to adjust:' Chris Kuper outlines his plans to replace Jeff Stoutland
Chris Kuper’s job description is coaching the Eagles’ offensive linemen. His initial challenge is getting them to believe he can do it.
Google patches new Chrome zero-day flaw exploited in the wild
Google has released emergency updates to patch another Chrome zero-day vulnerability that has been exploited in the wild, the fifth such flaw patched since the start of the year.
Palmetto Sports Daily: Gamecock baseball coaching search heats up, Stanley Cup Final gets wild
Julia, Caroline and Bronwyn talk about the latest in the South Carolina baseball coaching search and recap a wild Game 3 of the Stanley Cup Final.
'The Last of Us' fans can breathe easy, the series isn't canceled
'The Last of Us' fans had a scare when online rumors spread that the wildly popular HBO post-apocalyptic drama had canceled filming.
Sports Wrap, June 7: Teasley news conference, Vikings minicamp week, Twins, Lynx, and Dylan Larkin rumors
In case you missed it: Our Chris Long, Darren 'Doogie' Wolfson, and Alec Ausmus went back-and-forth Sunday night on Sports Wrap. The Vikings, Twins, Lynx, and Dylan Larkin to Wild trade rumors all came up.
All-new Lab in Kenya Fills Critical Gap in Wildlife Health
/PRNewswire/ -- Conservation stakeholders gathered to celebrate the official opening of the Laboratory in Northern Kenya (LiNK), an all-new veterinary...
Trump’s birthday spectacle contrasts wildly with Biden’s understated 80th
Their birthday plans reflect their personalities — and the shifting politics of the moment, as brash self-promotion has become a political asset.
Finding Nemo: Scientists Use AI To Catch Illegal Marine Wildlife Traffickers
Hidden inside luggage, children's toys and parcels, trafficked shark fins, seahorses and sea cucumbers often slip across borders unnoticed. Now researchers in Australia have trained an AI system to recognize these marine wildlife products in airport CT scans with 92% accuracy.
Xbox Fans Go Wild As Asha Sharma Gives Free Consoles To Everyone At FanFest LA
Watch the reaction here
Lane County warns businesses to be ready for increased wildfire danger
As a potentially active fire season nears, officials say business owners should ensure they are as ready at work as they are at home.
Monster Hunter Wilds confirmed for Nintendo Switch 2
Monster Hunter Wilds is coming to Nintendo Switch 2.
Entertainment: Subtronics to Wet 'N' Wild; Unreleased Prince songs
Subtronics plays Cyclops Island at Wet’n’Wild tonight at 5 p.m., with live music, food, drinks and select attractions.
Spencer Pratt's Race for Mayor Shows How Climate Disasters Can Fuel Anti-Establishment Politics
Research has long shown that poorly managed disasters foment distrust in institutions.
Monster Hunter Wilds Is So Back With Big Ascendance Expansion
Capcom is all in on supporting Nintendo's latest handheld hybrid
Wayans brothers“ ”break down “Scary Movie”'s wild post-credits parodies of these 2 horror hits
Please welcome "Short Hand" and "Brosferatu" to the canon of horror spoofs.
Wildlife ecologist says her favorite science talk this year was in her children's classroom
"The kids are alright, and they sure are ready to protect the natural world into the future."
Peptide Injections Touted as ‘Fountain of Youth.’ Spoiler Alert: They’re Not
Wellness peptides have become wildly popular despite lacking credible evidence for their safety and effectiveness. Here's why experts advise against using compounded peptides for health and fitness.
Scientists map more than 200 years of nature's progress
Armed with trail cameras, artificial intelligence, and a powerful national research network, scientists are revisiting Lewis and Clark's legendary journey to see how America's wildlife has changed over ...
Monster Hunter Wilds confirmed for Nintendo Switch 2
After it was heavily rumored for the platform, Monster Hunter Wilds has finally been confirmed for Nintendo Switch 2. A release date will be given later. Many fans thought that Capcom was tinkering with a port following a datamine. However, this is the first time a port has been officially acknowledged. Monster Hunter Wilds initially launched last year. Here’s an...
RuneScape: Dragonwilds Soars onto XBOX on September 15, 2026
Adventure across a beautiful, high-fantasy world in RuneScape: Dragonwilds, coming to Series X|S September 15, 2026.
Capcom Shines Bright With Massive Reveals at Summer Game Fest 2026
'Resident Evil Veronica' announcement, 'Monster Hunter Wilds: Ascendance', and who to look out for in 'Street Fighter 6' Year 4.
Even the RuneScape Spinoff Is Coming Out in September
Add another game to the September pileup: RuneScape: Dragonwilds is due out on PC, PlayStation 5, and Xbox Series X and S on September 15, 2026.
Kentucky now knows their opponent in the ACC/SEC Challenge
The Kentucky Wildcats now know who they will play in the 2026 ACC/SEC Challenge, an annual matchup between the two conferences.
Boston Celtics insider drops surprising Giannis Antetokounmpo reality check
The Boston Celtics have emerged as a potential wild card in the Giannis Antetokounmpo trade conversation. Following Jaylen Brown’s unusual comments on Twitch after Boston’s postseason exit, some around the league have speculated that he may be open to seeking a situation where he can lead his own team. Antetokounmpo has also been mentioned as [...]
Scientists race to collect the last seeds from a critically endangered tree before it goes extinct
Seeds from the last surviving wild Dendroseris neriifolia tree are now stored in Kew Gardens' Millennium Seed Bank as researchers work to find ways to reintroduce the species into the wild.
Wild card for SpaceX is the AI business, says NYU finance professor Damodaran
Aswath Damodaran, NYU School of Business, joins 'Closing Bell' to talk SpaceX IPO valuation.
What a toy whale tells Pacific Northwest scientists about the potential for renewable tidal energy
Northwest researchers are working to understand the impact of underwater tidal energy turbines on wildlife.
The Knicks’ grimy Game 1 win, plus a World Cup retrospective
The Pulse Newsletter 📣 | This is The Athletic’s daily sports newsletter. Sign up here to receive The Pulse directly in your inbox. Good morning! Embrace the grime today. Coming up: 🗽 New York’s moxie 🌬️ Sabalenka’s collapse 👨🏻🦲 Wildest World Cup moments One thought raced through my head every time I watched a New York Knicks possession in the fourth quarter last night: These dudes are grimy. I mean that as a huge compliment. There’s grit, and then there’s grime. Every bucket, every rebound, every screen oozed difficulty, as if each player was...
Rabies Makes Its Return to Wyoming - Wyoming Department of Health
As summer approaches and temperatures rise, the Wyoming Department of Health (WDH) is warning residents about wild animals that may carry rabies. The most common carriers of rabies in our state are bats and skunks, but any mammal can be infected with rabies, including humans. The first confirmed case of rabies for 2026 occurred […]
Exploring the night sky with author Craig Childs
On July 31 we'll discuss Childs's book, "The Wild Dark," his adventure in the desert, and why darkness matters.
Los Angeles Mayor Karen Bass advances to November runoff as she seeks second term
Spencer Pratt, a Republican and former star of the reality television show “The Hills,” was second in early returns. Pratt accuses Bass of letting wildfires get out of control and failing to make enough progress on the homeless crisis.
ENTERTAINMENT: ‘Music’ at Wildwood; ‘Aftermaths’ exhibit opens at AMFA Saturday
"Aftermaths: Mat Collishaw," featuring the latest film from British painter, photographer, sculptor and filmmaker Mat Collishaw, opens Saturday in the Fine Arts Club New Media Gallery at the Arkansas Museum of Fine Arts.
Jason Sudeikis calls dating 'daunting' following Olivia Wilde split in rare comment about personal life
Jason Sudeikis finds dating 'daunting,' he says, six years after he and Olivia Wilde ended their engagement.
Tomb Raider: Legacy of Atlantis comes with an AI disclaimer
It has emerged that Tomb Raider: Legacy of Atlantis' developers Crystal Dynamics and Flying Wild Hog have used AI in the game's development.
San Francisco's wild housing market: AI boom sends home prices soaring
Overnight AI fortunes, multimillion-dollar bidding wars, and looming IPOs are rocking San Francisco real estate and sending home prices soaring.
Rockies' TJ Rumfield hits home run off Jo Adell's head in wild botched catch in win over Angels
Jo Adell missed the fly ball, which went through his glove and off his head before clearing the wall at Angel Stadium on Tuesday night.
NCAA Men’s Golf: Arizona falls to UCLA in semifinals
Arizona men’s golf’s best postseason in decades ended just short of competing for a national championship. The Wildcats fell to UCLA in the NCAA semifinals Tuesday at Omni La Costa Resort in Carlsbad, Calif. after knocking off Vanderbilt earlier in the day in quarterfinals action. Arizona’s run to the semifinals marks the program’s best finish […]
RuneScape: Dragonwilds Launches on Consoles Later in 2026, Sony Picks Up Spinoff for PS Plus
RuneScape: Dragonwilds launches on PlayStation 5 later in 2026, developer Jagex has announced, marking the first time the RuneScape IP has made the jump from PC to consoles in its 25-year history.
Oregon’s Dante Moore among cover stars for EA Sports College Football 27
The wildly popular college football video game will prominently feature the Ducks quarterback on the cover.