SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " track " 2,483 found 🔀 AI-powered Shuffle
Fallout from USMNT loss to Turkey and previewing the Mbappe-Haaland clash
On today’s show, we look back at the United States’ final group stage match against Turkey and evaluate their readiness for the Round of 32. Manchester City insider Sam Lee joins us to preview the tournament’s first true superstar heavyweight clash as Kylian Mbappe and France square off against Erling Haaland and Norway in a battle for Group I supremacy. Plus, The Athletic’s Jay Harris is back in the studio to break down the latest bracketology, advancement percentages, and qualification permutations for Groups G, H, and I using The Athletic’s World Cup Tracker.
Meet a scientist tracking invasive reptiles, and even their parasites
An insider's look at Florida’s war on invaders: the giant snakes, egg-eating predators and parasites spreading through the Everglades.
Good Sports: Former Bulldog track and field athlete aims to be flag football Olympian
Last June, Kaja Bins didn't know what flag football was. Kaja now has the potential to become an Olympian in a sport she learned a year ago.
World Cup 2026 Round of 32 tracker: Who’s qualified, who’s eliminated and who’s still alive
THE NEXT GENERATION TAKES THE TRACK: COPACI AND PANAM SPORTS LAUNCH ELITE CYCLING DEVELOPMENT CAMP IN TRINIDAD AND TOBAGO
Young cyclists from across the Caribbean are gathering in Trinidad and Tobago […]
Nintendo Switch 2 ends first full year in the U.S. at nearly 6 million units sold, second fastest-selling video game system
Following the latest U.S. sales report from Circana, we have information about the first full-year sales of Nintendo Switch 2. The console ended its first twelve months at 5.9 million units sold. According to Circana, it’s the second fastest-selling video game system in the U.S. with tracked history dating back to 1995. The only other platform to outdo it was...
NASA's canceled Artemis hardware contracts reached $5.9 billion, audit finds
NASA was on track to pay nearly half a billion dollars for a stage adapter. A stage adapter should not cost half a billion dollars.
It's Summer Sale Season, So I Tracked Down 25 Actually Good Gaming Deals Under $20
There's a million sales happening right now, so I sifted through them all to find 25 genuinely solid gaming deals that are each under $20.
Target rolls out new attendance tracking system for workers
Target's new point-based attendance tracking system rolls out in the coming months, the latest of several changes aimed at improving store operations.
Apple has new ‘iRing’ wearable product in the works, says leaker
Leaker Kosutami says an Apple ‘iRing’ is now in development to compete with other health trackers like Oura’s smart ring.
Can your smartwatch detect sleep apnea?
No smartwatch can actually diagnose sleep apnea, but some can track certain signs that might indicate you have the condition.
KFF Poll Shows Three in Ten Adults Turn to Social Media or AI for Health Information, with Lower-Income Adults More Likely to Cite Cost and Access Barriers as a Reason
The latest KFF Tracking Poll on Health Information and Trust finds roughly three in ten adults report turning to social media (31%) or AI chatbots (29%) at least monthly for health information and advice. The top reasons people report turning to social media for health advice are wanting to hear from those with similar experiences or a desire for quick information.
iPhone Ultra 2 already given go-ahead, iPhone Air 3 not, says leaker
We may still be waiting for the launch of the iPhone Ultra, but a leaker with a decent track record...
ADUSA tapped a former Amazon exec to helm its business. What does this mean?
The grocery company’s nominee for the top role may raise some eyebrows given Amazon’s brick-and-mortar track record, but Claire Peters' appointment could be the key to further omnichannel growth.
Folarin Balogun and USMNT Transfer Updates
Hosts Tamerra Griffin and James McNicholas break down a massive six-match World Cup slate as group stages reach their climax. Soccer insider David Ornstein joins the show to discuss the escalating transfer market buzz surrounding USMNT star Folarin Balogun and Tottenham’s Lucas Bergvall. Plus, the team highlights The Athletic’s interactive World Cup Tracker with Jay Harris to map out the complicated qualification pathways for Group A, B, and C. Can the USMNT line up a favorable Round of 32 matchup? Senior Editor Hannah Vanbiber also dives into the debate surrounding Jeremy Doku’s...
Utah State Joins Mountain Pacific Sports Federation as Affiliate Member in Indoor Track & Field
LOGAN, Utah – Utah State has accepted an invitation to join the Mountain Pacific Sports Federation as an affiliate member in men's and women's indoor track & field, it was announced by the conference on Thursday. Utah State's membership in the conference will be effective on July 1.
2026 NBA draft: Tracking the top undrafted free agent signings
Rookie Wire is tracking the top undrafted free agents following the conclusion of the 2026 NBA draft on Wednesday.
Highlights of Aspen Ideas: Health, day two
On June 23, Aspen Ideas: Health ushered in the actual first full day — and evening — of programming. Here are some highlights from different tracks, or themes. NextGen Health Track: On the Frontiers of Brain Health “As belly size gets larger, the memory center in the brain gets smaller,” said Richard Isaacson, director...
The Trump administration has attacked science 574 times. Track each instance with this online tool
The Union of Concerned Scientists is aiming to visualize the scale of the president's anti-science actions, from censorship to the sidelining of experts.
Galaxy Z Fold 8 Release Date: Samsung Devices Get New Confirmation
Samsung's Galaxy Z Fold 8 Ultra, Z Flip 8 and Watch 9 series have been cleared for U.S. launch, confirming the July Unpacked release date is on track.
Day Two of Competition Highlights Athletes Across Multiple Sports
The second day of competition at the 2026 Special Olympics USA Games was cut short due to inclement weather, but not before some memorable moments. Before outdoor events were halted, athletes showcased speed on the track, excitement and enthusiasm at gymnastics, and pride on the football and soccer fields. Even as an athletics athlete from Special Olympics Southern California lost his shoe, he managed to win the race.
Dave And Buster's Entertainment (PLAY) Stock Sees Fair Value Cut After Q1 Analyst Revisions
The fair value estimate for Dave & Buster's Entertainment has been revised from US$18.88 to US$17.00, bringing the price target closer to updated assumptions on comparable sales and earnings. Analysts link this adjustment to a balance of cautious near term expectations after Q1 and ongoing optimism that longer term changes in the business could still support the story if execution improves. Read on to see how this evolving narrative might shape how you track Dave & Buster's Entertainment from...
I’ve tracked Prime Day for 11 years. These 17 laptop and computer deals are actually worth it
Prime Day is officially here, and our computing expert found some great deals on laptops and computers you can get right now.
Automakers could halt car sales in California without delay in vehicle tracking law
A group representing major automakers warned on Tuesday that car companies may be forced to halt sales of both new and used vehicles in California on July 1 unless the state delays vehicle technology rules that aim to prevent perpetrators of domestic violence from tracking survivors.
Biden judge overruled on key Trump immigration policy
Federal appeals court revives Trump administration's nationwide expedited removal policy, allowing fast-track deportations of eligible illegal immigrants.
2026 World Cup Bracket, Standings, Projections: USA in Round of 32, Who Else Might Advance?
Track the 2026 FIFA World Cup bracket with live standings and Round of 32 projections. See where Team USA stands and who's on track to advance.
VA’s top health official pushes IT overhaul to cut bureaucracy, boost veteran care
As VHA balances cost, disruption and rollout pace across its modernization portfolio, John Bartrum said he's tracking success on two fronts.
NASA satellite captures wave of warm water hundreds of miles long that signals a devastatingly strong El Niño
This year's El Niño is on track to be among the strongest ever recorded.
Trump administration front-loaded science cuts, tracking tool reveals
The Union of Concerned Scientists' new tool documents administration rollbacks in rulemaking, personnel and funding.
Master’s Program Revamped to Address Informatics Needs
The Master of Science in Biomedical Informatics program — previously known as the Master of Science in Health and Biomedical Informatics — will launch in the fall offering two tracks: one in bioinformatics and another in health informatics.
EIGHT JAGUARS EARN COLLEGE SPORTS COMMUNICATORS ACADEMIC ALL-DISTRICT HONORS
INDIANAPOLIS - Eight members of the IU Indianapolis men's and women's cross country and track and field programs were named College Sports Communicators Academic All-District on Tuesday (June 23) for their work in competition and in the classroom. Six members of head coach Justin Amburgy's men's squad were honored while two student-athletes from head coach Antonio McDaniel's women's team were recognized.
Four Hawks Named to College Sports Communicators Women's Track & Field / Cross Country Academic All-District Team
WEST HARTFORD, Conn. - On Tuesday, the College Sports Communicators (CSC) Academic All-District Track & Field / Cross Country teams were announced with four members of the Hartford women's track & field featured.
Cannes Lions International Festival of Creativity announces winners across the Entertainment and Craft Track Lions
Cannes Lions International Festival of Creativity announces winners across the Entertainment and Craft Track Lions
Rice Business launches early career track within MBA@Rice Online Program
Rice Business today announced the launch of a new Early Career Track within its MBA@Rice Online MBA program. The new track gives high-potential professionals with less than three years of work experience a path to earn their MBA earlier in their careers. The program will launch with the October cohort and applications are open now.
Huge Amazon Prime Days 2026 Sports Tech Deals Tracker!
Here's your complete Amazon Prime Days 2026 Sports Tech Gear Guide, covering 100+ sports tech product deals!
I’ve tracked Prime Day for 11 years. These 7 laptop and computer deals are actually worth it
Prime Day is officially here, and our computing expert found some great deals on laptops and computers you can get right now.
Most Americans now 'insecure' or 'desperate' in getting, affording health care: Gallup
Fewer than half of Americans can consistently access and afford the health care they need for the first time in Gallup tracking.
Most Americans now 'insecure' or 'desperate' in getting, affording health care: Gallup
Fewer than half of Americans can consistently access and afford the health care they need for the first time in Gallup tracking.
Pennsylvania Gov. Josh Shapiro on new fast track business development and company investments
Gov. Josh Shapiro (D-Pa.) joins 'The Exchange' to discuss business development in the state, taxes in the state and more.
Apple Wallet in iOS 27 adds new feature for tracking your money
Apple Wallet in iOS 27 adds a handful of welcome new features, and today’s beta 2 brought another—Insights—to US users. Here are the details.
Apple’s latest AirTags are cheaper than ever for Prime Day
The four-pack is down to $90, marking the first major discount on Apple’s new item trackers.
New Apple TV 4K is coming this fall with three new features: report
The wait for a new Apple TV 4K has been longer than expected, but it’s reportedly on track for a fall launch with three new features.
Citizen science is the key to F&G’s hugely successful program, Turkey Tracker
Idaho Fish and Game’s hugely successful project — dubbed Turkey Tracker — launched in the summer of 2024. During its inaugural two years, the project has racked up 2,157 reports of over 15,000 turkeys, all thanks to the public.
Every Apple Watch Model Hits Its Lowest Price Ever for Prime Day
Prime Day deals are already in full swing today, despite the event not kicking off until tomorrow, June 23. Below we're tracking all-time low prices across the Apple Watch lineup, including Apple Watch Series 11 for $120 off, Apple Watch SE 3 for $50 off, and Apple Watch Ultra 3 for $150 off. Note: MacRumors is an affiliate partner with Amazon. When you click a link and make a purchase, we may receive a small payment, which helps us keep the site running.
Wyze Scale BodyScan tracks more than just your weight, has Google Health support, $79.98
Wyze is today launching a new scale that tracks more than just your weight while also being affordable, with the...
Osaretin Osagie Named NE10 Sport Excellence Award Winner
Southern Connecticut State University men's track & field All-American Osaretin Osagie was named the 2026 Northeast 10 Conference Outdoor Track & Field Sport Excellence winner, as announced by the NE10 on Friday, June 19.
Reader wants to know what happened to Tennessee's football museum
David says why my football/track plan won't work. Randy revives memories of Peyton Manning wax statue. Jimmy predicts end of Josh Heupel era.
Katy Growth Tracker: New Restaurants, Entertainment Expansion and 348-Unit Apartment Project
Several commercial and residential development projects are moving forward across the Katy area, including new restaurants, an entertainment venue expansion and a large apartment community planned in Jordan Ranch.
The public health team watching the World Cup
As millions gather for the World Cup, a scrappy public health operation led by a team at Georgetown is tracking disease threats using surveys, wastewater and online chatter to spot outbreaks early.
Vance meets top Iranian officials as US looks to get negotiations back on track
U.S. Vice President JD Vance and top Iranian officials are trying to build out the interim deal to end the war in Iran reached by the two sides last week. They are meeting at a Swiss mountainside resort near Lake Lucerne.
Nearly All EAE Business School Grads Found Jobs In 2025, With Salaries Growing 70%
Spanish school's employment report tracks grads across master's & MBA programs, finding a pronounced tendency to ‘triple jump’.
Vermont’s Governor Scott vetoes Legislature’s attempt at healthcare reform
The bill was designed to fast-track premium savings for public school employees and people buying plans on Vermont’s Affordable Care Act marketplace.
FULL SHOW: Inside INdiana Business 6/21/26
.video-js, .video-js .vjs-tech { position: relative; width: 100%; height: auto; z-index: 0; } var player = videojs('player_block_b08a815d951c2b8f2effb3e301b14dfe'); player.nuevo({ contextMenu: false }); var vast = { started: false, paused: false, resumed: false, ended: false, }; var video = { started: false, paused: false, resumed: false, ended: false, } var event_label = 'Video: 204053 - Article: FULL SHOW: Inside INdiana Business 6/21/26'; var post_id = 204052; var post_url = "https://www.insideindianabusiness.com/videos/full-show-inside-indiana-business-6-21-26"; player.vastAds({ tagURL: "https://servedbyadbutler.com/vast.spark?setID=13487&ID=177008&pid=117129", id: "PreRoll" }); player.on('vast.adStart', function() { vast.started = true; }); player.on('vast.adError', function() { vast = { started: true, ended: true }; }); player.on('play', function() { if (vast.ended && !video.paused) { video.started = true; window.dataLayer.push({ event: "Videos", eventCategory: 'Video', eventAction: "Video Played", eventLabel: event_label }); var audio_insight_data = { event_type: "video_played", data: { video_id: post_id, video_url: post_url }, ...insight_data, }; insight.track(audio_insight_data); } if (video.started && video.paused) { video.resumed = true; window.dataLayer.push({ event: "Videos", eventCategory: 'Video', eventAction: "Video Resumed", eventLabel: event_label }); var audio_insight_data = { event_type: "video_resumed", data: { video_id: post_id, video_url: post_url }, ...insight_data, }; insight.track(audio_insight_data); } }); player.on('pause', function() { if (vast.ended) { video.paused = true; window.dataLayer.push({ event: "Videos", eventCategory: 'Video', eventAction: "Video Paused", eventLabel: event_label }); var audio_insight_data = { event_type: "video_paused", data: { video_id: post_id, video_url: post_url }, ...insight_data, }; insight.track(audio_insight_data); } }); player.on('ended', function() { //vast.adEnd fires after ended, pointless to use. vast.ended = true; if (video.started && !video.ended) { video.ended = true; window.dataLayer.push({ event: "Videos", eventCategory: 'Video', eventAction: "Video Ended", eventLabel: event_label }); } var audio_insight_data = { event_type: "video_completed", data: { video_id: post_id, video_url: post_url, percentage: 100, }, ...insight_data, }; insight.track(audio_insight_data); }); player.on('fullscreenchange', function() { window.dataLayer.push({ event: "Videos", eventCategory: 'Video', eventAction: "Video Fullscreen Toggled", eventLabel: event_label }); }); player.on('enterpictureinpicture', function() { window.dataLayer.push({ event: "Videos", eventCategory: 'Video', eventAction: "Video Picture-in-Picture Opened", eventLabel: event_label }); }); player.on('leavepictureinpicture', function() { window.dataLayer.push({ event: "Videos", eventCategory: 'Video', eventAction: "Video Picture-in-Picture Closed", eventLabel: event_label }); }); let lastReportedPercentage = 0; player.on('timeupdate', function() { const currentTime = player.currentTime(); const duration = player.duration(); if (duration) { const progressPercentage = Math.floor((currentTime / duration) * 100); if (progressPercentage % 5 === 0 && progressPercentage !== lastReportedPercentage) { lastReportedPercentage = progressPercentage; var audio_insight_data = { event_type: "video_completed", data: { video_id: post_id, video_url: post_url, percentage: progressPercentage, }, ...insight_data, }; insight.track(audio_insight_data); } } });
Spain target convincing win to dispel World Cup doubts
A wounded Spain will aim to get their World Cup challenge firmly back on track when they face Saudi Arabia in Atlanta on Sunday.Saudi Arabia also drew their opening game 1-1 with Uruguay.
Jack Whitehall joins Silverstone F1 comedy line-up
The Northamptonshire circuit announces the "final layer" of its off-track entertainment for 2026.
1980's 'That's Entertainment' by The Jam: Written in Just 10 Minutes
The track became one of the rock band's most acclaimed songs.
Dirt on Dirt - Salina gives Davenport another MLRA sweep
DirtonDirt.com covers Dirt Late Model racing like no other publication, magazine or website with massive amounts of original content including videos, photos, stories, columns, blogs and more. Eldora Speedway's World 100 and Dream, the Dirt Track World Championship, Lucas Oil Late Model Knoxville Nationals and all the major races are covered along with the major tours, including the World of Outlaws Late Model Series and Lucas Oil Late Model Dirt Series.
Cardinal Health (CAH) Stock Could Be 9.6% Undervalued Despite Rich P/E Signals
Cardinal Health (CAH) has drawn investor attention after its stock closed at $221.77. This has put recent performance and current valuation metrics in focus for those tracking large U.S. healthcare distributors. See our latest analysis for Cardinal Health. While Cardinal Health’s share price slipped around 2% in the latest session, the 30-day share price return of 10.55% and 1-year total shareholder return of 37.25% sit alongside a very large 5-year total shareholder return of 334.47%. Taken...
Doom soundtrack composer Bobby Prince dies aged 81
Robert Prince III – best known as Bobby Prince, the man behind the iconic score of the original Doom game – has died aged 81.
Halo PS5 Backtracks PS Plus Co-Op Demands, Says They Were a Mistake
PSN account needed for both players
Overemployment survives RTO mandates, layoffs, and employee monitoring
Return-to-office mandates, layoffs, and employee tracking have made overemployment harder. These workers say they're still making it work.
Olympian Jenny Simpson shows 'encouraging improvement' after collapse
The 39-year-old Simpson underwent CPR at a track Tuesday and was taken to the hospital.
Carmen Electra reveals why she loves the Prince diss track that 'everyone knows is written about me'
Carmen Electra is looking back on her relationship with Prince, from their brief love affair, to the album they made together in 1993, to the diss track she swears 'everyone knows' was written about her.
Oakes Farms withdraws plans for new Bonita Springs entertainment complex
Oakes Farms has withdrawn its proposal to transform the old greyhound track in Bonita Springs into an entertainment complex.
Bobby Prince, the composer of Doom’s iconic soundtrack, has died at 81
Prince’s Doom soundtrack was selected for preservation in the Library of Congress this year…
Iran’s ships head homeward to Gulf for ‘business as usual’ after US deal
Tracking data shows cargo vessels departing from Malaysian waters as Washington reaches agreement with Tehran
The best wireless earbuds for iPhone owners, Apple’s AirPods Pro 3 are on rare sale
They cancel noise, track your heart rate, even double as hearing aids, and Apple’s AirPods Pro 3 are on a rare sale right now
Health kicks off Aspen Ideas June 22-25
Since 2014, Aspen Ideas: Health has preceded the Aspen Ideas festivals. This year, from June 22-25, it offers more than 60 sessions with seven program tracks revolving around patient care, new treatments and technology, longevity and vitality, creativity, medical enterprise, leadership and how health-related questions often lack black or white answers.
Android developer verification on track for September, ‘Verifier’ service will soon auto-install
Google today published an update on Android developer verification, which is set for its initial launch later this year and...
Morris County Track Coaches Association spring postseason honors
Who did the Morris County track and field coaches select as the outdoor season's most consistent performers?
Gemini for Android using Bubbles to let you multitask & continue chats
After adding Dynamic Color earlier this month, the Gemini overlay on Android is now using Bubbles to help keep track of conversations.
Researchers found 8 common food additives linked to high blood pressure and heart disease
A major study of more than 112,000 people found that eating foods containing common preservatives may be linked to a higher risk of high blood pressure and heart-related diseases. Researchers tracked participants for up to eight years and discovered that people consuming the highest amounts of certain preservatives had significantly greater risks of hypertension, heart attack, stroke, and other cardiovascular problems.
Waves of lawsuits and internet tracking: CIPA in the digital age
Small businesses are getting sued at an alarming rate for violating internet privacy laws, with one law firm fielding over 500 lawsuits alone citing the California Invasion of Privacy Act.
Pistons 2026 NBA predraft workouts tracker: Every prospect to visit
Tracking the prospects we know have visited the Detroit Pistons for predraft workouts ahead of the 2026 NBA Draft.
Abarca Health and LucyRx Announce Strategic Combination to Create the Only Modern PBM Built for Commercial and Government Scale
Abarca Health and LucyRx today announced a strategic combination to create the only modern, independent pharmacy benefit manager with the scale, technology, and track record to credibly serve commercial and government clients of any size. Combined, Abarca and LucyRx will provide prescription services to more than 9 million members across the United States.
Georgia Republicans backtrack on redistricting plans
After Gov. Brian Kemp called them into a special session, state lawmakers said they didn’t have enough time to draw new maps that would have taken effect for the 2028 elections.
KFF Tracking Poll on Health Information and Trust: Use of Social Media and AI For Health Information and Advice
This poll finds that about 3 in 10 adults turn to social media for health information and advice at least monthly. Community connection and the need for immediate answers are the top reasons why people are turning to these tools. Slim majorities of those who use social media for health are confident they can tell what is true, and relatively few take steps to check the information they receive.
After devastating fire, USF marine scientists race to keep ocean monitoring on track
A fire at the USF Marine Science Laboratory displaced the Ocean Circulation Lab, which maintains its buoy program.
#New40k – New app for a new edition
Share army rules and track game scores in the updated Warhammer 40,000 app.
In the race for AI gold, healthcare is getting left in the dust by finance
If the economy were an inter-sector track meet in which AI adoption propels the runners, healthcare would be getting repeatedly lapped by financial services.
Pizza Hut bought by private equity firm that owns 24 Hour Fitness
P.E. firms have bought up restaurant chains in recent years, but they have a mixed track record when it comes to turning them around.
Google launches Wear OS 7 with Live Updates and a battery life boost
Track your meal delivery from your Pixel watch.
Your Business May Be Too Measurable for Its Own Good. Here's What It's Costing You.
Customers are making more decisions in places metrics can’t fully reach. The result is a growing disconnect between what you can track immediately and what actually shapes buyer confidence.
There’s one big flaw with the AG’s track record on Hawaii Medicaid fraud
However, $13 million came from a single case that began over a decade ago
Dave & Buster's Entertainment, Inc. Stock 12‑Month Price Target Cut to $19.78, Implies 61% Upside
Explore more price target data and ratings for Dave & Buster's Entertainment, Inc. on the Forecasts tab, and track all previous and future analyst recommendations for Dave & Buster's Entertainment, Inc. in the dedicated News Flow.Select reference data provided by FactSet. Copyright © 2026 FactSet R…
Health 'War Room,' Digital Tools Are Tracking Disease Risks During World Cup
Public health experts address the logistical challenge of tracking the health and location of players and fans across 16 World Cup host cities.
GLP-1 and weight-loss drugs: How fast-track health solutions are reshaping FMCG
GLP-1 weight-loss drugs are reshaping FMCG as health, body control, and self-optimization trends redefine consumer behaviour across Europe.
Stop managing your business finances in spreadsheets — QuickBooks is $300 right now
Intuit QuickBooks Desktop Pro Plus 2024 is on sale for $299.99 (reg. $536) for one year. Built for small business owners, freelancers, and accountants, it handles invoicing, expense tracking, inventory, payroll hours, and project profitability reporting.
Dave & Buster's Entertainment, Inc. Stock 12‑Month Price Target Cut to $20.11, Implies 63% Upside
Explore more price target data and ratings for Dave & Buster's Entertainment, Inc. on the Forecasts tab, and track all previous and future analyst recommendations for Dave & Buster's Entertainment, Inc. in the dedicated News Flow.Select reference data provided by FactSet. Copyright © 2026 FactSet R…
Lancaster County measles outbreak garners national attention; 4 new cases in the past week
With measles cases in Lancaster County continuing to rise and the state tracking possible public exposures at the courthouse and a local department store, the outbreak here is attracting national
From Managing Processes to Driving Outcomes: Oracle’s Latest AI Push Aims to Rewire Business
With a new class of enterprise applications that execute end-to-end processes, Oracle is showing how enterprise software has evolved from tracking work to driving outcomes.
When should parents stop tracking their kids' location?
Some parents may be crossing a line with tracking their young adult kids’ locations, according to a new national poll.
Most parents track their 18-25-year-old kids on their smartphones. Is that healthy?
A new survey from the University of Michigan asks parents about their use of technology to track their adult children, ages 18-25, including using "always on" location tracking on their smartphones.
Safety or surveillance: Tracking of young adults
Half of parents report tracking their young adult child’s location at least occasionally. Nearly all parents who track their young adult child’s location say their child is aware of the tracking. 1 in 4 parents who track their young adult child’s location say it sometimes makes them more anxious than reassured. Only half of parents say they gave their young adult child the option to opt out of location tracking.
North Carolina gains inside track to College World Series finals with 5-2 win over West Virginia
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
Simplify Business Finances With QuickBooks Desktop Pro Plus 2024 for $300
Track expenses, manage invoices, and more from one platform.