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Pope hope, that’s entertainment, and getting ahead in the CIA
Happy Friday friends, I want to start by just breathing for all of us a big long collective sigh of relief at the news this week that the pope’s doctors have basically blown the all clear for Leo’s health. Going from knowing nothing to him declaring to the world he needed surgery, to a cancer diagnosis, to bouncing out of the hospital in barely even days, to ringing the bell in less than two weeks is whiplash inducing. But in the best possible way. We are living in a world in which the Roman pontiff, by dint of history, biography and circumstance, is once more at the epicenter of global affairs. Not just conversations about religion, or Christian and post-Christian values, but the bleeding edge of the most pressing issues of human affairs. Think I am exaggerating a touch? Consider the images of the crowds who greeted Leo in Paris just weeks ago, and juxtapose them with the absolute photo negative scenes unfolding there recently. Ask yourself how many world leaders are talking about AI right now and directly citing the pope as they do so. Try to name a country who has had as many top-ranked diplomats in and out of both Russia and Ukraine in the last three years as the Vatican has in the last three months. It has been fascinating to watch Leo XIV emerge as not just a kind of pop culture reference point or totem to be cited (Francis was often name-checked this way) but as a kinetic force in global conversation. Given the state of things, we need global figures of gravitas and values, even better if they have real wisdom behind what they are saying. So news of Leo’s illness was, it seemed to me, a tremor with potentially Richter Scale implications. That not only has the worst not come to pass but instead we’ve had the best of outcomes announced is something to really be grateful for. Humanity, it seems to me, is entering one of its irregular but cyclical phases where the pace of change — technological, social, and geopolitical — outstrips the ability of previously settled norms and received wisdom to cope. Such periods – and I think the first decades of the last century were a similar such time – throw into question the viability of all kinds of institutions. And many of ours have been straining to breaking point for a few years now. The papacy has the power and the potential to be a steadying pole in all of this. That’s my hope, anyway. It’s a lot to freight the office with, though it is arguably its ultimate purpose from its founding, to be a steadying rock on which all that matters can be anchored. It’s also, of course, an intolerable weight of responsibility to place on a single man. But I am encouraged to have hope in – and for – Leo. The apostle whom he succeeds, after all, was famously unequal to some moments, failed some tests of faith, and resiled from taking the road which led ultimately to the circus on Vatican hill. Human frailty and limitations, of health, of character, of temper, can open us to Christ, whose strength is greatest in our weakness, so St. Paul learned. That gives me hope, and I am sure it consoles Leo, too. And so I will continue to pray for him. Because we need apostles of rock right now. Here’s the news. Subscribe The News The Dicastery for the Doctrine of the Faith issued yesterday a new document “Venite ad me: Considerations on the Transmission of the Faith in an Epochal Change.” It’s not a short document, and it is at pains to stress this isn’t a doctrinal note from the dicastery, either. Rather, it brings together reflections on an important issue from the Church around the world. Some of it I actually found really rather powerful. It is, however, 25,000, which is a lot for a busy reader to get through on a weekday. So, you can read our busy reader’s summary right here. — News broke yesterday of an Oct. 22 meeting of U.S. bishops with President Donald Trump. The meeting was organized by an official at the Heritage Foundation, according to several sources close to the meeting. Video of several U.S. bishops praying in the Oval Office over President Trump was posted on social media Thursday afternoon, first by White House Communications Advisor Margo Martin, and then by the official twitter.com account of the Archdiocese of Denver. The meeting has drawn sharp criticism because of its proximity to the upcoming midterm Congressional elections, in which Democrats are widely expected to win control of the House of Representatives, while control of the Senate remains closely contested. Sources close to the bishops’ conference told The Pillar that some USCCB senior officials were surprised by the existence of the meeting when video of it first emerged online. And a source close to conference president Archbishop Paul Coakley of Oklahoma City told The Pillar that the archbishop was “deeply frustrated” by the occasion of the meeting. An official conference spokesperson told The Pillar that the meeting was “not organized with or by the USCCB” and was “not affiliated with the conference.” You can read the whole story here. — The next National Eucharistic Congress will be held in Indianapolis in 2029, a return to the city that hosted the last gathering in 2024. You read it here first. By here, I don’t mean this newsletter, I mean at The Pillar. We broke the story this week. It’s a big deal, in as much as the last congress was a roaring success and the next installment has the potential to be a real focal point for evangelizing efforts in the coming years. Read all about it here. — As Pope Leo prepares for the longest trip of his pontificate, Church leaders in Uruguay say the pontiff will encounter a highly secularized culture, in a country with a very different Catholic history than many of its South American neighbors. The nation has not had a papal visit since 1988, and leaders who spoke with The Pillar say it has a dire need for evangelization, even amid the prospect of a small revival in faith. This is real reporting on the Church in the country, and frankly a story you simply are not going to be able to read anywhere else. Read the whole thing. — The Archdiocese of Detroit announced this week a plan that would see the vast majority of its parish priests reassigned next summer, amid a restructuring process expected to dramatically shrink the number of parishes in the archdiocese. Archbishop Edward Weisenburger said this week that the plan “asks much of our priests,” but is a “sacrifice they are making as brothers of one, unified presbyterate.” The thing is, as JD pointed out in an analysis yesterday, pastors of parishes have a legal right to stability in office, so the only way this kind of wholesale reassignment goes ahead is if all of the archdiocesan clergy agree to resign. That creates its own kind of legal issues, though, and re-raises longstanding questions about the effectiveness of canonical due process protections for priests when dealing with coercive exercises in authority. Read the whole thing here. — More than three months after the Dicastery for the Doctrine of the Faith issued its decree declaring the excommunication of the leadership of the Society of St. Pius X, questions remain about the full effects of the society’s schism. Specifically, the DDF’s July claim that marriages witnessed and confessions heard by SSPX priests are now invalid remains contested — and it emerged this week it appears that the Vatican’s own legal experts don’t agree. You can read my whole analysis of the situation and what it means here. All I would add is that the DDF’s undeveloped, some would say unsubstantiated, claim about the invalidity of some SSPX sacraments came in their July Explanatory Note on the schismatic consecrations by the society that month. It touches directly on both papal acts of governance — indeed it purports to nullify them — and the most intimate pastoral encounters possible in a parish setting. If there is one aspect of the Francis-era style of governance I would like the curia to finally cut out, root and branch, it would be these attempts to try to effect extraordinarily sensitive legislative acts via a note. — At least a dozen French bishops have spoken out following an eruption of violence on the country’s streets Oct. 17. Not surprisingly, they unanimously condemned the violence, but the length and content of their interventions varied significantly. Several sought to distinguish between the actions of rioters and what they suggested were the legitimate concerns of peaceful young protesters. Many also evoked Pope Leo XIV’s Sept. 25-28 visit to France, suggesting it offered a powerful counter-image to the scenes of looting and destruction. A number of bishops also stressed their solidarity with law enforcement officials who struggled to contain the disorder, as well as the owners of the roughly 3,000 damaged or looted businesses. What’s the background to the nationwide unrest that the French media calls “les violences du 17 octobre”? And what exactly are the bishops saying? Read all about it here. — A Polish bishop called for the firm defense of unborn children as well as compassion for their mothers this week, as the lower house of Poland’s parliament passed two bills seeking to liberalize the country’s abortion laws. The bill on decriminalizing assistance in an abortion passed by 217 votes to 213, while the abortion in cases of fetal abnormality bill passed by 233 to 203, thanks to the government’s majority in the lower house. Both bills will now move to the Polish Senate, the upper house of parliament, where the ruling coalition has a larger majority. The fetal abnormality bill is symbolically significant because if it became law, it would effectively overturn a 2020 ruling by Poland’s Constitutional Tribunal that a 1993 law permitting abortion for a severe and irreversible disability or a life-threatening incurable disease was unconstitutional. Read the whole story here. Subscribe **[The St. Paul Center App | Bible Study On-The-Go Read and understand the Bible with St. Paul Center’s new app! With today’s leading Catholic Scripture scholars as your guides, the St. Paul Center app empowers you to read the Bible](https://stpaulcenter.com/app?utm_source=pillar&utm_medium=email&utm_campaign=applaunch)** from the heart of the Church. Download the app for free at either the Apple or the Google app stores. https://stpaulcenter.com/app That’s entertainment I have written before about my deep and sincere reservations about the celebrity exorcist subculture which has taken root in American Catholicism. And, because I am very ill at ease with the entire thing, I try to keep a weather eye on the phenomenon without being drawn into the kind of online back-and-forth which these figures sometimes generate. Earlier this week, JD noted that one such celebrity exorcist type, Fr. Chad Ripperger, has undertaken, on the request of his bishop, a year’s fast from interviews and public speaking. I’m sure that will be salutary for him, if for no other reason than that receiving with docility requests from one’s rightful ecclesiastical superiors always comes with graces. Then a second thing happened this week which caught my eye. Apparently, another fixture in the celebrity exorcist world, Fr. Carlos Martins, has initiated a lawsuit against two lay men — apparently associates of Rippenger, though I am unclear in what way, exactly — for allegedly defaming him and his ministry on a podcast. It seems the suit was initiated nearly a year ago and is now pending. At issue, I read, is that the two men described Martins on a podcast as “not who he says he is” with regard to his exorcism ministry and that he “doesn’t know what he’s talking about.” These statements Martins considers to be false and defamatory and, his suit claims, “directly affected the sale and reception of [his] The Exorcist Files book that was newly released at the time these episodes aired.” I don’t want to get too into the weeds of the details here, but a couple of things struck me about all this.
New Amazon delivery center brings 2-day delivery to Upper Peninsula for 1st time
The opening of Amazon's first delivery station in the Upper Peninsula shrinks the region's delivery times from eight days to two.
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During an intense drought from 2020 to 2022, the Upper Colorado River Basin lost far more groundwater than the Lower Basin did, despite having much higher natural recharge.
Tigers qualify for states
by: Dom Gliozzi The 3A WPIAL Consolation match was more than a third-place battle, as the winner would advance to the PIAA State Tournament next week. With such high stakes on the line, third-seeded North Allegheny defeated fourth-seeded Upper St. Clair (at Sewickley Academy) on Wednesday afternoon by a 3-2 decision. The Tigers took the… More »
Native gardening to be featured at UUVA annual banquet
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The Preliminary Lunar Science Report for Artemis II is out
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STEM space in Upper Marlboro encourages kids to enter science careers
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Charm Security Appoints Dr. Elizabeth Huppert as Behavioral Science Director
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Missouri’s 6th Congressional district: What to know about the candidates running in November
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A Political Brain Trust in an Upper West Side Building
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How Americans’ Financial Health Is Faring In The “K-Shaped” Economy
Hey all, Jason here. Money20/20 is still two weeks away, but I’ve already started packing (not procrastinating for once!). My calendar is already filling up with various sessions I want to catch, meetings, and of course happy hours, dinners, and other side events. If you’ll be in Vegas and want to catch up, let me know by replying to this email, and we can try to find a time amidst the chaos of the Venetian. A big if not totally unexpected piece of news dropped on Friday: the Independent Community Bankers of America, a trade group that represents smaller U.S. banks, filed a lawsuit against the OCC and Comptroller Jonathan Gould, arguing that the regulator’s move to grant trust bank charters to firms seeking to use them to conduct substantial non-fiduciary activities exceeds the authorities granted to the OCC by Congress. I haven’t had time to fully digest the legal filing or speak to folks in my network about it, but you can expect to see coverage and analysis on it in next week’s newsletter. Subscribe or Support by Upgrading The NerdCon agenda just dropped. It’s stacked. Partner content: Nubank built an AI-first bank. Chime built its own banking core. Figure and Valon are rebuilding the mortgage stack. At NerdCon, you’ll hear from the people behind those bets: what they chose, what they learned, and what they’re still figuring out. The agenda is live, with leaders from Nubank, Chime, OpenAI, Remitly, Mercury, Figure, Valon and more. Follow the mainstage conversations, bring the problem your team is wrestling with to a hands-on workshop, or pull up a chair at a roundtable. Pick your quests. Meet us in San Diego, November 18–20. Fintech Business Weekly readers save 20% with code FBW20. Explore the Agenda Things To Know & Other Good Reads Federal Reserve Board finalizes changes to enhance the transparency and public accountability of its stress test and reduce volatility in its stress test-related capital requirements (Federal Reserve Board of Governors) FDIC Announces Conclusion of Independent Monitorship (FDIC) Modernizing Financial Regulation: Initial Observations from eSLR (Fed Vice Chair for Supervision Michelle Bowman) The Data Version of Godzilla versus Kong: FRED Takes on AI (Fed Governor Christopher Waller) Financing the AI buildout (Brookings) Q3’26: Rules for Banks but Not for Crypto (Fintech Takes Banking) The Inevitability of Local Stablecoins (Lombard Notes) Delusions of AI Governance: The Human-in-the-Loop Comfort Blanket (Fintech Snark Tank) Stripe agrees to acquire Parafin to expand revenue opportunities for platforms and help small businesses grow (Stripe) Listen: Fighting Fraud in the Age of AI, with SEON’s Tamas Kadar (Fintech Business Weekly) How Americans’ Financial Health Is Faring In The “K-Shaped” Economy If there is one overarching theme across the economy and politics in the U.S. at the moment, it’s “affordability.” The term is vague enough to encompass a panoply of factors shaping Americans’ day-to-day lives: rising costs for the hallmarks of being “middle class,” including healthcare, housing, childcare, and education, inflation and rising interest rates, and a job market with the specter of AI hovering over it. At the same time, policy shifts under the Trump administration have resulted in reduced subsidies to those who get health insurance under the Affordable Care Act and new restrictions on qualifying for Medicaid and SNAP, the impacts of which have yet to be fully felt. These factors are contributing to declining consumer confidence and general dissatisfaction with the economy, despite continuing GDP growth and stock market records. This divergence is encapsulated in the idea of the “K-shaped” economy, in which a small proportion of Americans have seen their wealth balloon, while the majority of American households struggle to preserve the lifestyle they have. Perhaps the greatest determinant of which branch of the “K” a household is on is whether their wealth and income are primarily derived from employment vs. from assets. Nearly two decades of low interest rates and, more recently, elevated rates of inflation have benefited asset owners, while those whose income is primarily or solely derived from labor have largely seen real purchasing power stagnate or decline. This is reflected in recent Bureau of Labor Statistics data showing that labor share of U.S. GDP — the fraction of economic output that accrues to workers as compensation in exchange for their labor — dropped to just 52.8% in Q2 2026, the lowest since the BLS began keeping records. In 1947, approximately 2/3rds of economic output accrued to workers; even as recently as 2001, labor’s share of GDP was 64.1%. Against this backdrop, we’ve seen the rise of more credit and credit-like products: cash advance apps, “no-fee” overdraft, earned wage access, and buy now pay later, which are often used as small-dollar short-term borrowing mechanisms to meet immediate consumption needs or pay other bills (eg utilities, cell phone, other debt payments). With the markers of a middle class existence and, increasingly, basic financial stability seemingly out of reach for many, it should be no surprise there’s been an increase in “financial nihilism,” something industry peers like Alex Johnson and Frank Rotman have discussed and analyzed the roots of. The explosion of gambling and gambling-adjacent products and services — often marketed under the guise of being an “investment” — is inextricably intertwined with the rise of financial nihilism. Crypto, sports betting, and, more recently, prediction markets offer an escape or even hope of sorts, like a contemporary, digital version of a scratch-off lottery ticket, while leaving the overwhelming number of people who use such products worse off. Share of Households That Are Financially “Vulnerable” Ticks Up The Financial Health Network’s 2026 Financial Health Pulse® report adds context on how American households are faring. (I linked to this report in last week’s newsletter, but wanted to take time to further unpack the data in the report this week.) The Financial Health Network publishes the report annually, providing insight into how Americans’ financial circumstances are changing over time. The 2026 report is derived from a survey fielded in April and May 2026. The report leverages survey responses to assess indicators of financial health across spending, saving, borrowing, and planning/protecting and to determine a zero to 100 “FinHealth” score. Those with scores between 0 and 39 are considered “Financially Vulnerable,” consumers with scores ranging between 40 and 79 are defined as “Financially Coping,” and those with scores of 80 to 100 are “Financially Healthy.” The report found that moderate improvements in 2025 were reversed, with the share of respondents considered financially “vulnerable” rebounding to 17%. The longitudinal data reflect the impact of pandemic-era programs, like expanded unemployment, cash stimulus payments, and pauses of federal student loan payments. The positive impacts of those programs, as reflected in the Financial Health Pulse reports, had largely disappeared by 2023. While pandemic-era inflation — to be fair, in part caused by the various support and stimulus measures — had come down from as high as 9% in 2022, it has rebounded since the start of Trump’s second term, with tariffs and energy market disruptions owing to the war in Iran pushing prices back up. Specific indicators in the survey that deteriorated from 2025 to 2026 include the share of respondents spending less than their income over the past 12 months, the share paying all bills on time over the past 12 months, the share that have a manageable amount or no debt, the share that are “moderately” or “very” confident their insurance is adequate to cover them in an emergency, and the share that “somewhat” or “strongly” agree that their household plans ahead financially. Unsurprisingly, lower- and moderate-income households are more likely to struggle to pay their bills on time and have any funds leftover to save. The share of low-income households whose income exceeded their spending dropped from 35% in 2025 to 31% in 2026, while the share of upper-income households whose income exceeded expenses remained unchanged at 63%. Households with student loans or revolving credit card debt reported having “a bit more” or “far more” debt than was manageable at rates far higher than those not carrying these types of debts. The share of those with student loan debt indicating their debt load was too high to manage increased from 50% in 2025 to 55% in 2026, while the share of those with revolving credit card debt saying the same ticked up from 51% in 2025 to 54% in 2026. Households that had student loans were markedly more likely to be financially “coping” or “vulnerable” vs. those without student loans. In 2026, 27% of households with student loans were considered financially vulnerable, a jump of 6% points vs. 2025. Households without student loans saw just a 1% point increase (not statistically significant) in those considered financially vulnerable. Households’ perception of the affordability of categories of goods and services paints a stark picture, with less than one-fourth considering higher education affordable, about a third deeming childcare affordable, and less than half viewing healthcare as affordable. Fintech Business Weekly is made possible by the generous support of paying subscribers — bringing you independent analysis of banking, fintech, and crypto without fear or favor. You can support my work by becoming a paying subscriber if you aren’t already. Paying subscribers enjoy: access to the entire archive of nearly six years of newsletters extended versions of the weekly newsletter, with additional content and analysis and (for founding member tier) quarterly personal 1:1 fintech Q&A / strategy calls with me, tapping into my unparalleled knowledge of the intersection of banking and fintech and experience working in the sector, including helping to launch Goldman Sachs’ retail bank Marcus Support Fintech Business Weekly You can also support Fintech Business Weekly by sponsoring a newsletter or podcast, putting you in front of 93,000+ of the most influential decision makers in banking, fintech, and crypto. Learn more about sponsor opportunities or request a media kit by dropping me an email. Democratic Senate Report Highlights How Iran Uses Tether to Evade U.S. Sanctions Iran uses stablecoins, specifically Tether, to evade sanctions, fund regional proxies, and to purchase military drones, a report released last week by the Senate Permanent Subcommittee on Investigations says. The report was authored by committee ranking member Senator Richard Blumenthal (D-CT) and the minority staff. Crypto and stablecoin proponents will often push back on criticism that criminals make use of these assets by arguing that, on an absolute dollar basis, far more illicit funds flow through traditional banking systems and payment rails than via crypto and stablecoins. And while that is likely true, it elides the reality presented in news story after news story: whether state actors — Russia, Iran, North Korea — or criminal groups, those looking to engage in illicit transactions increasingly favor stablecoins and, specifically, Tether (USDT). The report from the Senate Permanent Subcommittee on Investigations released last week adds context to how Iran uses Tether has a lynchpin in its shadow banking system. The report analyzed 846 wallets that have been sanctioned or targeted for seizure, finding that 84% of them transacted exclusively or primarily in Tether. The ability to create near limitless, anonymous wallets and to move funds effectively instantaneously and irreversibly have made crypto a favored financial mechanism for bad actors. Stablecoins solved key drawbacks of bitcoin, namely, the original cryptocurrency’s highly volatile value in dollars. And while Tether (the company) has the technical ability to “freeze” or destroy funds, the company is often limited and reactive in its approach to doing so, the Senate report argues. Tether, which is nominally based in crypto-friendly El Salvador, “has stated that its compliance with OFAC sanctions is ‘voluntary’ and that it follows ‘OFAC guidelines,’” the Senate report says. Owing to these favorable attributes, Tether “became a primary cryptocurrency for Iran, Hamas, Hizballah, and the Houthis beginning in 2023 and has expanded in scale since,” according to the report. Tether’s role in Iran’s shadow banking system, the report says, is enhanced by crypto exchanges like Bybit, Kyrrex, OKX, Gate, and Binance, and through “over the counter” exchanges and hawala networks. The consequences of these financial flows aren’t hypothetical. The Senate report links Tether as a funds transfer mechanism to Iranian proxies in the region, including Hizballah, the Houthis, and Hamas. Tether has also been used to make payments to secure components necessary to manufacture drones, the report says. The report concludes by arguing that “[s]tablecoin issuers with a significant nexus to the United States, particularly those that offer dollar-denominated stablecoins, should be subject to American sanctions law rather than being allowed to hide behind foreign jurisdictions.” Stablecoin issuers like Tether must be held accountable for repeated failures to prevent illicit finance and sanctions violations by law enforcement, the Department of Justice, the Securities and Exchange Commission, and OFAC, the report argues. [Paying Subscriber Exclusive] OUSD Goes Live, Make Your Own Neobank, U.S. Sanctions Russia’s A7 Network As “Transnational Criminal Organization” OpenUSD, the stablecoin issued by the Open Standard consortium that includes Stripe, Visa, Mastercard, core providers, crypto firms, and numerous banks, went live last week. Social commerce platform Whop raised eyebrows in fintech by offering creators on its platform the ability to launch their own neobanks, which the company describes as “great businesses that are easy to run,” in just 15 minutes. And OFAC and FinCEN target Russia’s “shadow banking” A7 Network — more on these stories after the paywall.
Red Wings C Marco Kasper Suffers Injury
Marco Kasper will miss Sunday's Red Wings game against Winnipeg with an upper-body injury, prompting Detroit to move Emmitt Finnie to center.
Upper Dauphin dominates Camp Hill
(WHTM) — Camp Hill is looking to get their first win of the year as they take on Upper Dauphin in week six. Well, Camp Hill will have to try next week to get their first win as they lost 41-6. Meanwhile, Upper Dauphin improves to 3-3.
Dylan Larkin Ruled Out for Opening Night
Dylan Larkin will miss the Red Wings season opener and Sunday's game with an upper-body injury. #RedWings
New legislation targets vacant storefront concerns amid closure of Upper West Side mainstays
Jake's Dilemma, a longtime neighborhood bar, is preparing to close after 32 years in business. The establishment is expected to shut its doors in a few weeks.
Making it easier to visit West Seattle Junction & Upper Queen Anne business districts with paid on-street parking, load zones, safer crossings, and more
Making it easier to visit West Seattle Junction and Upper Queen Anne business districts with paid on-street parking, load zones, and more.
Newsom and Harris continue circling, may finally collide
The two San Francisco Democrats have spent decades in tacit competition. Newsom said he would defer to Harris in the presidential race. Did he just give her the upper hand?
ND clinics to change name following merger of two Minnesota-based healthcare providers
Two Minnesota-based healthcare providers are planning to merge and could create one of the largest nonprofit healthcare systems in the upper Midwest.
HealthPartners, Essentia Health announce combination focused on improving access, quality and affordability
BLOOMINGTON, Minn. & DULUTH, Minn., September 29, 2026--Agreement reflects a shared commitment to improving health and well-being across Minnesota and the upper Midwest
Velvet Cowboy, a Western Bar With a $5 Food Menu, Opens on the Upper West Side Tomorrow
The Jacob's Pickles team's new bar opens Tuesday with Southwest-inspired cocktails and a menu where every dish costs $5.
‘Starship is in orbit’: cheers go up as huge SpaceX rocket circles Earth for first time
Mission goes ahead despite some fears an initial engine failure after the Texas launch would scupper the attempt
Mental health stabilization center opens in Upper Darby
Operated by MVP Recovery, this is the second STAR Center in Delaware County.
Logan Mailloux Leaves Preseason Finale With Upper-Body Injury
Defenseman did not return following fight with Chicago's Cole Smith late in first period of 3-2 loss to Blackhawks
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Smith Entertainment Group Welcomes Fans Back to the Delta Center with Elevated Offerings for 2026-27 Season
More than 1,500 full-view seats added to the upper levels for Utah Mammoth games. Fan-friendly enhancements include new menu items, expanded ticket offers and a free rewards program
Smith Entertainment Group Welcomes Fans Back to the Delta Center with Elevated Offerings for 2026-27 Season
More than 1,500 full-view seats added to the upper levels for Utah Mammoth games. Fan-friendly enhancements include new menu items, expanded ticket offers and a free rewards program
A Delivery Worker Followed the Upper West Side Stabbing Suspect Home, and Got an Unexpected Goodbye
A Bronx delivery worker who helped police find Raul Morales after the July stabbings is describing a brief, strange exchange the two had on the way up to Morales's apartment.
The Division's New Release is Going Up Against Zelda
The Division 2: Echoes of Central Park launches in November with a new story set in Central Park and the Upper West Side.
Tre Lamb and Tulsa have the upper hand against Arkansas
Arkansas fans hope to beat Tulsa but shouldn't expect it
These Upper Trim Levels Just Aren't Worth It
Let's dive in to all your answers, and see what you all came up with to loathe.
No. 13 Penn State vs. Wisconsin: Game Preview
The Nittany Lions open up Big Ten play against the Badgers after a 3-0 start. Penn State (3-0, 0-0) vs. Wisconsin (2-1, 0-0) Kickoff: 5 p.m., Beaver Stadium, State College, PA The Betting Line: Penn State -9.5 (Fanduel) TV: Peacock, 5 p.m., Dave Flemming (play-by-play), Matt Cassel (analyst), Ashley ShahAhmadi (sideline) Weather: A nice day with highs in the upper […]
Meta's Next Smart Glasses Collab Is With Blackpink's Lisa
Blackpink in your upper-facial area.
Carter Bear Sidelined Again With Upper-Body Injury
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Dylan Larkin is Back With Detroit Red Wings
Dylan Larkin returned to Red Wings practice after missing the start of camp with an upper-body injury, though his lineup status remains unclear.
Chip and Joanna Gaines Finally Sell Their Famous $2.7 Million Historic Waco Castle—Fully Furnished
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Sen. Dylan Roberts named Upper Basin co-chair of Colorado River Forum
Colorado State Sen. Dylan Roberts was elected co-chair of the Colorado River Forum’s Upper Basin during last week’s meeting in San Diego, where lawmakers and water officials discussed the looming expiration of the Interim Operating Guidelines and the growing need for basin-wide collaboration on conservation, infrastructure and long-term planning.
Sen. Dylan Roberts named Upper Basin co-chair of Colorado River Forum
Colorado State Sen. Dylan Roberts was elected co-chair of the Colorado River Forum’s Upper Basin during last week’s meeting in San Diego, where lawmakers and water officials discussed the looming expiration of the Interim Operating Guidelines and the growing need for basin-wide collaboration on conservation, infrastructure and long-term planning.
As tailors disappear, this Upper Bucks shop looks to a fifth generation
With tailors disappearing, an Upper Bucks shop is set to pass to a fifth generation. That's "extraordinarily uncommon," the head of a trade association said.
What Does the Science of Climate Change Really Look Like?
Editor’s Note: This is the second in a three-part series on how the Right should think about environmental and climate policy. Read Chris Barnard on Reclaiming Environmental Policy from the Left. More than a decade ago, the world’s governments negotiated and signed the Paris Climate Agreement, committing to hold global warming well below 2 degrees Celsius. In the following years, climate had immense cultural power. Greta Thunberg emerged. Fortune 500 companies established net-zero plans. The U.S. got the Inflation Reduction Act. Then the pendulum swung back. President Donald Trump returned to the Oval Office, speaking of green energy as a “scam” and carbon footprints as a “hoax” and on all matters of international policy emphasizing bilateral engagement and power over globalism and cooperation. The technology companies that had been at the forefront of net-zero pledges and green leadership discovered the importance of all-of-the-above power to their visions for artificial intelligence and began quietly postponing or removing their targets. On the left side of the political spectrum, rising concerns about inflation and cost pushed climate lower down in the stated priorities of voters and stump speeches of politicians. The moment is ripe for a reset on the politics of climate change and for conservatives especially to chart a course that acknowledges and addresses the real challenges in plausible ways. So what should we think about climate change as we enter a post-peak climate era? If it is neither an apocalypse nor a hoax, what will hold up as a durable view of climate change? And how does it project onto the concerns and priorities of the right-of-center’s emerging coalition? New to Commonplace_? Subscribe below to get the magazine in your inbox._ Subscribe A Solid Foundation As the politics and economics of climate careened over the past ten years, the physics carried on regardless. In 2015, the year the Paris Climate Agreement was adopted, the world emitted 41.2 gigatonnes of carbon dioxide. By 2025, emissions had risen only 2.4%, to 42.2 gigatonnes, because falling emissions from land use offset increasing emissions from fossil fuels. But slow growth in annual emissions is not rapid decline, let alone net-zero, so carbon dioxide kept accumulating in the atmosphere, going from 399 to 426 parts per million. Global temperature kept rising too, from about 1.1 degrees Celsius above the 1850–1900 average in 2015, to 1.4 degrees above it in 2025. None of this should surprise anyone. Even most prominent skeptics, like the authors of the 2025 report commissioned by the Trump administration’s Department of Energy, accept the basic physics. Carbon dioxide added to the atmosphere at industrial volumes accumulates and traps heat that would otherwise escape to space. That heat warms the upper ocean and increases temperatures at the surface. Increased ocean heat and melting of land ice cause sea levels to rise. Changes in the climate become noticeable to us as subtle shifts in temperature and precipitation, seasons arriving early or late, changes in the surrounding ecosystem, and weather extremes. The much more meaningful debate is not about whether these things are happening, but about what it all means for human societies. (While it is a proxy measure of overall risk, no one experiences global surface temperature.) This debate invokes at least three interesting questions: how much today’s warming is showing up in regional climate trends, how much more warming we should anticipate, and how extreme weather events can be understood in the context of climate change. Recent scientific advances give us new insights into each of these, but there is still much to learn. This is the context in which the next generation of conservative leaders will be the first to deal with significant climate change as a fact, not a forecast. It will be with them for their entire careers. Our evolving scientific picture of climate change will come from weather and climate records stretching further into the past, new kinds of observations in the present, better modeling tools for the future, and simply more time to observe the emergence of climate signals and their tangible effects on ecosystems and communities in the United States and around the world. The policy landscape will be shaped by not only the impacts of changes in the climate, but also by the ways in which societies respond and by the emergence of new technologies for both altering the trajectory of emissions and adapting to new climate realities. Global climate records now show the fingerprints of warming in different phenomena around much of the world. The IPCC, in its most recent assessment report, documents warming trends over all land regions, even as natural variability adds substantial variance to local trends. And the highest temperature extremes have become more intense and frequent, almost everywhere, since the 1950s. Scientists are highly confident that these changes are attributable to human influence. But confidence in detecting trends and attributing them to human influence degrades across heavy precipitation events; drought trends are heterogeneous and not attributable to human activity with great confidence. For hurricanes, tornadoes, and other severe storms there is even less confidence in trends or their relationship to climate change. In general, a fair summary of the evidence is that for well-observed phenomena, like surface temperature or heavy rainfall, with a clear relationship to warming, our multidecadal observations are consistent with human influence overcoming natural variability over long time periods and extremes increasing. For regions that are sampled more sparsely, or phenomena with a higher noise-to-signal ratio, we will need to observe them longer to understand the magnitude of the climate signal or improve dynamical understanding using models and observations together. But for Climate For those who can’t wait, we also have new techniques that attempt to understand the role climate change has in influencing particular extreme events. When the climate is changing and disaster strikes, it is natural to ask whether that disaster was somehow “caused” by climate change. For scientists and policymakers acting in good faith, answering that question helps develop a more accurate picture of the problem, how it may be getting worse, and what preparations we should be making to respond to it. It may, at some point, give some weight to how liability is assigned by courts or adaptation funding is distributed by society. But how we ask this question is extremely important. It is easy to get the analysis wrong by discounting the role that meteorology plays. As meteorologist Theodore Shepherd explained in a clear 2016 review of climate attribution methods, “if a weather or climate event is truly extreme in the present climate, then perforce it requires unusual meteorological conditions, which means that climate change is at most a contributing factor.” Share Scientists have two ways to probe climate as a contributing factor, both of which have entered media coverage of extreme weather events. One asks a probabilistic question: How much more likely is a particular event (e.g., a temperature record over a particular area) amid global warming? The answer involves using historical records and computer simulations to estimate the likelihood of such an event in both a changed and a preindustrial climate. The findings are less about the specific event, and more about events of that nature. The other question is: How has the changed climate affected the specific event in question? Here, scientists try to understand what a similar event would have looked like in the preindustrial climate. This is sometimes called the storyline approach, where the story is the specific meteorological details of the event. These methods offer ways to test the intuition of scientists about real weather extremes. In late June and early July of 2021, a persistent high-pressure ridge, or heat dome, set up over the Pacific Northwest and an extraordinary heat wave affected the area from Oregon to British Columbia. For six days, it shattered temperature records across the region and hundreds died from heat-related causes, in an area where such high, and persistently high, temperatures were well outside of experience and many live without air conditioning. Scientists have studied its connection to climate change using multiple approaches. This specific event was created by a rare combination of meteorological factors, a strong high-pressure ridge created the conditions for extreme heat, which occurred on top of higher average temperatures in the region from global warming. Probabilistic analyses showed that climate change increased the likelihood of such an event by at least 8-fold to more than 100-fold. One standout example found that such an event had effectively zero probability of occurring in the preindustrial climate. The enormous range in these assessments reflects how hard it is to estimate probabilities of events at the tail of the historical record. Estimates of the effect on the temperature of the event are more clustered. A recent review paper documents how multiple methodologies have found a positive influence, roughly 1-2 degrees Celsius of an anomaly that exceeded 15 degrees, of climate change on the temperature magnitude of the event. Multiple studies have investigated and found some positive influence of climate change in other extreme events. Attribution studies found climate likely increased the heavy rainfall that accompanied Hurricane Helene in North Carolina and surrounding regions in 2024. The extensive fires that struck Los Angeles in 2025 illustrate how the causal chain can become messy, though. Studies do detect a positive influence of climate on the event’s likelihood, but while climate change likely contributed to underlying aridity, it would not have played a role in the heavy winds or land practices that preceded disaster. These event attribution studies will become more common for extreme, or damaging, weather events. They can be produced quickly, and often are reported before peer review. As the Pacific Northwest heatwave example shows, when multiple methods converge on a positive attribution, the finding should probably carry some weight even if you have to be careful about accepting the results from a single study. I expect that as climate change proceeds and the climate thus departs further from a preindustrial counterfactual, the influence will become more detectable across a variety of extreme events and more easily identified. This will be used to cast blame, but can also be used to inform how communities and society adapt to ongoing change. We May Still Be Surprised One positive development, insofar as less climate change is better, has been that our central estimates for future climate change should probably be revised downward. Mostly, that is because the high-end warmings that scientists regularly analyzed about ten to 20 years ago, driven by high emissions throughout the twenty-first century, now appear to be somewhere between unlikely and impossible. At one time, the upper end of mainstream climate projections extended well into 4 to 6 degrees Celsius of warming by the end of this century, which, models suggest, would have wrought enormous real-world damage. Current energy and policy trends now point toward 2.5 or 3 degrees. Damages and risks are commonly modeled as increasing steeply with more warming, so this is already a better-than-previously-expected outcome for the climate (which is independent of the physical response to emissions). But we should maintain a wide range for plausible outcomes and prepare for the possibility of being surprised. Emissions trajectories are subject to deep uncertainty, the physical climate response is still developing, and whatever change occurs in the climate will then be mediated through unpredictable economic, social, and political institutions. Over the past decade, the pace of warming surprised some keen observers and appeared to accelerate, though not yet outside the range of expectation provided by climate models. The reasons for that apparent acceleration are being actively studied (as was the apparent pause in warming from 1998 to 2012), but no single driver has emerged. Some blame it on the El Niño, variability which would have no bearing on climate. Some think it is a result of factories in East Asia and global shipping fleets cutting aerosol emissions, which in the strongest version of the argument would indicate higher climate sensitivity to carbon-dioxide emissions. Others are more measured, not yet ready to draw solid conclusions as to whether climate projections require revision. We will have to see. Long-Term Thinking Climate change asks us to think over long time scales. But the pace of human-driven warming is compressing a large global change into a century. Changing weather patterns and extreme events are already causing adjustment costs and damages and will do more. Adaptation will help, but it is not free. For some communities, these costs will erode livelihoods and well-being, and may force migration. Are we prepared for large-scale managed retreats in the United States? Thankfully, American wealth, geographical diversity, and moderate climates may leave us better prepared than many around the world. But wealthy countries can still suffer serious disruption from narrowly concentrated costs, even if they appear entirely manageable in aggregate. Readers of Commonplace are familiar with the challenges of rapidly adapting to economic forces. The displacement that came from the China Shock is barely perceptible in aggregate GDP and employment data, but it affected millions of people and those people were far less mobile than economic models tended to assume. Deindustrialization rippled through the nation with enormous effects for not only our economic vitality, but also our national security. The forces surrounding climate change may not be so different; the world gets richer and must accept some diffuse costs. Those may be modest overall, but cause all manner of unpredictable effects with which policymakers must cope. In the case of the China Shock, our faith in a growing pie served us poorly. We’ll need to do better on climate. Leave a comment
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