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Houston’s Asian population surges, but political representation lags, Rice study finds
As early voting begins, new Rice research sheds light on why some members of one of Houston’s fastest-growing populations say they remain underrepresented in local politics.
Galaxy S27 series case image adds weight to earlier design leaks
Previous leaks about Samsung’s next flagship non-foldable smartphones, the Galaxy S27, Galaxy S27+, Galaxy S27 Pro, and Galaxy S27 Ultra, have revealed renders
Not upgrading to iPhone 18 Pro or Duo? Here’s what’s coming next year
iPhone Duo preorders just begun, and iPhone 18 Pro has been on the market for about a month. Of course,...
Rice graduate students showcase innovative research at synthetic biology science cafe
The Science and Technology Policy Program at Rice’s Baker Institute for Public Policy hosted a “science cafe” Oct. 13 to bring research to reality and answer questions from the public, giving attendees a look at projects underway in university laboratories and an opportunity to ask questions about the science, its potential applications and its implications for society.
Samsung Galaxy phones can't tell if they're connected to Bluetooth or not
Samsung Galaxy phones are experiencing a problem that is causing the volume slider to show the incorrect icons.
Week of Well-Being highlights health and personal growth
Owls gathered at the Grand Hall Oct. 13 for a Well-being Fair as part of Rice’s Week of Well-Being, an initiative focused on promoting health, education and personal growth. The week is sponsored by Rice Employee Health and Well-Being and the Human Resources Benefits Department.
Samsung is expanding One UI 9 with Android 17 to the oldest qualifying flagships
Samsung’s Android 17-based One UI 9 update is starting to arrive on Galaxy S23, its oldest Galaxy flagships eligible for the update.
A recent Samsung change leaves some Galaxy phones stuck after updating
A One UI 9 post-update "access denied" error is preventing some Samsung Galaxy devices from reaching the home screen.
Northwest Biotherapeutics and the UK National Health Service Blood and Transplant Announce Collaboration to Support DCVax®-L Production
/PRNewswire/ -- Northwest Biotherapeutics (OTCQB:NWBO) (the "Company" or "NWBio"), a biotechnology company developing DCVax® personalized immune therapies for...
Rice Business Wisdom marks 10 years of bringing faculty research to wider audience
The anniversary issue examines a technology reshaping how people work, learn and make decisions. Featured stories explore how AI and machine learning influence household financial decisions, what drives data center location decisions across the United States and whether generative AI can help organizations sustain creativity over time.
Amazon US Prime Deals: the Samsung Galaxy S26 Ultra is 30% off
Despite the recent price hike that put the base model at $1,400 MSRP, you can still get an S26 Ultra under $1,000. The Samsung Galaxy S26 Ultra launched at...
Catalytic confessions and a quest for Matt Damon: PodCAT puts science on mic
PodCAT, hosted by researchers from Rice, the University of Rochester and Penn State University, is a podcast devoted to the science of catalysis, academic careers and the surprisingly personal stories of the researchers themselves.
Nobel Prize in Physics awarded to Francis Halzen for ice research
Scientist Francis Halzen won the 2026 Nobel Prize in Physics, the Royal Swedish Academy of Sciences in Stockholm announced on Tuesday.
Northwest Biotherapeutics Announces Keynote Presentation on Harnessing Immunity: A Personalized, Multi-Target Approach to Cancer At the UK National Health Service Annual Oncology Conference
/PRNewswire/ -- Northwest Biotherapeutics (OTCQB:NWBO) (the "Company" or "NWBio"), a biotechnology company developing DCVax® personalized immune therapies for...
6 One UI 9 features you should immediately try out
The One UI 9 features worth trying first
iPhone 18 Pro Max vs Samsung Galaxy S26 Ultra: which should you choose?
Two of the very best phones compared
Rice experts available to discuss human spaceflight, safety and space policy
Leveraging Rice’s deep ties to U.S. space exploration, faculty can analyze the technical, political and physiological implications of recent developments across the space industry.
Samsung has updated these Galaxy devices to Android 17
Samsung is now rolling out its Android 17-based update, One UI 9, to its collection of supported Galaxy smartphones and...
Rice Engineering and Computing names Karen Lozano as director of Tapia Center for Empowerment through STEM Education
Rice’s George R. Brown School of Engineering and Computing has named Karen Lozano as the director of the Tapia Center for Empowerment through STEM Education.
CenterPoint Energy completes sale of its Ohio natural gas business to National Fuel Gas Company for $2.62 billion
/PRNewswire/ -- CenterPoint Energy, Inc. (NYSE: CNP) ("CenterPoint" or the "Company") today announced that it has successfully completed the previously...
How did Portland become the global epicenter of women’s sports?
Portlanders have consistently shown up for women’s sports and helped create the world of women’s sports we know today.
Samsung’s Android 17 floodgates are open – updates rolling out for Galaxy S26, S25, more
The floodgates are open. After a delay and staggered starts, Samsung is widely rolling out its Android 17-based One UI...
Samsung Galaxy S27 Ultra camera leak points to warmer photos and cleaner night shots
Leaker Ice Universe says the Samsung Galaxy S27 Ultra moves from the Galaxy S26 Ultra's cool color profile to warmer tones, holds back small bright light sources on both its main camera and 50MP 5x telephoto, and shows less shadow noise at night.
Galaxy S27 Ultra camera could solve two major issues seen on Samsung phones
The launch of the Galaxy S27 series is still four months away, but most details about the lineup's phones have already leaked. While the Galaxy S27 Ultra's basi
The Galaxy S25 series plus the Galaxy Z Fold7 and Z Flip7 are now getting stable One UI 9
The update has started rolling out to users in South Korea. Samsung announced the One UI 9 update for the S26 series – it started rolling out in South...
Millions Of Galaxy S25 And S26 Phones Get New Samsung Features Today
Samsung is finally rolling out its free feature upgrade to millions of Galaxy phones after a delay with the One UI 9 release. Here's who's getting it.
Samsung rolling out Android 17, One UI 9 for more Galaxy S26 users
Samsung is widening the rollout of Android 17 and One UI 9 to the Galaxy S26 series in the US, but the floodgates aren't fully open yet.
Samsung finally reveals everything coming to your Galaxy S26 with One UI 9
One UI 9 is finally rolling out to the Galaxy S26 — here's everything that's new.
Samsung Galaxy S26 Users, Check Your Phone For This Free Upgrade Now
Samsung is finally rolling out its free feature upgrade to millions of Galaxy phones after a delay with the One UI 9 release. Here's who's getting it.
Deals: Galaxy Z Fold7 vs. Galaxy Z Fold8 and Z Fold8 Ultra, plus Galaxy S26 FE alternatives
The Z Fold7 is a lot cheaper than its replacement - but you will be missing out on some great improvements and the Z Fold8 Ultra is discounted as well.
You can check your Samsung Galaxy's health with a built-in test
Bluetooth, sensors, speakers and battery life are just a few of the things you can check by running Samsung's health test on your S26 or earlier model Galaxy.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Rice has climbed one spot to No. 16 in the nation in U.S. News & World Report’s Best Colleges rankings, with the university also earning top 10 recognition for value, undergraduate teaching and student experience.
Samsung's One UI 9 rollout may have hit a speed bump for the Galaxy S26
Samsung has pushed back the Galaxy S26 series' One UI 9 rollout date in Thailand, raising questions about the wider release.
Rice to bring brain health conversation to United Nations
Three experts from Rice will attend Brain Week at the United Nations General Assembly Sept. 21-25 to join an international conversation that reaches well beyond neuroscience and medicine.
City Arts and Sciences Academy receives $250,000 grant
LYNN — The school year at City Arts and Sciences Academy is off to an auspicious start, with news that the school has been awarded a $250,000 grant from the… Related posts: ‘The American Dream’ explores the pursuit of justice with DA Paul Tucker LEAP of faith Lynn Community Health Fellowship graduates 70 Role reversal
Samsung Confirms Free Feature Upgrade For Millions Of Galaxy Phones
Samsung has officially confirmed One UI 9 is rolling out to Galaxy S26 phones today with 11 new features. Here's what's new and how to get the update.
Five One UI 9 features you should try first
Samsung released the stable One UI 9 update for the Galaxy S26 series in Korea on September 16. A wider rollout should start from September 21, with devices suc
I put the iPhone 18 Pro Max vs. Galaxy S26 Ultra through a 7-round face-off
Apple doesn't have a price advantage this time
One UI 9 global release dates for some Galaxy devices revealed
Samsung finally started rolling out the One UI 9.0 update for the Galaxy S26 series a few days ago, following months of beta testing. The update, which debuted
Samsung Galaxy S26 FE review: An incremental price hike for incremental updates
It’s tough times for the midrange phone.
Galaxy S27 Pro, S27 Ultra charging and battery specs just leaked, and it's good news
New regulatory filings have revealed battery and charging details for the Galaxy S27 Pro and S27 Ultra. And there's good news.
Rice to launch Master of Artificial Intelligence program in fall 2027
Rice will launch a new Master of Artificial Intelligence program in the fall of 2027.
Emily McBride on Maternal Mental Health and the Lindsay Clancy Trial
Fiction writer Emily McBride joins co-hosts V.V. Ganeshananthan and Whitney Terrell to discuss her debut novel, Queen Mab, and maternal mental health. McBride talks about the media frenzy around th…
Snap tries to make the case again for its $2,200 smart glasses
Snap unveiled new features for its smart glasses this week.
Rising diesel prices hit area businesses
Razorback Rentals owner says fuel costs are the highest since he took over the business in 2004
The day Galaxy S26 series owners have been waiting for since May has finally arrived... for some
The stable Android 17-based One UI 9 update is (slowly) rolling out for Galaxy S26, S26 Plus, and S26 Ultra devices at last.
Samsung releases stable One UI 9.0 update for Galaxy S26 series
Samsung debuted the One UI 9.0 update by opening the beta program for the Galaxy S26, Galaxy S26+, and Galaxy S26 Ultra in May. Now, after almost five months an
Samsung Gallery is adding Google Photos backup to replace OneDrive
New updates are starting to roll out that will let Samsung Gallery replace its OneDrive integration with Google Photos support....
Looks like Samsung Gallery has already found its OneDrive replacement
As Samsung's partnership photo storage partnership with Microsoft winds down, the company is moving to Google to fill the gap.
Hoeven makes case for the Protect College Sports Act
Senator John Hoeven made the case for the Protect College Sports Act, bipartisan legislation to improve fairness and stability in college athletics.
Samsung launches ‘Re-Newed’ Galaxy S26 series, $1,099 for Ultra
Samsung is now selling its Galaxy S26 series flagships at a discount with refurbished models available for around $200 off....
Rice Business marks new era of growth with opening of Virani Hall
Asha and Farid Virani Hall, a 112,000-square-foot building which now stands alongside McNair Hall, offering students a combined 400,000 square-feet designed to support the school’s expanding community of graduate and undergraduate students, faculty, researchers and alumni.
Galaxy S27 Pro and S27 Ultra to get major display upgrade
Samsung’s Galaxy S27 Pro and S27 Ultra are reportedly set to receive M16 OLED panels, promising improved brightness, color accuracy, efficiency, durability and new privacy features. The standard S27 models, however, are expected to use older M14 technology.
Galaxy S27 Pro and S27 Ultra to get biggest OLED upgrade in 3 years
Samsung is making big changes to the Galaxy S series next year. The company is expected to launch four Galaxy S27 series phones early in the year, and two of th
iPhone 18 Pro Max vs Samsung Galaxy S26 Ultra: How these XL phones compete
Apple or Samsung? It really comes down to which ecosystem you prefer.
Apple iPhone 18 Pro Max vs. Samsung Galaxy S26 Ultra: The Highest-End Phones Compared
The iPhone 18 Pro Max has a big camera upgrade -- and a bigger price. How does it compare to Samsung’s flagship phone?
New measure captures how scientists’ identities shift across academic disciplines
Rice and Michigan State researchers have developed and validated a new way to measure the extent to which scientists remain closely connected to the core of their discipline over the course of their careers.
5 Android phones you should buy instead of the Samsung Galaxy S26 FE
Thinking about picking up the new Galaxy S26 FE? Before you do, you might want to consider your alternatives.
Galaxy S27 Pro gets Samsung’s fastest charging speed yet
Samsung is planning to launch four high-end phones, the Galaxy S27, Galaxy S27+, Galaxy S27 Pro, and Galaxy S27 Ultra, early next year. While most of their spec
Deals: Galaxy Z Fold8 Ultra and Z Flip8 get first big price cuts, Galaxy S26 FE launches
The Galaxy S26 FE comes with a $200 gift card, which helps it fend off the Galaxy S26+ and Galaxy A57. The Samsung Galaxy Z8 series of foldables launched...
10 Literary Science Fiction and Fantasy Novels That Offer Hope for the Future
During graduate school, I finished the novel that found me an agent—but when my agent submitted it to publishers, all twenty of them turned the manuscript down. Truthfully, it was closer to a colle…
Galaxy S27 Ultra and Pro’s dramatic camera redesign appears in leaked case render
Drastic changes are apparently coming to the 2027 Galaxy S series. The Plus version doesn't seem to be going away, as many past rumors wrongly predicted in rece
Debi Mazar claims ‘Entourage’ set became ‘toxic’ after she welcomed her second baby: ‘Didn’t like that I got fat’
Debi Mazar claimed that the ‘Entourage’ set became ‘toxic’ after the actress welcomed her second baby.
Rice-developed BuoyBeads bring biotechnology lessons to high school classrooms
A biotechnology kit developed at Rice allows high school students to create living materials.
Samsung Galaxy S26 series receives seventh One UI 9 beta with Galaxy Z Fold8 series' features
This was a surprise, as the sixth beta was released just a few days ago. Samsung released the sixth One UI 9 beta for the Galaxy S26 series earlier this...
Galaxy S26 series gets seventh One UI 9.0 beta update
Samsung has released the seventh beta version of One UI 9.0 for the Galaxy S26, Galaxy S26+, and Galaxy S26 Ultra. According to the changelog, it brings three c
Samsung's Galaxy S26 FE Strips the S26+ Down to Its Basics
The value of these 'Fan Edition' Samsung phones isn't what it used to be.
I tried the Samsung Galaxy S26 FE early. It’s best feature just might be the price
Our tech reviewer just got to try Samsung’s latest mid-range phone, and he thinks the Galaxy S26 FE offers a solid set of features and specs for its price.
The Samsung Galaxy S26 FE is now official and its price ends the FE's best streak
The Fan Edition has started at the same number since 2024. That run is over as of today.
Samsung’s $700 Galaxy S26 FE Is Better, but It’s Getting Harder to Call It a Bargain
Samsung's best software features from 2026 are coming to the lower-cost S26 FE -- but at $700, it's certainly not cheap.
Galaxy S27 Ultra leak reveals the 7,000mAh battery Samsung reportedly rejected
We can always dream
Galaxy S26 Ultra is the world’s most popular Android phone, and that’s a first
Android phones are never the top-selling smartphones globally, but the ones that get closest are almost always budget models. In...
Saint Louis Science Center honors legacy of late VP Becky Thompson
The Saint Louis Science Center announced the recent death of its vice president of science and education late last month.
Galaxy S27 series design gets way more interesting in new leaked renders
A few more design cues for the entire Galaxy S27 series have just been revealed through a series of fan-made CAD renders. According to leaks, next year's Galaxy
Invest more in human capabilities as AI advances, health leaders urge
Speakers at HIMSS26 APAC say better health outcomes would require redesigning health systems to harness AI.
Samsung reportedly bringing this major redesign back from the dead with Galaxy S27 [Gallery]
According to new leaks, Samsung is planning to revive a lost redesign with its Galaxy S27 series, but details are...
New minor explores how biology, behavior and society shape health
Rice’s new undergraduate minor examines the biological, psychological and social factors that shape health.
Zambian Police Summon Opposition Leader After Disputed Election
Zambian police summoned the nation’s opposition leader after he pledged to challenge the outcome of last week’s presidential election, over which observers have raised concerns.
Why governments need science advice: Lessons from UK’s chief science adviser
Professor Dame Angela McLean, the U.K. government’s chief science adviser, discussed the role of science advice in government during an armchair discussion at Rice University’s Baker Institute for Public Policy, hosted by the Science and Technology Policy Program as part of its Civic Scientist Lecture Series.
Samsung confirms August 27 event for the ‘newest addition to the Galaxy S26 family’
Samsung is teasing a new entrant to the Galaxy S26 series coming at an event on August 27, but it’s...
Samsung announces Galaxy launch event for August 27, likely for S26 FE
Not even a full month has passed since the last Samsung launch event, and the company is getting ready for another. Moments ago, Samsung sent out invitations fo
Samsung One UI 9.5 leak hints at new premium UI design changes
Samsung is continuing to work on its upcoming One UI 9.5 update. A new testing build with the CZHD firmware has reportedly been spotted for the Galaxy S26 series. The new build gives us an early look at some of the design changes Samsung may bring with the next version of One UI. According to […]
Baker Institute fall calendar brings global leaders, foreign policy scholars and science innovators to Houston
The Baker Institute’s fall 2026 calendar will bring prominent policymakers, scientists, business leaders and scholars to Houston this fall for a series of public conversations on energy and grid resilience, artificial intelligence and health, global affairs, demographics, science policy and the future of Texas.
I'd skip the expensive Samsung Galaxy S26 Ultra for these phones every time
Forget Samsung's latest, these five phones are great alternatives
Deals: the Google Pixel 11 series is now on pre-order with gift cards and trade-in bonuses
The Galaxy Z8 foldables have similar offers, though, and the Galaxy S26 models are cheaper than the respective Pixel phones.
Deals: Pixel 11 series goes on pre-order, Galaxy Z8 foldables and S26 models drop prices
The new Pixels will be available from August 20, but Samsung is already trying to undercut the newcomers. Google launched its new Pixel 11 series earlier...
New One UI 9 beta for the Galaxy S26 may be released soon
There has been a steady stream of One UI 9 beta releases for the Galaxy S26 series over the past couple of months. The stable release shouldn't be that far off
Google Pixel 11 vs Samsung Galaxy S26: Specs, price, camera details
How to Google and Samsung's flagship phones compare?
Here’s your first look at One UI 9.5 design!
Samsung has yet to roll out the stable One UI 9.0 update for existing devices, but One UI 9.5-related leaks are already here. Earlier today, we reported that th
Someone is already running One UI 9.5 on a Galaxy S26
As Galaxy users around the world wait for Samsung to bring One UI 9 (Android 17) to their devices, someone has managed to get hold of a One UI 9.5 firmware for
Scientists uncover new clue to how protons maintain their identity
New results from the STAR detector at the Relativistic Heavy Ion Collider (RHIC) suggest that gluons, the gluelike particles that hold quarks together inside protons, play a central role in the conservation of baryon number, an essential part of a particle’s quantum identity.
Rice launches SCOPE, a new science communication center
The Center for Science Communication and Public Engagement (SCOPE) is now open at Rice.
Every Galaxy phone and tablet eligible to get One UI 9 (Android 17) update
In May, Samsung unveiled its latest custom Android interface for Galaxy smartphones and tablets, One UI 9.0, by releasing its beta version for the Galaxy S26 se
Leaked Galaxy S26 FE specs confirm another battery disappointment from Samsung
Samsung doesn’t seem to even try to surprise anyone with its next Fan Edition phone.
Galaxy S26 FE specs leak alongside a higher price tag
Ahead of its launch that will likely happen next month, Samsung’s Galaxy S26 FE has had its full specs leak...