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Research report: Digital Science and Sunmedia partner to bring research impact reporting to Japan’s medical affairs teams

Sunmedia will use Dimensions and Altmetric data in customized reports intended to assess attention, sentiment and real-world connections for Japanese medical affairs teams.

Oct 21 • 1:49 AM EDT • Science • bioengineer.org

National 2D materials research hub names new director

Stephanie Law, associate professor of materials science and engineering at Penn State, has been named director and principal investigator of the Two-Dimensional Crystal Consortium-Materials Innovation Platform, a U.S. National Science Foundation-supported national user facility within Penn State’s Materials Research Institute.

Oct 16 • 3:07 PM EDT • Science • psu.edu

Enhancing hidden defects to strengthen metal materials

Scientists have found a way to use defects in crystals to engineer stronger materials, according to a new study.These imperfections, usually caused by tiny distortions within the material, could be a powerful design tool for building complex, three-dimensional structures.Using a two-step process to strengthen a pair of metal alloys, researchers ...

Oct 15 • 2:09 PM EDT • Science • news.osu.edu

2026 U.S. Gas Utility Business Customer Satisfaction Study

TROY, Mich.: 14 Oct. 2026 — Overall satisfaction among gas utility business customers rises 10 points (on a 1,000-point scale) to 655 in the JD Power 2026 U.S. Gas Utility Business Customer Satisfaction StudySM, released today. Business customer satisfaction improved across nearly all dimensions. Trust and information provided show the strongest gains, each up 24 […]

Oct 14 • 8:00 AM EDT • Business • jdpower.com

Scientists control where 2D semiconductor crystals begin to grow, addressing key challenge in stacking AI chips

Two-dimensional (2D) semiconductors, only a few atomic layers thick, are promising materials for making AI chips faster and more energy efficient by stacking additional semiconductor layers on top of ...

Oct 13 • 11:40 AM EDT • Science • techxplore.com

Physicists discover “astonishing” property of light that defies expectations

Scientists have uncovered a surprising hidden ability of light that allows it to develop spinning, twisting behavior as it travels through empty space, without special lenses, mirrors, or materials. Researchers discovered that light’s internal geometry can naturally produce left- and right-handed patterns, challenging long-standing assumptions about how light behaves. By carefully arranging a beam’s structure, scientists can control where and how these spinning patterns emerge, unlocking a new way to manipulate light.

Oct 12 • 8:00 PM EDT • Science • sciencedaily.com

CSU researchers test AR ‘X-ray vision’ technology for judging distance in blocked-visibility situations

Research being conducted at Colorado State University is bringing technology once thought to be science fiction one step closer to reality. Augmented reality technology allows three-dimensional objects to be placed in real-world surroundings as if they were physically present. It is most commonly found in mixed reality headsets such as the Apple Vision Pro or...

Oct 12 • 2:08 AM EDT • Science • collegian.com

Microsoft Is Taking AI Beyond the Data Center, But Its Surface Business Is Just a Small Piece of the Pie

The tech giant's latest Nvidia-powered Surface devices add another dimension to its growth strategy as shares trade near all-time highs.

Oct 11 • 4:30 PM EDT • Technology • barchart.com

Microsoft Is Taking AI Beyond the Data Center, But Its Surface Business Is Just a Small Piece of the Pie

The tech giant's latest Nvidia-powered Surface devices add another dimension to its growth strategy as shares trade near all-time highs.

Oct 11 • 4:30 PM EDT • Business • finance.yahoo.com

Microsoft Is Taking AI Beyond the Data Center, But Its Surface Business Is Just a Small Piece of the Pie

The tech giant's latest Nvidia-powered Surface devices add another dimension to its growth strategy as shares trade near all-time highs.

Oct 11 • 4:30 PM EDT • Business • barchart.com

Statement From Archbishop Ronald Hicks on the Health of Pope Leo XIV

Your prayers mean the world to me, and please know that I am praying for each of you as well.

Oct 11 • 12:13 PM EDT • Health • thegoodnewsroom.org

Scientists Uncover Two Hidden Forms of Disorder in Next-Generation Semiconductors

A study of twisted two-dimensional semiconductors reveals how subtle material disorder can emerge at different spatial scales. Two distinct forms of hidden disorder may influence how ultrathin semiconductors emit light. One extends across relatively large areas of the material, while the other is concentrated around tiny defects. A new theoretical approach offers a way to

Oct 9 • 2:20 PM EDT • Science • scitechdaily.com

Someone's modded Diablo 2 for VR, and seeing the world through your character's eyes brings a whole new dimension to the series

First-person Diablo 2, in virtual reality, is a radical new way to experience the classic old game.

Oct 6 • 12:05 PM EDT • Technology • eurogamer.net

Digital Science appoints Charlesworth as strategic sales partner of Altmetric and Dimensions in China’s scholarly publishing sector

AsiaNet 201874

Oct 5 • 9:45 PM EDT • Science • english.kyodonews.net

Digital Science appoints Charlesworth as strategic sales partner of Altmetric and Dimensions in China’s scholarly publishing sector

Digital Science has appointed Charlesworth as its strategic sales partner of Altmetric and Dimensions in China’s scholarly publishing sector. This collaboration aims to support the growing demand for research data and information across this rapidly developing market.

Oct 5 • 8:30 AM EDT • Science • newswise.com

Digital Science Appoints Charlesworth as Strategic Sales Partner of Altmetric and Dimensions in China's Scholarly Publishing Sector

London, United Kingdom--(Newsfile Corp. - October 5, 2026) - Digital Science has appointed Charlesworth as its strategic sales partner of Altmetric and Dimensions in China's scholarly publishing sector. This collaboration aims to support the growing demand for research data and information across this rapidly developing market.China's local publishing industry has grown significantly in scale and maturity, with journal publishers actively strengthening their international position, investing in.

Oct 5 • 5:00 AM EDT • Science • finance.yahoo.com

Dear Apple Stock Fans, Mark Your Calendars for October 13

Apple is preparing a notable smart-home expansion for Oct. 13, adding a fresh dimension to its product ecosystem.

Oct 3 • 2:30 PM EDT • Technology • barchart.com

Scientists add third dimension to light and unlock hidden electron states

A 3D light field using crossed femtosecond lasers has allowed scientists to access and image elusive electronic quantum states.

Oct 3 • 8:33 AM EDT • Science • interestingengineering.com

Scientists Find Structural Guide to Unusual Magnetism in Quantum Materials

Researchers in Japan found that a crystal’s structural dimensions classified magnetic states more consistently than electron concentration.

Oct 1 • 3:56 AM EDT • Science • thequantuminsider.com

Pokémon Legends: Z-A – Nintendo Switch 2 Edition + Mega Dimension Bundle Coming Soon

The Pokémon Legends: Z-A – Nintendo Switch 2 Edition + Mega Dimension bundle is coming soon.

Sep 30 • 9:10 AM EDT • Technology • pokemon.com

Power Outage: Tigers' Home Run Leaders of 2026

Despite Dillon Dingler’s late-season slump and Spencer Torkelson’s streaky production, Detroit’s persistent power struggles highlight a lineup fighting to overcome the cavernous dimensions of their home ballpark.

Sep 28 • 11:19 PM EDT • Sports • sports.yahoo.com

Why We Lost to Oklahoma State

A one dimensional offense, and a defense that couldn’t get stops gives WVU fans a reality check.

Sep 27 • 10:19 AM EDT • Sports • sports.yahoo.com

Minecraft is getting its first new dimension in 14 years, and it's called The Sift

Mojang has announced The Sift, Minecraft's first new dimension in more than 14 years.

Sep 27 • 7:20 AM EDT • Technology • eurogamer.net

Maryland football destroyed by UCLA, 54-3, in 9th straight Big Ten loss

COLLEGE PARK, Md. — Maryland was outclassed from the start. In a game that was scoreless after one quarter but quickly devolved into another lopsided loss, nothing went the Terps’ way. Maryland couldn’t establish a running game despite a questionable insistence on doing so; quarterback Malik Washington never got going in the one-dimensional offense and threw four interceptions; and the Terps’ ...

Sep 26 • 8:22 PM EDT • Sports • sports.yahoo.com

Minecraft Is Getting A New Dimension Called The Sift In 2027

The Sift will first be released with Minecraft Dungeons 2 later this month before arriving in the base game.

Sep 26 • 3:19 PM EDT • Technology • engadget.com

Minecraft Dungeons II’s New Dimension Coming to Minecraft Java & Bedrock Edition

At Minecraft LIVE, Mojang announced that the first new dimension in 14 years - The Sift - will be coming to both Minecraft Dungeons II and Minecraft Java & Bedrock Edition. Learn more inside.

Sep 26 • 2:00 PM EDT • Technology • news.xbox.com

Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL

Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting

Sep 26 • 9:36 AM EDT • Technology • newsletter.semianalysis.com

ProTributeBands.com Clarifies Direct Booking Model for Corporate Event Entertainment Planners

SAN RAMON, CA - September 25, 2026 - PRESSADVANTAGE -ProTributeBands.com, the curated booking and lead generation platform for high-end tribute bands, has outlined how its direct-booking structure works for event planners seeking corporate event entertainment. Under the model, bands featured on the platform negotiate terms and close each booking directly with the client, while ProTributeBands follows up to keep the transaction moving smoothly.The structure separates ProTributeBands.com from traditional booking agencies that insert themselves into every contract. Rather than acting as an intermediary that controls the final agreement, the platform connects event planners, performing arts centers, festivals, wedding clients, and private party hosts with pre-screened, national-act-caliber tribute acts, then steps back so the parties can settle details themselves. The platform maintains contact with both sides to ensure momentum is not lost during the process.Founded by David Victor, former guitarist and co-lead vocalist of the multiplatinum band BOSTON, ProTributeBands.com features tribute acts covering artists such as Queen, The Beatles, ABBA, Journey, The Eagles, and Pink Floyd. Selected bands receive optimized profile pages and booking leads generated through the platform."Event planners often assume a booking platform means another layer of negotiation and markup," said David Victor, Founder of ProTributeBands.com. "The approach here is different. The bands negotiate terms and close each booking directly, which keeps the conversation honest and the details accurate. The platform stays involved by following up so nothing stalls between the first inquiry and the signed agreement."The direct-booking method reflects how corporate and private event planning typically operates. Planners frequently need to confirm technical requirements, stage dimensions, scheduling, and performance specifics with the people who will actually be on stage. By allowing those conversations to happen between the client and the band, the model aims to reduce miscommunication that can occur when information passes through a third party.ProTributeBands.com applies a screening process before an act appears on the platform, focusing on production quality, musicianship, and readiness for larger venues. The company ranks tribute bands across categories including Queen, The Beatles, The Eagles, Journey, Pink Floyd, and BOSTON tributes, drawing on performance quality and audience response.The ProTributeBands guide to hiring a tribute band offers additional context for planners weighing these decisions, covering topics such as understanding the audience and event, assessing entertainment value, viewing an act in person before hiring, and reviewing rider and insurance requirements. The guide addresses the practical considerations planners face when selecting an act for a corporate function, festival, or private celebration."A tribute production for a corporate audience has to hold the room the same way a headline act would," Victor said. "The vetting exists so planners can trust that the act they see listed can deliver at that level, and the direct-booking structure lets them confirm every detail with the band before committing."ProTributeBands.com serves clients across the United States and abroad, working with tribute acts that perform at performing arts centers, summer concert series, product launches, corporate parties, private parties, and wedding receptions. The platform also accepts artist submissions from tribute bands seeking consideration for inclusion. The company operates online at protributebands.com.###For more information about ProTributeBands.com, contact the company here:ProTributeBands.comDavid Victor(925) 236-0217hello@protributebands.com11040 Bollinger Canyon Road Suite E-938, San Ramon, CA 94582

Sep 25 • 5:10 PM EDT • Entertainment • wkow.com

Calling all current and future scientists: Kiel is the place to be this week

This week, Kiel has become a meeting place for science in Europe. Researchers, school pupils, young scientists and members of the public are coming together through a series of major events led or co-organised by Kiel University.At the centre of it all are around 150 of Europe’s most talented young researchers, aged 14 to 20, who have travelled to Kiel from nearly 40 countries for the 37th European Union Contest for Young Scientists (EUCYS). Running from 22 to 27 September, the European Union’s flagship competition for young scientists brings together winners of national science competitions to present around 100 original research projects across fields ranging from engineering and computer science to medicine, environmental research and the social sciences. The winners will be announced at the Award Ceremony on Saturday.For Kiel University, hosting EUCYS is both an honour and a natural extension of a much longer story. Germany’s northernmost comprehensive university has invested for many years in supporting young scientific talent and bringing research into dialogue with society. The Kiel Science Factory gives school pupils opportunities to experience research first-hand, while programmes such as Rent-a-Scientist send researchers directly into local classrooms. Major annual public events including Kiel Week and the European Researchers’ Night take science beyond the campus through talks, exhibitions and hands-on activities.That long-standing commitment has increasingly taken on a European dimension – and this week, many of those efforts are coming together.One of the foundations for this success is the European Researchers’ Night (ERN), which celebrates its tenth edition in the Kiel region this year. The initiative is funded through the Marie Skłodowska-Curie Actions, with Kiel University developing the successful EU proposals and securing the funding, while regional partner KielRegion coordinates the many activities on the ground. Together with research institutions, schools, companies, local authorities and civil society, they have built ERN into a major platform for public engagement.Over the years, Kiel’s ERN programme has grown far beyond a single evening into a whole “Science Summer”, beginning with “Science Shopping” in spring and culminating tomorrow, 25 September, in Science Day.“We have developed a wide range of public engagement formats, often together with the other research institutions in the region, the city and regional authorities, schools, companies and civil society,” says Eckhard Quandt, Kiel University’s vice president for research, academic infrastructure and transfer. “Over the past decade, we have increasingly taken this commitment to the European level.”That combination of European funding expertise and strong regional partnerships also helped Kiel University take the next step. Drawing on its experience with ERN and its European networks, including the SEA-EU University Alliance, the university brought together Brest in France and Split in Croatia for a successful bid to the EU’s new Science Comes to Town initiative. Throughout 2026, the three cities are serving as Europe’s first Science Ambassadors, with more than one thousand activities bringing science into schools, public spaces, cultural venues and everyday life.EUCYS is perhaps the clearest example of how Kiel University is using Science Comes to Town to create new connections between major European initiatives. From the outset, the university deliberately planned the contest for the week of European Researchers’ Night and opened the EUCYS exhibition to the wider Science Day audience. Tomorrow, that means thousands of visitors can encounter the next generation of scientific talent first-hand, while the young researchers themselves gain a much bigger public stage.“Because we opened EUCYS up for European Researchers’ Night, there will be a lot of people actually visiting the exhibition,” says organiser Stefanie Altemark of Kiel University.“We wanted Europe’s most talented young scientists not only to compete with one another, but also to become visible to the wider public. At the same time, people in Kiel will have the opportunity to see what the next generation of scientists are already capable of,” says Quandt.“We’ve shown over the last years that science is a big part of Kiel, and it’s always been the goal to not only show that to people in Germany, but also to show it to people all over Europe. Thanks to Kiel University’s expertise in European funding programmes, we have been able to turn that ambition into reality,” says Sünje Fock, who is coordinating the Science Summer at KielRegion.The model is characteristic of Kiel University’s approach: combining European funding expertise and international networks with strong regional partnerships to give major initiatives greater reach and visibility.This year also marks the 30th anniversary of the Marie Skłodowska-Curie Actions, giving Kiel University the special opportunity to welcome Vanessa Debiais-Sainton, Head of Department for the Marie Skłodowska-Curie Actions at the European Research Executive Agency, to Kiel tomorrow. Her visit brings together two priorities that have shaped Kiel University’s work over the past decade: supporting researchers and bringing science closer to society. Debiais-Sainton emphasises how closely the two are connected: "For thirty years, the Marie Skłodowska-Curie Actions (MSCA) have given more than 150,000 researchers the chance to pursue their dreams and open up new fields. Doctoral Networks and Postdoctoral Fellowships give them the freedom to move, to connect, to train and to follow their curiosity across borders, sectors and disciplines. But excellence cannot live only in laboratories. Researchers’ Night takes science out of the lab and into the city, to the families, the schoolchildren and the curious minds who will become the next generation. Kiel shows what that looks like at its best. That is the MSCA promise: open science, open borders, open doors."For Kiel University, these activities are not separate endeavours. They are part of a broader understanding of academic excellence in which outstanding research, talent development, international cooperation, knowledge transfer and engagement with society strengthen one another.“For me, one of the most important lessons from the past decade is that scientific excellence, knowledge transfer, talent development and engagement with society cannot be treated as separate tasks,” stresses vice president Quandt. “They reinforce one another.”That philosophy is also reflected in Kiel University’s current bid for Germany’s Excellence University status. The designation is part of Germany’s national Excellence Strategy, which provides substantial long-term funding to selected universities to strengthen internationally competitive research and their overall institutional development. A successful outcome would provide new opportunities to build on what has already been created: deepening international cooperation, creating more opportunities for knowledge exchange and public engagement, and extending the university’s reach across the region and beyond. “If we are successful, it would allow us to take what we have built in Kiel considerably further – including expanding our networks and transfer activities beyond the region and increasingly across the Baltic area,” says Quandt.This week’s events offer a glimpse of what that could mean in practice: a university using its research strength, European expertise and regional partnerships to create opportunities for scientists at every stage of their careers while making science more visible, accessible and exciting to the wider public.

Sep 24 • 5:37 AM EDT • Science • sciencebusiness.net

Here’s how iPhone Duo and iPad mini compare in size

Here’s how iPhone Duo’s folding screen compares to the size of the iPad mini, including side-by-side comparisons, dimensions, and more.

Sep 22 • 11:28 AM EDT • Technology • 9to5mac.com

Xulon Press announces a new work where theology and science meet, The Dimensional Universe: Quantum Ontology, Dynamics and Patterns of Duality from author Jack K. Mayfield.

Phoenix, AZ, Sept. 21, 2026 (GLOBE NEWSWIRE) -- Xulon Press announces the release of The Dimensional Universe: Quantum Ontology, Dynamics and Pa...

Sep 21 • 12:00 PM EDT • Science • markets.businessinsider.com

Xulon Press announces a new work where theology and science meet, The Dimensional Universe: Quantum Ontology, Dynamics and Patterns of Duality from author Jack K. Mayfield.

With the existence of a mysterious immaterial dimension governed by quantum mechanics that still baffles the world’s top physicists, Mayfield builds a bridge long thought impossible: rigorous science standing shoulder to shoulder with theology.

Sep 21 • 10:00 AM EDT • Science • globenewswire.com

NSF invests in translating low-dimensional semiconductor technologies to establish U.S. leadership in microelectronics

The U.S. National Science Foundation today announced an initiative to translate low-dimensional semiconductor technologies from laboratory demonstrations into platforms for U.S. manufacturers to…

Sep 17 • 4:21 PM EDT • Science • nsf.gov

Scientists discover a major brain shift between ages 50 and 75

Scientists have uncovered sweeping changes in how the human brain controls and organizes its genome beginning in midlife, offering new clues to why aging sharply increases the risk of Alzheimer’s and other neurodegenerative diseases. One of the biggest shifts occurred between about ages 50 and 75, when many of the brain’s original immune cells declined and were replaced by cells with more inflammatory characteristics. Researchers also found weakening of cells that help maintain the blood-brain barrier, along with widespread deterioration in the genome’s three-dimensional organization.

Sep 15 • 8:00 AM EDT • Science • sciencedaily.com

The Amazing Science of Castells arrives in Tarragona with 14 Posters

Tarragona hosts until October 13 an exhibition of 14 posters that explains the physics, chemistry, and social dimension of the human towers.

Sep 13 • 3:51 AM EDT • Science • modernetdigital.cat

Scientists visualize proteins' hidden water architecture that may help define biological function

For decades, scientists have understood proteins primarily through two defining features: their amino acid sequence and their three-dimensional structure. This framework has driven major advances in biology, ...

Sep 10 • 8:00 PM EDT • Science • phys.org

How have the new dimensions changed Kauffman Stadium?

The K has been more hitter friendly this season thanks to the changes in the wall dimensions

Sep 8 • 2:00 PM EDT • Sports • sports.yahoo.com

The war on Iran’s energy infrastructure creates rising political risk

When Israel targeted Tehran’s oil storage facilities in the initial days of the war launched on Feb. 28, black smoke blanketed the capital and plunged parts of the city into darkness. Roughly ten days later, strikes hit natural gas facilities at the giant South Pars field, key oil refineries, major steel plants, and petrochemical complexes, impacting thousands of workers. These attacks on vital energy and industrial assets revealed a critical dimension of the conflict: compounding an already acute domestic energy...

Sep 7 • 8:00 PM EDT • Politics • amwaj.media

Jayden Savoury Has Announced Himself as MSU’s Top Tight End

The Orchard Lake product transformed offseason hype into on-field production, emerging as Alessio Milivojevic’s vital security blanket while providing a new, physical dimension to the Spartans' passing attack.

Sep 7 • 12:19 AM EDT • Sports • sports.yahoo.com

Researchers create polar wurtzite nitride semiconductor NbAlN

Polar wurtzite nitride semiconductors such as aluminum nitride and gallium nitride underpin high-power and high-frequency electronics. Researchers have now achieved the first epitaxial growth of niobium aluminum nitride (NbAlN) on GaN while preserving its polar crystal structure. Used as a barrier layer, NbAlN increased the interfacial two-dimensional electron gas density from 5.1 × 1012 to 1.7 × 1013 cm−2, opening new possibilities for polarization-based materials design in future GaN electronic devices.

Sep 6 • 8:00 PM EDT • Science • eurekalert.org

Steve Aoki's Skincare Routine is Cake-Proof

The multidimensional music icon shares his secret to looking stage-ready.

Sep 4 • 11:00 AM EDT • Science • nylon.com

This strange “spacetime crystal” can suddenly become a black hole

Physicists have mathematically captured a bizarre “spacetime crystal” that can either dissolve or collapse into a microscopic black hole after only a tiny change in energy. Their breakthrough came from an unusual trick involving infinitely many dimensions, potentially giving researchers a new tool for studying primordial and microscopic black holes.

Aug 30 • 8:00 AM EDT • Science • sciencedaily.com

Minecraft Dungeons II Gameplay Trailer

Discover the Sift, a mysterious new dimension in Minecraft Dungeons II. Watch the latest gameplay trailer, explore strange new landscapes, face powerful threats, and learn more about the biggest Minecraft Dungeons adventure yet. Pre-order now before launch on September 29.

Aug 20 • 1:00 PM EDT • Technology • minecraft.net

High touch, not merely high tech

Commentary: AI is revolutionizing the customer journey in a wide array of dimensions. What must not be lost in this revolution, though, is the human element — including empathy, care, ethical reasoning, as well as effective decision-making and support.

Aug 20 • 10:00 AM EDT • Business • rbj.net

Everyday Injustice Podcast Episode 337: Marc Bookman Examines the Death Penalty’s Politics, Failures and Enduring Appeal

Marc Bookman, legal director of the Atlantic Center for Capital Representation, recently discussed capital punishment on Episode 337 of 'Everyday Injustice.' Bookman challenged the perception of a national death penalty resurgence, asserting its continued application is increasingly confined to a limited number of states. He also critiqued public opinion polling on capital punishment, specifically a Pew poll, for failing to present alternatives such as life without parole. Additionally, Bookman previewed his forthcoming novel, 'Albert's Time,' which explores the ethical dimensions of capital punishment by confronting the execution of an undeniably guilty individual.

Aug 17 • 7:10 AM EDT • Politics • davisvanguard.org

Josh Allen and DJ Moore show signs of bringing back big-play dimension

In a crowd-buzzing moment, one play represented why the Buffalo Bills acquired Moore in trading a second-round pick to the Chicago Bears in March.

Aug 14 • 12:56 PM EDT • Sports • spectrumlocalnews.com

Edinburgh international film festival showcases a Scottish industry in rude health

This year’s festival is superpowered by a strong year for Scottish cinema, showing it can thrive under the ‘four dimensional perpetual catch-22’ of global ambitions

Aug 13 • 1:05 PM EDT • Health • theguardian.com

Digital Science Connects AI Agents to World-Leading Research Data with New Dimensions MCP Servers

Digital Science has announced the launch of new Model Context Protocol (MCP) servers for Dimensions, giving enterprise AI agents direct, license-aligned access to one of the world's largest interconnected global research databases.

Aug 10 • 11:00 AM EDT • Science • newswise.com

AbCellera women’s health data top ‘most aggressive upside scenario,’ putting Astellas and Bayer on notice

AbCellera has reported phase 2 results “beyond even the most aggressive upside scenario” that its CEO dared to consider, boosting the biotech’s chances of challenging Astellas and Bayer for a women’s health market. The phase 2 clinical trial compared ABCL635, an antibody targeting NK3R, to placebo in patients with hot flashes caused by menopause. Investigators enrolled 92 postmenopausal women experiencing a mean of about 10 moderate or severe hot flashes per day. By Week 4, the number of moderate or severe hot flashes had fallen by a mean of 8.8 on ABCL635 and by 3.5 on placebo. That statistically significant, placebo-adjusted reduction of 5.3 hit the trial’s primary endpoint. The level of efficacy also cleared the bar set by existing drugs. While cross-trial comparisons can be misleading, AbCellera CEO Carl Hansen, Ph.D., had seen enough to start hyping the program. “We now view ABCL635 as a potential best-in-class non-hormonal therapy with strong differentiation against approved NK3R competitors across all important dimensions, including efficacy, safety, dosing and convenience,” Hansen said on a Monday morning conference call with investors to discuss the data. “We believe ABCL635 is now a highly de-risked program.” Last week, Hansen used AbCellera’s earnings call to set expectations for readout, with the CEO defining success as a clean safety profile and efficacy comparable to the two approved small molecules. The data vaulted over that bar. Astellas linked (PDF) one of the small molecules, Veozah, to placebo-adjusted reductions in hot flash frequency of 2.1 and 2.6 at Week 4 of its two phase 3 trials. Bayer reported (PDF) placebo-adjusted reductions of 3.04 and 3.29 at Week 4 of pivotal studies for its small molecule, Lynkuet. At 5.3, the placebo-adjusted reduction in AbCellera’s trial comfortably cleared the standard set by the incumbents. Veozah and Lynkuet came to market based on evidence of their ability to reduce the frequency and severity of hot flashes. AbCellera’s phase 2 study covered both endpoints, with the Canadian biotech reporting a mean reduction in severity of 1.4 points at Week 4 on ABCL635, compared to 0.3 points for placebo. Again, the placebo-adjusted result compares favorably to data on Veozah and Lynkuet. Analysts shared Hansen’s enthusiasm for the data. The phase 2 results “firmly validate ABCL635 as a potentially best-in-class treatment,” BMO Capital Markets analysts said in a note to investors Monday. ABCL635’s apparent efficacy edge “is likely attributable to the higher dosing/target engagement the asset is able to reach vs. the oral agents due to its wider therapeutic index,” the analysts added. The analysts, who model $2.3 billion in unadjusted peak sales for ABCL635, flagged the safety profile as another positive of the phase 2 readout. While Veozah carries a boxed warning for liver damage, nobody on ABCL635 in the phase 2 trial had elevated liver enzymes or bilirubin values. If replicated in phase 3, the lack of a liver signal could allow approval without the monitoring requirements imposed on Veozah. Investors appeared equally enthused, sending AbCellera's stock up 32% to $9.21 in premarket trading Monday from a Friday closing price of $6.93. Next, AbCellera will collect the Week 12 data and talk to its advisors about further development. The results open up “a wide variety of possibilities of how we might take this forward into phase 3 studies to truly maximize the value of the asset and make sure that ABCL635 is able to demonstrate its differentiation potential,” Sarah Noonberg, M.D., Ph.D., AbCellera’s chief medical officer, told investors.

Aug 10 • 8:24 AM EDT • Health • fiercebiotech.com

Digital Science launches Dimensions MCP servers

Existing Dimensions API customers can begin using the Model Context Protocol servers immediately without extra licence

Aug 10 • 5:00 AM EDT • Science • researchinformation.info

Claude Fable 5 AI finds a tiny formula that topples an 87-year-old math conjecture

A mathematician working at Anthropic says he used the AI model Claude Fable 5 to uncover a remarkably simple counterexample to the Jacobian conjecture, a famous problem that has resisted mathematicians for more than a century. The result shows that the conjecture is false in three dimensions and above, although the original two-dimensional version remains unsolved.

Aug 5 • 8:00 AM EDT • Science • sciencedaily.com

Learning from routine health system data builds better neuroimaging AI models

Nature Medicine - We trained a three-dimensional visual foundation model directly on 5.24 million routine clinical computed tomography (CT) and magnetic resonance imaging (MRI) image series so that...

Jul 30 • 8:00 PM EDT • Health • nature.com

After Hobbes vs Rousseau: Politics must move beyond human nature

Since the great debate between Hobbes and Rousseau, our political theory has been organised around a single question: is human nature essentially good or essentially corrupt? Graham Harman, the philosopher behind object-oriented ontology, argues that this is simply the wrong question to be asking. The real forces governing our collective fate - climate change, artificial intelligence, geography, and pandemics - are non-human; therefore, questions about human nature are not the central ones. Instead, Harman proposes a politics reorganised around our relationship to non-human objects and environments, in which quasi-government institutions incentivise and deter actions with the aim of extending the survival of the human race. “It is easier to imagine the end of the world than the end of capitalism.” This has become one of the most popular phrases among twenty-first-century intellectuals. Often misattributed to Fredric Jameson, it has been warmly embraced by such influential authors as Slavoj Žižek and the tragically departed Mark Fisher, and has fueled the notion that the major problem with the political Left is that it simply needs to become more speculative and creative. Naturally, this is never a bad idea in any human pursuit. But what if the political distinction between Left, Right, and Center itself results from a failure of imagination? SUGGESTED READING Hobbes vs Rousseau: are we inherently evil? By Robin Douglass This particular division has been with us only since the summer of 1789. During the simmering prelude to the French Revolution, it referred originally to the physical position in the National Assembly of radical figures on one side and loyal monarchists on the other. These positions are linked with two entirely different camps of modern political theory. On the Left we find a series of authors ranging from the moderate (Locke) to the supercharged (Rousseau) to the truly radical (Marx), all of them contending that exploitation of the many by the few justifies revolutionary overthrow of the existing order. On the Right they are countered by the likes of Machiavelli, Hobbes, and Schmitt, a group of thinkers convinced that corrupt human nature can be tamed only by force. In the words of the Nazi supporter Schmitt: “One could test all theories of nature and state and political ideas according to their anthropology and classify these as to whether they consciously or unconsciously presuppose [humans] to be by nature evil or by nature good.” This is the division we continue to face today, even in the daily retail politics of Western democracies.___Our species has regularly proven itself capable of both the noblest gestures and the most scathing cruelties, making it hard to define us as essentially either emancipatory or brutal in our aims.___The most refreshing feature of David Graeber and David Wengrow’s 2021 book The Dawn of Everything: A New History of Humanity was their awareness that the forced choice between Rousseau and Hobbes (as they put it) is no longer sufficient. Our species has regularly proven itself capable of both the noblest gestures and the most scathing cruelties, making it hard to define us as essentially either emancipatory or brutal in our aims. Far from being stationed “beyond good and evil,” we seem to be fully entangled with both. We are not naturally good or evil, Graeber and Wengrow contend, but naturally experimental and imaginative. They rest their case on the archaeological record, which seems to bear witness to numerous episodes of seasonally shifting governments and festivals, which vacillate in the same society (even in the same year) between the egalitarian and the dictatorial. Such praise of political experiment makes a good fit with the generally anarchist position defended by these authors. Yet it is also what I find most disappointing in their position. Although they are right that the forced choice between Hobbes and Rousseau falls short of what our new situation requires, the authors simply replace it with praise for the human being as a political tinkerer and performer. In other words, they give us just another theory of human nature, one that would not have been out of place in the sixteenth or seventeenth century. What other options might we have?___The time is ripe for a retheorization of politics on the basis of something other than human nature… We are not just alienated and limited by objects, but also empowered and unleashed by them___One fresh approach would be to treat politics within a broader framework than human nature, given that the polis does not exist in a vacuum filled exclusively with people. When Bruno Latour went to observe the baboons of Kenya with the San Diego anthropologist Shirley Strum, they jointly concluded that these primates were more socially interdependent than our own species. Each baboon is so reliant on the dynamics of the group that they find themselves locked into constant surveillance of their potentially dangerous peers. The group structure turns out to be inherently volatile. Humans, by contrast, are able to stabilize their societies to a large degree through the mediation of inanimate objects. Although one’s position in society may seem to fluctuate over time, considerable stability is produced through such items as apartment keys, wedding rings, and identification cards, all of them serving to secure us a place distinct from that of our fellows. The Italian philosopher Maurizio Ferraris has written at length about the crucial role of documents in establishing social relations, making him a hero among notaries in his country. Proper names and license plates cement our position amidst other humans, as do symbolic achievements such as graduation from a top university or distinguished wartime service with its various medals and ribbons. None of this is found among baboons, despite their closeness to us on the evolutionary tree: after all, we did share a common ancestor just 25 to 30 million years ago. SUGGESTED VIEWING The goodness paradox With Richard Wrangham The time is ripe for a retheorization of politics on the basis of something other than human nature, whether understood in the manner of the Left or of the Right. We are not just alienated and limited by objects, but also empowered and unleashed by them. But initially, it is true, we face non-human things primarily in the form of constraints. It would be difficult, perhaps impossible, to form a human civilization underwater, deep underground, atop Mount Everest, or in outer space. Human dependence on the non-social background takes on subtler form in discussions of political geography, especially unloved on the more idealistic Left. Consider the luckless position of Poland during World War II, sandwiched between Hitler on one side and Stalin on the other. By contrast, note the good fortune of the United States in not having a military peer positioned on any land border. Anglo-American geopolitics, since the writings of the American naval commander Alfred Thayer Mahan and the British geographer Sir Halford Mackinder, has been wedded to the notion that one or more liberal offshore naval powers should prevent any authoritarian “heartland” regime from gaining effective control of Eurasia. That remains the case whether the opponent is the impatient Napoleon, the swashbuckling German Kaiser, the villainous Hitler, the murderous Stalin, or the industrial juggernaut Chinese. In their current Foreign Affairs article “Heartland vs. Rimland,” Michael Beckley and Hal Brands analyze the current and coming state of the world on the basis of these same rather durable principles. In recent years a similar outlook has been embraced, in inverted form, by the Putin-loving Russian philosopher Aleksandr Dugin, an icon of the Rightist intellectual underworld. For Dugin, the Anglo-Saxons are an evil force bent on destroying the spiritually superior people of the land: much like Athens in its failed war with Sparta, or Carthage in its eventual collapse against Rome. But the shared notion on both sides is that any strategy that fails to take geography into account is likely to end up as a defeated form of excessive optimism.___When dealing with environmental degradation, then, we are doing business with forces that promise dire effects on our species as a whole.___More striking for us today than geography is the non-human object called climate, which threatens rimland and heartland equally. Even if we contend that humans are one hundred percent responsible for triggering the climate crisis, it remains non-human in the sense of being an independent force beyond our effective control. In a major work published just before his death in 2002, The Structure of Evolutionary Theory, the American paleontologist Stephen Jay Gould noted the tendency of evolutionary theorists to focus too closely on the fate of individuals in view of their successful or failed adaptation to circumstances. With climate change, however, we confront a force that goes well beyond the scope of any individual life. Whereas Richard Dawkins extended evolutionary questions downward from individuals to the sub-individual gene, Gould pushed it upward, speaking of entire species or clades as impacted by environmental change. The asteroid that struck the Yucatán 66 million years ago is only the most famous example of this sort. In the wake of that catastrophe, large animals needing abundant supplies of food were at a fatal disadvantage by contrast with the smaller birds and mammals of the planet. When dealing with environmental degradation, then, we are doing business with forces that promise dire effects on our species as a whole. The effect is to shift our attention away from individual beings towards the survival of the group.In the United States in particular, the COVID-19 pandemic sparked considerable backlash among those who asserted a nearly absolute degree of individual freedom. In California I encountered those who demanded that their businesses be allowed to reopen, that it was enough to cover their mouths but not their noses, or that they should have the right to enter any public area despite refusing vaccination. Yet public health is probably the clearest argument against libertarianism, which often merely asserts the autonomy of individuals against any claims of the commons. In normal times the individual is worth defending; under conditions that threaten the survival of part or all of our species, compulsion may be our only resort, as with perfectly reasonable blackouts and rations in wartime. To rebuild human society under the constraints of climate change will be one of the great challenges of the century to come, as will our improvised grappling with artificial intelligence. Such phenomena pose existential risks for humanity, and leave far less room for tolerance of individual brattiness. Cases are mounting of devastating wildfires caused by arson. Recently it was reported that there is even a website where one can bet on the location of coming wildfires, raising the specter of deliberate blazes set to collect on wagers. The death penalty has steadily lost support in a world where many stress the infinite value of human life. But if we focus instead on entire ecosystems, those who purposely burn the forests may begin to look worse than serial murderers.___The politics of the future may be splintered by disagreement over such topics as how to manage our environing background and how to permit or restrict the entry of new objects into the political sphere.___So far I have spoken of force, authority, and punishment: measures sure to have greater appeal to those who identify with what we know as the Right. But other implications of the post-anthropocentric world are likely to have different backers. If non-human objects are seen as structuring political space, it stands to reason that they can no longer be introduced solely by the pace of technical breakthrough. Fields ranging from cybernetics to energy will demand increased politicization once they are reconceived not just as products of individual human investment, but as renovations of collective political geography. This need not involve world government, with its inherent risk of tyranny, but may involve quasi-governmental enforcers of prestige along the lines of a less corrupt FIFA or International Olympic Committee, punishing deviant states not with violence but with less tangible incentives.Politics will never lose its historic links with conflict and faction. But rather than factions aligned by differing theories of human nature, the politics of the future may be splintered by disagreement over such topics as how to manage our environing background and how to permit or restrict the entry of new objects into the political sphere. This will prove just as incommensurable with the modern Left/Right spectrum as a globe is with a two-dimensional map.

Jul 30 • 8:00 AM EDT • Politics • iai.tv

Everything We Know About MacBook Ultra's All-New Design

Apple's next high-end laptop is expected to bring the most substantial external changes to the MacBook Pro line since 2021. No renders, case leaks, or dimensions have emerged, but a series of reports have established much of what is set to change.

Jul 27 • 9:00 PM EDT • Technology • macrumors.com

When It Comes to Fusion, Materials Matter

Fusion at high temperatures powers the sun and, if harnessed, could provide a potential source of energy here on Earth. But controlling fusion reactions has other benefits. The process also generates subatomic particles called neutrons that are used in a range of applications spanning medicine, research, and national security. Now, scientists at the University of California, Davis (UC Davis), and the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) have found that the materials surrounding a fusion reaction can dramatically increase how often it occurs, particularly at low energies where fusion is rare. The study was published July 18 in Nature Communications. Their approach sets up a way to study and engineer nuclear reactions within solid materials, opening a new field of “materials-driven fusion.” Instead of designing materials just to survive the harsh conditions of fusion, researchers might be able to design materials that boost the reaction in specific conditions, similar to the way catalysts speed up chemical processes. “It gives you a new knob to turn that you didn’t have before,” said Arun Persaud, head of the Fusion Science & Ion Beam Technology group in Berkeley Lab’s Accelerator Technology & Applied Physics (ATAP) Division. “If we understand this effect better, it opens the door to engineering new materials that would affect the fusion rate under certain conditions. Someday future progress might enable more compact and efficient neutron generators, which have all kinds of applications, like cargo screening, planetary science, and medical therapy and imaging.” In the experiment, researchers used two different methods to pack deuterium, a heavy form of hydrogen atoms that is often used in fusion, into thin foils of palladium and titanium. They then fired a beam of deuterium ions at the foils at different energies and measured how often fusion happened. Then they compared the rates from the different materials and methods with the “bare” fusion reaction (not in a material). The team found that fusion rates depended on how the deuterium was loaded into the metal foils. The biggest effect was at the lowest energies, below 2.5 kiloelectronvolts (keV), where theory predicts fusion rates drop off sharply. Instead, researchers found a surprising plateau: Some samples showed elevated fusion rates roughly a quintillion times higher than bare fusion reactions. (A quintillion is a 1 followed by 18 zeroes.) Researchers are not exactly sure why that’s happening, though they have some ideas and ways to test them. The electrons and defects within the material might partially shield repulsive electrostatic forces between deuterium nuclei, making it easier for them to get close together and fuse. Tuning the electronic structure, defects, and composition of materials could help make nuclear reactions happen more readily. “It comes down to better understanding the mechanism so that we can try to enhance it,” said corresponding author Jeremy Munday, a professor at UC Davis. “We’ve seen that we can increase fusion rates, but what is the limit? Can we bring it to lower temperatures or energies? There’s obviously a lot of interest and excitement about fusion, so if there’s something we can learn about the physics at these lower energy scales, maybe there’s something we can translate to other areas of nuclear science.” The team plans to explore a wider range of materials and continue probing the unexpected fusion plateau at lower energies. Their work establishes a reproducible experimental platform to study how solid materials influence nuclear reactions, creating a new area of research that links fusion science with materials science and chemistry. “The work shows conclusively that the material environment where fusion occurs at low temperatures is an active participant rather than a passive container,” said Cameron Geddes, director of ATAP. “That adds a new dimension to fusion research.” This work was funded by the U.S. Department of Energy’s Advanced Research Projects Agency-Energy (ARPA-E). ### Lawrence Berkeley National Laboratory (Berkeley Lab) is committed to groundbreaking research focused on discovery science and solutions for abundant and reliable energy supplies. The lab’s expertise spans materials, chemistry, physics, biology, earth and environmental science, mathematics, and computing. Researchers from around the world rely on the lab’s world-class scientific facilities for their own pioneering research. Founded in 1931 on the belief that the biggest problems are best addressed by teams, Berkeley Lab and its scientists have been recognized with 17 Nobel Prizes. Berkeley Lab is a multiprogram national laboratory managed by the University of California for the U.S. Department of Energy’s Office of Science. DOE’s Office of Science is the single largest supporter of basic research in the physical sciences in the United States, and is working to address some of the most pressing challenges of our time. For more information, please visit energy.gov/science.

Jul 23 • 11:00 AM EDT • Science • newscenter.lbl.gov

Dimension Capital's $800M third fund shows the intersection of science and compute is booming

The four-year-old firm's latest fund is 60% larger than its second vehicle announced 18 months ago.

Jul 21 • 9:27 PM EDT • Science • techcrunch.com

How Americans Are Engaged With News, Politics, Religion and Civic Life

Americans’ engagement with others is not one-dimensional. Instead, they sort into four distinct groups that reflect different patterns of participation in society.

Jul 16 • 9:36 AM EDT • Politics • pewresearch.org

Physicists finally build a quantum material predicted more than a decade ago

Researchers have achieved a major milestone by creating a long-sought two-dimensional quantum material and confirming its unusual conducting edge states. The ability to control these states through strain could make the material a promising platform for future room-temperature quantum electronics.

Jul 10 • 8:00 PM EDT • Science • sciencedaily.com

Scientists may have finally solved the black hole information paradox

Researchers have proposed that black holes stop evaporating at the last moment, leaving behind tiny remnants that preserve all the information they contain. The same seven-dimensional geometry behind this idea could also help explain why elementary particles have mass.

Jul 4 • 8:00 AM EDT • Science • sciencedaily.com

Professor, Mentor, Researcher, and Data Pioneer: Celebrating Lynn Blewett’s Retirement

I first met Lynn Blewett as a graduate student at the University of Minnesota School of Public Health, where her courses on the U.S. health care system fundamentally shaped how I understand policy and evidence. What struck me most was her ability to translate complex health systems into their human dimensions and to remind us […]

Jul 1 • 9:30 AM EDT • Health • ccf.georgetown.edu

The Arts and Sciences of Judo: The New Edition Expands the Frontiers of Knowledge

The publication of Volume 6, Number 1 of "The Arts and Sciences of Judo" marks another important milestone in the development of judo research worldwide. As the International Judo Federation's interdisciplinary journal, under the supervision of Professor Sanda Čorak, it has become a recognised platform where science, education and the values of judo come together to deepen our understanding of the many dimensions of our sport. It also forms an integral part of the IJF Academy's mission to promote education, lifelong learning and the dissemination of knowledge throughout the global judo community.

Jun 27 • 10:12 PM EDT • Science • ijf.org

Digital Science launches self-citation screening tool

Dimensions Citation Check identifies self-citation, assesses its significance, and helps editors make informed decisions

Jun 16 • 5:00 AM EDT • Science • researchinformation.info

Digital Science Launches Dimensions Citation Check API for Self-Citation Risk Screening

London, United Kingdom--(Newsfile Corp. - June 16, 2026) - Digital Science, a leading technology company serving stakeholders across the research...

Jun 15 • 8:00 PM EDT • Science • newsfilecorp.com

Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?

Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.

Jun 14 • 3:14 PM EDT • Technology • newsletter.semianalysis.com

What It Takes To Be A Top Tier Entertainment Lawyer in 2026

Share I’ve recently run several popular posts breaking down data related to sought after legal jobs. General Counsel Big Law Appellate Attorney Here is another in this series. Two Lawyers, One Elite Market Entertainment law can sound like a single professional category. In practice, the lawyers who reach the top of the Hollywood market often look quite different from one another. Consider two attorneys from the 2025 top-entertainment-law universe. Lesley Freeman represents one route: the company-side entertainment lawyer. She is chief legal officer of AGBO, where she oversees company-wide business and legal affairs across film, television, video game and interactive experiences, and technological innovation, after senior legal roles at MGM, Amazon MGM Studios, HBO, and O’Melveny. Daniel Petrocelli represents another route: the outside-counsel trial lawyer. He is chair of O’Melveny’s trial practice and a vice chair of the firm, with a national litigation practice that includes entertainment, sports, and media disputes. Their careers differ by platform, role, practice area, and professional identity. One sits inside an entertainment company; the other practices from a major law firm. One is associated with corporate and governance work; the other with litigation. Yet both fall within the same publicly recognized top tier of Hollywood lawyers. That contrast points to the article’s central question. If there is no single mold for a top entertainment lawyer, are the paths simply idiosyncratic, or do they follow recurring patterns? The data suggest the latter. The attorneys recognized on The Hollywood Reporter and Variety’s 2025 top-attorney lists do not follow one career template, but their paths are not random. They cluster around several defined routes: entertainment-focused private practice, company-side or operator experience, corporate and finance conversion, litigation conversion, public-service-to-litigation pathways, and smaller specialized lanes in labor, employment, and celebrity family law. Across those routes, the recurring ingredients are platform strength, educational capital or Los Angeles market proximity, long career tenure, specialized practice identity, and entertainment-industry fluency. The article examines five dimensions of the top-attorney sample: route into entertainment law, firm or organizational platform, education pipeline, seniority, and practice specialization. Data and Methodology The dataset includes 103 attorneys drawn from The Hollywood Reporter and Variety’s 2025 lists of top entertainment or Hollywood attorneys. For each attorney, the dataset tracks current organization, law school, J.D. year where available, first-known bar admission year, practice area, prior roles, platform type, and route into entertainment law. The sample is best understood as a recognized-attorney dataset, not a census of all entertainment lawyers. It captures lawyers who reached public top-tier recognition in 2025, rather than every lawyer practicing in the entertainment sector. Multiple but Defined Routes Into Entertainment Law The first question is how these lawyers entered the entertainment-law market. Because every attorney in the dataset is entertainment-related by definition, the key distinction is not whether they practice entertainment law. It is how they got there. The largest group followed what might be called the entertainment private-practice route. These attorneys appear to have built their practices around entertainment, media, talent, music, rights, production, intellectual property, or adjacent industry work relatively early. That route accounts for 40 of the 103 attorneys in the sample, or 38.8%.

Jun 8 • 12:46 PM EDT • Entertainment • legalytics.substack.com

The cult of objectivity has broken consciousness science

With 22 competing theories and no consensus in sight, the science of consciousness is lost. In this exclusive IAI interview, Berkeley psychedelics researcher and bestselling author of a new book on consciousness Michael Pollan insists that even though consciousness lies beyond traditional forms of scientific investigation, we should resist becoming dualists who see it as something radically different from ordinary stuff in the world. Instead, he makes the case for reimagining science itself: it must stop reaching for objective descriptions of physical reality, and instead embrace subjectivity as the indispensable core of all inquiry. Alasdair Craig: How did your experiences with psychedelics get you interested in consciousness?Michael Pollan: One of the things that happens on psychedelics is that they foreground consciousness. What formerly seemed perfectly transparent and ever present—and yet, non-existent, as water is to fish—suddenly you see it. The metaphor I use in the book is that psychedelics sponge the windscreen. Suddenly you realize: wow, there’s a windscreen, there is this phenomenon that’s mediating my relationship to reality. This is not an unusual realization on psychedelics. I think a lot of people are called to think about consciousness after psychedelic experiences. So that was the proximate inspiration for A World Appears: A Journey Into Consciousness (2026).And then there was a more specific way in which psychedelics influence the book. That was a particular experience I had on psilocybin. I had the sensation that the plants in my garden were conscious and returning my gaze, with their own point of view and agency, and I got curious as to how to evaluate an insight like that. I mean, what’s the truth quotient of insights you have on psychedelics? And I was reading William James—who, of course, wrote beautifully about mystical experience—and he said, we can’t judge the metaphysics here, but we should pay attention to two criteria: (1) How useful is it to think this is true? He was a pragmatist, of course. And (2) can we subject it to other ways of knowing to validate it? Because maybe we should treat these insights as hypotheses. And that’s kind of how I approach psychedelics, as a great generator of hypotheses, but they need to be tested against other ways of knowing. And so that led me down this long path exploring the science of plant intelligence and plant sentience.AC: I love your phrase, “smudging the windowpane of conscious experience.” So do you now start to think, actually, even when I’m not on psychedelics, I’m just seeing a screen all the time, which is not reality, but rather is my conscious experience, behind which reality is hidden?MP: Well, you know, not when I’m brushing my teeth and making breakfast! But yes, in meditation, certainly. I mean, one of the things you realize is that my experience happens to be this way now, but it could be another way. And many things can affect it. My morning coffee changes the screen in various ways, sharpens certain things.___The only tool we have to understand consciousness is consciousness.___There’s this wonderful metaphor in Aldous Huxley’s book, The Doors of Perception, where he thinks we channel consciousness, and that what the brain does is edit it, and there’s a reducing valve. And psychedelics open the reducing valve wider. I don’t know that I’m ready to buy into the idea that consciousness exists outside brains, but I do love that metaphor because there are times when you are more conscious than others. I know I’ve switched from window pane to valve, but you know, a camera aperture can open wider or narrower. And I do have a sense of that. I have a sense of when I’m being less conscious, and when I’m being more conscious, by which I mean, you know, more present, taking in more sensory information. So when you start thinking about consciousness as a matter of degree, that changes things also.I think when we scroll on social media, obviously, we’re conscious. But minimally so, because we don’t have to generate our own thoughts. We’re basically taking these little hits from other people and thinking their thoughts.The process of writing this book made me kind of relativize everyday consciousness as just one type, which is exactly what William James said. Normal consciousness is one type, separated by the flimsiest of screens from the other types.AC: If we stick with the metaphor of the smudge on the window that you get when you take psychedelics, it seems like we’re saying that consciousness has become like an object that you’re looking at, right? You’re looking at the smudge and that just is consciousness. But sometimes we’ll talk about consciousness as a state that you’re in, rather than an object you can perceive. You’re either conscious or you’re not conscious. So it’s difficult to really know what sort of thing we’re talking about when we talk about consciousness, right?MP: Yeah. When you say that consciousness is an object, what’s the subject? Consciousness also? The only tool we have to understand consciousness is consciousness. So we’re in a closed loop and when we get a perspective on consciousness, we’re not achieving any distance from it. That’s one of the problems with studying consciousness. Science is predicated on an objective, God’s eye view of things, and you never get that. There’s no such thing. SUGGESTED VIEWING The brain filters consciousness With Àlex Gómez-Marín But, yeah, there is this sense, I think, that consciousness is something you can approach. Certainly, when you’re writing and trying to recreate a conscious experience, it’s a fiction, but you’re standing back from it, and looking at it. But there’s no real subject-object distinction.AC: That’s so interesting, because when philosophers start talking about consciousness, they often talk about what they call “qualia”, which is their word for the felt experience of, say, the color red. And I think that way of speaking often makes us think of the qualia as an object, which you can see out there: the redness of red. But, as you say, we also want to collapse the subject-object distinction when we talk about consciousness. So there’s something strange going on here…MP: Oh, yeah, there are many strange things going on! *AC: Let’s talk about the varieties of consciousness. Apart from perceptions, there are, pains, emotions, thoughts, and so on. What is it that holds all this diversity together so that they all count as instances of consciousness? What is it that they all have in common?MP: Yeah, that’s a really good question. I mean, there is sensory information, right? Which we perceive coming from the world outside ourselves. And then there’s internal information, which is what’s called interoception. And this is very important too. This is where feelings come from—what are sometimes called homeostatic feelings—that are intended to get the brain to keep us in these narrow ranges of temperature and glucose and so on. That’s a very important part of consciousness. And according to some researchers, who I think are probably right, this is where consciousness begins, with these very primal feelings, like hunger and thirst and warmth and itch, and things like that. And then there’s this third thing, which is our thinking about thinking.And what holds all this together is, I think, the sense of self. Consciousness generates a self: it is probably an organizing principle. All this stuff is happening to the self. It’s a construct, I think, but it is very useful. It can connect all these different streams of consciousness to a single being or a place, metaphorically speaking.* AC: The first half of your book is about the science of consciousness. Is consciousness just another thing, like black holes or the origin of life, which we don’t yet understand, but which we should have every hope that science will one day get to the bottom of, or is there something special about consciousness that makes this unlikely?MP: It depends how you define science. As we define science now, it’s going be very difficult. Science since Galileo has had a set of rules or assumptions, which is that the proper remit of science is to deal with the objective, quantifiable, third-person world. And the physical sciences have done amazing work under that set of limitations. Galileo—for tactical reasons, not for philosophical reasons—said science should not deal with the soul, which at the time was what consciousness was considered to be. So what is subjective, what is qualitative, what is first person, we’re going to leave to the church, he said. And this was a good agreement, and it probably kept many scientists from getting burned at the stake. But it leaves science in an awkward spot, now that it wants to venture into that territory of qualities, of first-person experience. And I don’t think it has the proper tools. I think it will have to add to its toolkit in some way, and find a way to bring in phenomenology, or lived experience and introspection, which science is usually dismissive of.The challenge—we alluded to it earlier—is that the only tool you have to study consciousness with is consciousness. And what I mean by that is, the whole scientific enterprise is a manifestation of consciousness. As much as scientists like to flatter themselves with this idea that they attain a godlike perspective on what they study, when it comes to consciousness, there’s no such thing. And it’s fine for all the things you can step outside of and study from that perspective. But two areas it won’t work are consciousness and cosmology.___It could be that we live in this anomaly of not believing nature is conscious. And maybe psychedelics are teaching us something we’ve forgotten.___With cosmology, too, you have to study the universe from inside the universe. It’s not that cosmologists haven’t made progress. We know a lot about the age of the universe and expansion and things like that. But we can’t penetrate what happened before the Big Bang. We just don’t have the tools because we can’t stand outside.The fact that there are 22 full-scale theories of consciousness tells you all you need to know: we’re kind of lost. And I was surprised to find that we are more lost than I thought we were when I started this. I thought that there’d be leading theories, or that we had experiments that we could conduct that would nail some of this down. And the fact is, we don’t.So, I don’t know if science can solve it. But, of course, we can change the rules of science. A really influential book for me was a book called The Blind Spot, by two physicists, Marcello Gleiser and Adam Frank, and a philosopher, Evan Thompson. It’s a reminder that science is a social practice. It’s organized in a certain way and it can be organized in a different way. But it has this huge blind spot at the center of it, which is its failure to recognize that it is a form of consciousness itself, and it doesn’t have a good way of taking account of lived experience.AC: On the one hand, I think you want to resist traditional dualism, which would say that consciousness is something magical, something supernatural, right? But on the other hand, you’re accepting that there is this division in reality between the stuff that you can investigate objectively and measure, and so on—the stuff that science has been good at finding out about—and consciousness, which, for some reason, you can’t objectively measure. Some would take this to suggest that the dualism is actually right. Is there a way of reconciling these two strands of your thinking?MP: To call it magical is full of value judgement. I mean, you could just say immaterial. The interesting thing is, I think, that intuitively we’re all dualists. And I don’t know whether that’s because we’re children of Descartes and other cultures are less dualist than we are. Or it may be because that’s how consciousness feels. It feels different than the body. It feels separate from the body. But I don’t think we should trust that intuition.AC: So let’s think about ways that science might be changed to get at consciousness. I suppose the starting point would be the way that you begin the second half of your book. You have this nice line from William James, where he says, “We now begin our study of the mind from within.” Could you give us some sense of the ways of studying the mind from within? What does this involve?MP: I don’t know what that science looks like. But one of the points I’m making is that it depends on the humanities. I found that I learned as much, if not more, about consciousness, from reading novels and poetry. There is a sense of the fullness and complexity of consciousness that you don’t get in any scientific account. I interviewed this stream-of-consciousness writer and I approached her as an expert on consciousness, and she is. So I think that dialogue is really important.I’m reading Ben Lerner’s new novel, Transcription. Just read the first page of this novel: it’s a man falling asleep on a train, going to conduct an interview, and there is the experience of being in the train, facing backwards, there’s the view outside, but there’s a reflection of himself through which he’s seeing outside. There’s the memory of dropping his kids off at school. All this is going on in one moment of consciousness. Scientists aren’t going anywhere near that. But I think it’s useful for them to think about. That’s where we’re trying to go: like, how does such a layered experience happen? You know, it also makes you wonder, could a computer ever do this? And it gives you some doubt.*AC: Before we get to computers, perhaps we could talk briefly about plants. How did you come to feel that they are sentient?MP: Well, it was a psychedelic experience, and it’s not unusual on psychedelics. In fact, there’ve been studies about how people become animists during psychedelic experience. Their belief in animism arises after a single psychedelic experience.You know, most scientists would say this is all a myth. But we have only 400 years of the age of enlightenment and science. Before that, we were animists, and if you go around the world, most indigenous cultures are still animists, and children are animists, by and large, until they go to school. So it could be that we live in this anomaly of not believing nature is conscious. And maybe psychedelics are teaching us something we’ve forgotten.As I said, I wanted to test this idea, and see whether there was conventional scientific evidence for it. And there’s fascinating work going on in a field that calls itself—in a rather cheeky way—plant neurobiology. These are people who fully realize there are no neurons in plants, but they’re trolling conventional botanists! And they’re doing experiments that are demonstrating that plants can learn and remember, which is kind of amazing: how do you store a memory without neurons? They’re finding plants that can solve problems, that can hear and see. In fact, they have 20 senses to our five or six. For example, a bean plant looking for something to twine, and given a pole within eight inches or so of it, knows where that pole is and will aim its spiraling reach at that pole. What is that about? Is it bouncing signals off of it?One of the spookiest things is the fact that the same anesthetics that put us out put plants out. You might think that plants are already out, but they’re not. They’re just slow. If you take a plant with a fast behavior, like a Venus flytrap, and give it an anesthetic, it will stop reacting. So you have to ask yourself, what is lost when the plant is anaesthetized? Some state of alertness, of awareness, of its environment, of reactivity. I’m not prepared to call that consciousness, but maybe it’s sentience—which is a simpler form of consciousness, and involves the ability to sense what’s going on in your environment and assess what’s good and bad for you and act appropriately. That may be a universal quality of life.AC: Let’s turn from plants to AI. You point out that LLMs are trained on the internet rather than direct interactions with reality. You put this really nicely when you say the internet is not the world so much as a shadow cast by the world. So LLMs are living in this kind of shadow world, or in Plato’s cave, as you put it. What’s the significance of this for AI consciousness and moral consideration? And, to recall the beginning of our conversation, if we’re stuck behind a veil or screen of consciousness, are we also stuck in a kind of shadow world?MP: I don’t think they’re the same shadow worlds because our world includes nature and other people. And even if it’s mediated in some ways... There is a reality out there, and we are in relation to it, through consciousness. There’s friction with it. What’s missing from the LLMs is that friction with the real world. There’s more to the world than human representation, which is what they’re dealing with. And that means that so far, AI is a cultural technology for combining thoughts we’ve already had. SUGGESTED VIEWING Cracking the code for thought With Roger Penrose, Sabrina Gonzalez Pasterski, Max Tegmark, Güneş Taylor Genuine creativity is more than collage. A lot of what AI does now is tantamount to collage, putting this with that and you know, that’s part of art, certainly. But there are also genuinely new ideas that come into the world that don’t come in through manipulating the representations we already have. So it remains to be seen whether AIs can be truly creative in that more radical sense.But my arguments against AI becoming conscious have to do with the fact that the idea of AI consciousness is based on this faulty metaphor that the brain is a computer. There are dimensions in which the brain is like a computer—it certainly does its share of computation. But computers have this sharp distinction between hardware and software, and brains don’t. In a brain, hardware and software are identical. Every memory is a physical change to the brain. Brains are not interchangeable in the way computers are. So this idea that you could take the consciousness out and somehow run it on another substrate, a silicon substrate, seems foolhardy.Anyway, it’s a more extended argument, and I may be wrong. And when we move to computers that aren’t based on silicon—neuromorphic computers and things like that—all bets may be off.AC: Regarding your point about LLMs being stuck in the world of our representations—the internet or whatever—and not being able to interact with reality, are these representations, the world of the internet, themselves part of reality? We’ve created the internet, but it’s still a real thing that exists. And so while the LLMs may be trapped within that part of reality, they’re nevertheless within reality and interacting with it and so on. So it’s not obvious that there’s a barrier there to them becoming conscious and being creative.MP: Yeah, I mean, if our consciousness is built out of human culture, which is what we’re talking about with all those representations. But I tend to think consciousness comes a bit more out of nature and friction with the natural world, but...AC: So there’s a fundamental divide between the natural world and human artefacts?MP: And we lose track of that, and especially people in this computer world. You know, the people who are creating these AI systems, my guess is they’ve been into video games since the age of three, and they didn’t go outside a lot. And their own contact with nature is somewhat limited. I could be wrong, it’d be a very interesting thing to ask, all the wizards of AI, whether they like to go fishing and hiking and do things like that. Or were they on computers from a very early age? I interviewed Blake Lemoine, the Google engineer who came to believe that LaMDA, the Google LLM out at the time, was conscious and deserved personhood. It was very clear that he didn’t see a distinction between this bubble in which he lived and the real world. And I think we’ve all been distanced from the natural world, and this is taking us even further away. But it’s still there, you know, and we still have bodies, and we’re still mortal, and we don’t live in a simulation.AC: I think that’s a great place to finish. Michael Pollan, thank you very much!

Jun 3 • 8:00 AM EDT • Science • iai.tv

The Dropout lineup that is redefining modern entertainment

From 'Dimension 20,' and 'Game Changer' to 'Very Important People,' how Dropout rolled the dice and won.

Jun 2 • 8:00 AM EDT • Entertainment • mashable.com

Where do you rate Great American Ballpark?

I was in Cincinnati and Great American Ballpark. I have to say, regardless of the outcome, that I really liked it. Yes, it’s small. Not just the outfield dimensions, though. It’s cute, as the wife remarked. I feel that the rows are closer together in the lower bowl. I didn’t realize how pitched the right […]

May 31 • 9:36 AM EDT • Sports • sports.yahoo.com

Cowboys HC Schottenheimer looking to 4th dimension to gain advantage

In order to gain any advantage, Brian Schottenheimer is making a major change.

May 27 • 5:02 PM EDT • Sports • sports.yahoo.com

Dropout curious? Here's where you should start watching.

From "Dimension 20" to "Game Changer" and beyond, we tell you the best launch points for this streaming comedy platform.

May 23 • 5:00 AM EDT • Entertainment • mashable.com

Chemist Rebekka Klausen wins prestigious Brown Investigator Award

Klausen will use the award money to pursue basic science that pushes the frontiers of three-dimensional silicon structures

May 19 • 8:15 AM EDT • Science • hub.jhu.edu

Scientists claim our dreams are real in another dimension

You know those dreams that feel way too real? The ones with full storylines, familiar places, recurring people like you didn’t imagine them but went there.

May 18 • 1:04 PM EDT • Science • geekspin.co

New MatterChat Model Helps AI to ‘See’ the Language of Science

From writing emails to generating computer code, much of the artificial intelligence prevalent in our daily lives has succeeded by mastering one domain: text. However, this leaves a major blind spot in the physical sciences, where models depend on the high-resolution, three-dimensional data of the physical world, like the intricate lattice of atoms in a crystal. Delivering on the promise of using AI for science requires teaching these data-driven text models to seamlessly “talk to” physics-based models. Now, a new AI framework from Lawrence Berkeley National Laboratory (Berkeley Lab), called MatterChat, solves this problem by creating a specialized “bridge.” It connects the conversational power of a Large Language Model (LLM) with a physics-based AI that models “interatomic potentials”: the complex physical forces between atoms. The resulting system already significantly outperforms general-purpose AI tools like GPT-4 at predicting material properties, and the team hopes it can accelerate scientific discovery by serving as a robust research partner that provides grounded insights and generates step-by-step instructions for synthesizing novel materials. A paper describing this work was recently published in Nature Machine Intelligence. “Traditional simulations can provide the physical rigor required for materials science, yet their computational cost remains prohibitive for high-throughput screening. Conversely, while LLMs excel at rapid knowledge synthesis, they inherently lack the ‘structural vision’ to interpret materials directly from their underlying atomic coordinates,” said Yingheng Tang, a postdoctoral researcher in Berkeley Lab’s Applied Math and Computational Research Division (AMCR) and lead author on the paper. “MatterChat was built to solve this dilemma, empowering LLMs with a structural ‘vision’ that allows researchers to leverage their full potential for solving complex, real-world materials challenges.” Empowering language models to solve complex challenges in materials science To build MatterChat, the Berkeley Lab team drew inspiration from technologies like Vision Question Answering (VQA) and Text-to-Image (T2I) generation. In these tasks, AI must translate high-level text concepts into visual images, or vice versa. Doing so requires developers to build tools that “bridge” two fundamentally different forms of data. The researchers adapted this concept to the physical sciences. With MatterChat, they created a “bridge model” that successfully connects an LLM’s general knowledge with the deep understanding of the atomic-scale world encoded in scientific interatomic potentials. Until now, researchers using LLMs to solve materials problems usually had to feed them raw data files as if they were just strings of text. It’s like asking an AI to understand a complex 3D engine based only on a parts list: the LLM can read the names, but it can’t “see” how the atoms fit together in space. MatterChat solves this by training a specialized AI bridge model, pre-trained on millions of crystal structures and an LLM, to align the LLM’s representation of the world with the interatomic potential’s representation of the world. The bridge model can translate physical insights into a format the LLM can actually understand. By giving the LLM these “scientific eyes”— a scientific “inductive bias” in the terminology of AI — the Berkeley Lab team has transformed it into a robust research tool capable of providing grounded scientific insights into complex materials challenges, such as predicting thermal stability or analyzing electronic band gaps. “We think of atoms as living in a physical space, but from a machine learning perspective, they are just vectors living in some very non-trivially structured manifold in a high-dimensional Euclidean space; and, of course, the same is true for the sentences and paragraphs that we use to express our ideas about those atoms,” said co-author Michael Mahoney, Berkeley Lab’s Scientific Data Division (SDD) AI Initiative Research Lead. “The bridge model basically gets those two structures to ‘talk with’ each other.” As a proof-of-concept of this general approach, the team trained their bridge model on a dataset curated by pairing nearly 143,000 stable atomic structures from the Materials Project with their corresponding physical properties. This training data was automatically assembled using the Materials Project’s API and deliberately enriched with properties fundamental to microelectronics design — like formation energy and bandgap — allowing MatterChat to learn the complex patterns connecting a material’s atomic blueprint to its functional performance. To validate their model, the researchers benchmarked MatterChat against a suite of other AI systems, from general-purpose LLMs to other specialized scientific AI methods. The results show that MatterChat consistently outperformed its competitors across a range of tasks. The model was more accurate in classifying material types and demonstrated superior precision in predicting numerical properties. For example, it excelled at predicting a material’s bandgap, a property critical for designing new electronics from high-capacity energy storage to next-generation computer chips. “Our design is significantly more efficient because we don’t have to build a massive AI model from the ground up,” said co-author Zhi (Jackie) Yao, a research scientist in Berkeley Lab’s AMCR. “Instead, we take two powerful, pre-trained models — a structural encoder for materials physics and an open-source LLM — and use them off-the-shelf. The only component we actually train is the lightweight ‘bridge model’ that translates between them. It’s the difference between building an entire car factory and simply designing a smart adapter that connects a world-class engine to a world-class navigation system. This approach is not only computationally efficient, but also makes the system modular, so we can easily upgrade components or adapt the bridge for other scientific domains in the future.” Crucially, this modular design highlights exactly how institutions like Berkeley Lab and the Department of Energy are carving out a highly valuable niche in the booming AI landscape. Rather than competing with Silicon Valley tech giants to build ever-larger language models from scratch, the lab is focusing on the specialized connective tissue that makes commercial AI useful for hardcore science. Because the bridge model approach underlying MatterChat is forward-compatible, it is perfectly positioned to leverage these parallel tracks of innovation. As Mahoney pointed out, “We expect that industry will continue to develop improved LLMs, and we expect domain scientists and facilities will continue to generate new data. An important part of scientific machine learning is not simply to solve problems on today’s data, but instead to develop general methods that will be forward-compatible with orders of magnitude more data, whether from scientific domains or from LLMs.” According to Yao, the MatterChat project, which was initially developed and enhanced with funding from a Berkeley Lab Laboratory Directed Research & Development (LDRD) Program, will now expand its capabilities. In a collaboration with Fermilab, MatterChat is already contributing to a U.S. Department of Energy Genesis Mission project — called Accelerating eXtreme Environment Specs-to-Silicon (AXESS) — that aims to speed up the development of next-generation, high-speed, radiation-hardened detectors for challenging particle physics experiments by using advanced 3D integrated circuits (chiplets) and AI-driven data analysis. In addition to the LDRD support, the team also credits supercomputing resources at the National Energy Research Scientific Computing Center (NERSC), located at Berkeley Lab, with MatterChat’s success. “We are incredibly grateful to NERSC; this research simply would not have happened without access to the Perlmutter supercomputer through their AI for Science program,” said Tang. Wenbin Xu, a NERSC postdoctoral fellow at the time, was also a major co-author of the work, as was Benjamin Erichson, a research scientist in Berkeley Lab’s SDD, highlighting the benefits of AMCR-SDD collaboration on AI for science. ### Lawrence Berkeley National Laboratory (Berkeley Lab) is committed to groundbreaking research focused on discovery science and solutions for abundant and reliable energy supplies. The lab’s expertise spans materials, chemistry, physics, biology, earth and environmental science, mathematics, and computing. Researchers from around the world rely on the lab’s world-class scientific facilities for their own pioneering research. Founded in 1931 on the belief that the biggest problems are best addressed by teams, Berkeley Lab and its scientists have been recognized with 17 Nobel Prizes. Berkeley Lab is a multiprogram national laboratory managed by the University of California for the U.S. Department of Energy’s Office of Science. DOE’s Office of Science is the single largest supporter of basic research in the physical sciences in the United States, and is working to address some of the most pressing challenges of our time. For more information, please visit energy.gov/science.

May 18 • 11:00 AM EDT • Science • newscenter.lbl.gov

Scientists catalog the ‘fractal dimensions’ of more than 130,000 islands

The “coastline paradox” helped to define fractals, but coastlines themselves turn out to be less fractal than thought

May 16 • 7:00 AM EDT • Science • scientificamerican.com

Seaport Entertainment Group and the Team Behind Public Records Announce Partnership to Open New Project in New York City’s Seaport Neighborhood

NEW YORK, May 14, 2026--Seaport Entertainment Group (NYSE: SEG) today announced a partnership with Public Service, the organization behind Public Records, to develop a new project in the Seaport in Lower Manhattan. The restaurant concept, which will involve the revitalization of a historic building, is expected to open in 2027. This addition brings an exciting new dimension to one of the most iconic waterfront neighborhoods in New York City.

May 14 • 7:00 AM EDT • Entertainment • finance.yahoo.com

Soil science reimagined: from farmland to the final frontier

Soil science is undergoing a profound transformation, evolving from its traditional focus on agriculture to a multidimensional discipline addressing some of the most urgent challenges of our time. A new perspective calls for expanding the boundaries of soil science to include nontraditional domains—such as climate regulation, urban resilience, forensic investigations, cultural heritage protection, and extraterrestrial exploration. The study proposes a systems-based framework that recognizes so

May 11 • 7:30 PM EDT • Science • newswise.com

Samsung Finally Fixed the Fold: First Look at the Z Fold 8 Wide Design

Get a first look at the Samsung Galaxy Z Fold 8 Wide design changes, including a refined dual-camera setup and updated screen dimensions.

May 9 • 11:00 AM EDT • Technology • geeky-gadgets.com

Physicists discover quantum particles that break the rules of reality

Physicists may have just cracked open a hidden side of the quantum world. For decades, every known particle was thought to belong to one of two categories — bosons or fermions — but researchers have now shown that bizarre “in-between” particles called anyons could also exist in a one-dimensional system. Even more exciting, these strange particles may be adjustable, allowing scientists to tune their behavior in ways never before possible.

May 9 • 8:00 AM EDT • Science • sciencedaily.com

Scientists Think the Fifth Dimension May Exist—and It’s Hiding Behind the Universe We Know

On the latest episode of “The Astounding Pop Mech Show,” Shawn Gorman and John Gilpatrick discuss how reality may have been missing an entire layer all along.

May 8 • 2:43 PM EDT • Science • yahoo.com

Scientists Think the Fifth Dimension May Exist—and It’s Hiding Behind the Universe We Know

May 8 • 2:43 PM EDT • Science • popularmechanics.com

Quantum topology emerges at near field

Light: Science & Applications - Near-field nanophotonics platform with spin-orbital coupling enables single-photon skyrmions with robust topological structures for high-dimensional quantum...

May 7 • 8:00 PM EDT • Science • nature.com

Scientists finally solve 40-year-old physics puzzle about how things grow

In a major breakthrough, scientists have experimentally confirmed a universal growth law in two dimensions using a quantum system of fleeting light–matter particles. The finding strengthens the idea that wildly different processes—from crystals to living systems—may all follow the same hidden rules.

May 6 • 8:00 AM EDT • Science • sciencedaily.com

Scientists Found a Surprising State of Matter That's Breaking Dimensional Rules

A new kind of anomalous Hall effect produces transdimensional matter.

May 5 • 8:00 AM EDT • Science • popularmechanics.com

MIT scientists finally reveal the hidden structure of a mysterious high-tech material

For decades, relaxor ferroelectrics have powered everything from medical ultrasounds to sonar systems, yet their inner atomic structure remained a mystery—until now. Researchers have finally mapped their three-dimensional structure in unprecedented detail, uncovering hidden patterns in how electric charges are arranged at the nanoscale. The breakthrough not only challenges long-standing assumptions about how these materials behave but also allows scientists to refine the models used to design them.

May 4 • 8:00 AM EDT • Science • sciencedaily.com

iPhone 18 Pro Max Is Proof That Apple No Longer Believes Thicker Devices Are Aesthetically Unattractive, As Long As There Are Benefits

A thicker iPhone 18 Pro Max will bring various advantages to the table, as new details reveal the flagship’s dimensions and compared them to the iPhone 17 Pro Max

Apr 26 • 5:14 PM EDT • Technology • wccftech.com

Latest attack threatening President Trump reflects rising political violence in US

The moral dimension of political polarization in the US, where each side views the other as immoral, helps fuel attacks like the one against Trump at the Washington Hilton.

Apr 26 • 4:40 PM EDT • Politics • theconversation.com

Foldable iPhone Ultra confidential docs leak: 9.2mm design, Android-style selfie cameras, color options

Leaked schematics from a case manufacturer detail the possible dimensions of the upcoming iPhone Fold. The leak suggests a folded thickness of 9.23mm - notably thinner than previous 11mm rumors. The drawings outline a 167.59mm x 120.59mm footprint, a significant 13mm camera plateau, and Touch ID on the side.

Apr 25 • 6:54 PM EDT • Technology • notebookcheck.net

Samsung Galaxy Z Fold8 to bring a smaller punch hole for the selfie camera

It's rumored to be slightly thicker than the Fold7, though. While the Samsung Galaxy Z Fold8 is rumored to be slightly thicker than its predecessor, the...

Apr 24 • 9:37 AM EDT • Technology • gsmarena.com

Galaxy Z Fold 8 Wide dimensions, aspect ratios of displays leak

A popular tipster has shared the dimensions and the aspect ratios of both the displays of the Galaxy Z Fold 8 Wide.

Apr 24 • 8:20 AM EDT • Technology • sammobile.com

Scientists Think the Solution to an Infamous Paradox Could Be Hiding in the 7th Dimension

By stopping black holes from fully evaporating, hidden dimensions may solve a cosmological paradox.

Apr 23 • 8:00 AM EDT • Science • popularmechanics.com

Digital Science introduces Compass by Dimensions to transform medical affairs publication insights

Apr 20 • 9:00 AM EDT • Science • newswise.com

Digital Science launches Compass to track real-world publication impact

New platform from tech company combines data from Dimensions and Altmetric into a single, self-service platform

Apr 20 • 8:00 AM EDT • Science • researchinformation.info

Digital Science Introduces Compass by Dimensions to Transform Medical Affairs Publication Insights

Compass unifies citation data and attention metrics in a single solution for real-time publication intelligenceLondon, United Kingdom--(Newsfile Corp. - April 20, 2026) - Digital Science, a leading technology company serving stakeholders across the research ecosystem, today announced the launch of Compass by Dimensions, a dedicated publication impact tracking solution designed for medical affairs teams.Compass - initially available to publication planners and medical affairs professionals in a..

Apr 20 • 5:01 AM EDT • Science • finance.yahoo.com

Digital Science Introduces Compass by Dimensions to Transform Medical Affairs Publication Insights

London, United Kingdom--(Newsfile Corp. - April 20, 2026) - Digital Science, a leading technology company serving stakeholders across the research...

Apr 19 • 8:00 PM EDT • Science • newsfilecorp.com

Stephen Hawking's black hole information paradox could be solved — if the universe has 7 dimensions

Stephen Hawking's theory of black hole evaporation clashes with the laws of quantum mechanics. A new paper finds a way around this paradox, provided that the universe has seven dimensions.

Apr 16 • 5:00 AM EDT • Science • livescience.com

The depths of Neptune and Uranus may be “superionic”

Sophisticated models predict that a quasi-one-dimensional superionic state of carbon hydride exists under the extreme pressures and temperatures found deep inside Neptune and Uranus.

Apr 3 • 8:00 AM EDT • Science • carnegiescience.edu