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'Working Lab' helps Norwich small business owners
Global City Norwich and Foundry66 are accepting applications for a 12-week program to help local businesses grow.
Bend columnist: Art, laughter can light up the darkness
Those of us who work on GO! magazine labored a bit over this week’s issue and what it should look like. GO! is, to me, the fun part of the […]
Regional Entertainment Calendar
Upcoming entertainment events scheduled within a 250-mile radius of Mountain Home include: Wednesday, Oct. 22-Sunday, Oct. 25 Dirty Dancing: The Musical, Walton Arts Center, 495 W. Dickson St., Fayetteville. Tickets: […]
Oregon to increase 2027 payments to care organizations for Health Plan members
Next year, Oregon will pay an average of nearly $630 more per member every month to the organizations arranging providers for the vast majority of Oregon’s 1.4 million Medicaid members […]
Take a look inside Binghamton’s new mental health crisis center
Step inside the new Binghamton crisis center designed to provide a sanctuary for people experiencing a mental health crisis
Romanian lawmakers back government led by independent Luca Niculescu as country seeks to end monthslong political crisis
Romanian lawmakers back government led by independent Luca Niculescu as country seeks to end monthslong political crisis.
Scientists say authors of a controversial government climate report made basic error
Climate contrarians questioned evidence of a human fingerprint on climate change in a report commissioned by the Energy Department. Critics say it was based on flawed analysis.
Punahou Alumni Share Insights on Public Service and Hawaiʻi Politics
Punahou alumni State Rep. Mike Lee ’00 and State Rep. Jackson Sayama ’15 returned to campus on Oct. 14
Star Wars Battlefront 3 Talks In Early Stages With DICE And Bungie, Says Rumor
Star Wars Battlefront 3 might be happening. This is huge news for Star Wars gaming fans as Disney has big plans for the series. They are reportedly in talks with two game development studios over …
Northern NH maternal health organizations receive grants from border commission
The Women of the Mountains Birth Initiative, also known as WOMB, and Families Flourish Northeast Inc. received $119,705 to help tackle the maternal health crisis in northern New Hampshire, the Northern Border Regional Commission announced.
Business Bulletin: Are those “Cloud storage is full” messages real?
If you receive an email warning appearing to be from a company you know and trust that states your online storage is full and your family photos, important documents and other files could soon be deleted ... would you click on the "fix" button?
Star Wars Galactic Racer Devs Reveal They Have Big Plans For More Content
Star Wars Galactic Racer is going to get more content and developers Fuse Games will be making sure the community’s requests are a priority. In a new interview with The Games Business, Fuse …
Regional Entertainment Calendar
Upcoming entertainment events scheduled within a 250-mile radius of Mountain Home include: Wednesday, Oct. 21-Sunday, Oct. 25 Dirty Dancing: The Musical, Walton Arts Center, 495 W. Dickson St., Fayetteville. Tickets: […]
Commentary: New Hampshire sure is beautiful this time of year, apolitically speaking
It’s mid-October, and New Hampshire has never been more stunning. How stunning? The autumn reds and golds are barely muted by the pall of another election season. Not that this campaign cycle hasn’t tried its soulless best to drape the landscape in gray.
La Pine High School loses medical sponsorship
After 10 years the La Pine Community Health Center ended its medical sponsorship of La Pine High School on Oct. 2, causing the Deschutes County Health Services Department to scramble […]
‘Gus the Bus’ to provide free food at Lamprey Health in Newmarket
Gather, a Portsmouth-based food pantry, is bringing its fresh food bus, nicknamed “Gus the Bus,” to Lamprey Health Care’s community health center in Newmarket.
GO-NORTH ‘cautiously optimistic’ ahead of federal rescoring of rural health program
When the federal government announced how much money it was giving New Hampshire as part of its Rural Health Transformation Program, Granite State leaders bragged that the state secured more funding than any other New England state.
Commentary: Healthcare is broken, and it's time for leaders in New Hampshire and the nation to act
Standing outside the New Hampshire State House on Tuesday morning, surrounded by Granite Staters gathered for Protect Our Care’s “Sick of It! Fix Health Care Now” bus tour rally, I spoke about what I saw when I was president of the Manchester NAACP with respect to our broken healthcare system.
Artist opens downtown Walla Walla gallery to the public
Photographs and found-object constructions will be on display Saturdays through Nov. 28 at The Noodle Grotto Studio Gallery.
Business Bulletin: BBB warns of healthcare fraud during open enrollment
If you or a family member are considering changes to your Medicare or Healthcare.gov coverage during open enrollment, your Better Business Bureau (BBB) urges you to be cautious of unsolicited calls, emails, and texts offering to help you find the best plan or deal. Scammers often take advantage of open enrollment to trick people into sharing personal information, Medicare or insurance details, and financial information.
FinnBoy Records, Books & Curio offers curated vintage experience
FinnBoy Records, Books and Curio sits to the west of GU's campus, offering a wide variety of physical media and vintage finds.
“Big Cat Diaries”: A story about accompaniment and connection
Last week, the Magnuson Theatre hosted their performance of "Big Cat Dairies" inspired by a GU professor's experience in the Amazon rainforest.
In Peterborough, a civics quiz: Is Jonah Wheeler proving his independence? Or ignoring his voters?
In Peterborough, there’s something of a political schism playing out over two-term state Rep. Jonah Wheeler, a Democrat who has angered some in town with his votes.
Editorial: Bend small business program challenged by being new
Bend’s new grant program for small businesses is a challenge for the city because it is new and because the city has to be careful when it is giving away […]
Service 1st marks 100 years in business, extends beyond mortgage lending
- Company traces its roots to 1926 and continues to grow with new products and expansion into more vertical markets -
AI doom has a precision problem
Until there is more clarity on basic questions, neither developers nor policymakers can credibly establish a quantitative AI risk assessment.
Central Oregon farmers, ranchers to learn from visiting business school
Three Central Oregon producers will attend a nationally recognized business management school for farmers and ranchers, which will visit Bend during the last week of October. High Desert Food and […]
Ruth Tucker joins the Bulletin
The Bulletin is excited to welcome Ruth Tucker as the nonprofit's Advancement Services Coordinator. As Advancement Services Coordinator, Tucker will support the daily operations of the Advancement team, including gift entry, event registration entry, acknowledgements, and administrative support in the implementation of the department's fundraising tasks.
Polls close in Bosnia in race where pro-Russia politician looms large and ethnic tensions simmer
Polls have closed evening in Bosnia after an election shaped by economic pressures, a youth exodus and concerns over corruption. Some leading politicians stoked ethnic tensions that have divided the
Nuclear doomsday mag says, AI Doomerism is bad science
Bulletin of the Atomic Scientists says AI doom is overrated; implies crass business motives at play.
Bend's newest high school focuses on business and career tech education
Deschutes River High, having just opened its doors last month, is repositioning itself as the magnet high school for Bend-La Pine Schools. The school, on the prior Bend Tech Academy […]
Editor's picks: Highlights in Bend music, art events
First Friday Art Walk You can’t do much better in terms of free entertainment than heading to downtown Bend or the Old Mill District for the monthly First Friday Art […]
Bend cheesecake business launches vending machine
Little Slice of Hell Cheesecakes launched its vending machine of cheesecakes earlier this month at Midtown Yacht Club, giving Bend a new way to grab local, homemade cheesecakes on the […]
Ukraine Health Cluster Bulletin #8 (August 2026)
Situation Report in English on Ukraine about Health and Protection and Human Rights; published on 30 Sep 2026 by Health Cluster
How the bad science of AI doomerism is good for big business
There is no clear path showing that today’s AI systems will lead to superintelligence, much less a basis for calculating the probability of doom.
How the bad science of AI doomerism is good for big business
There is no clear path showing that today’s AI systems will lead to superintelligence, much less a basis for calculating the probability of doom.
Dartmouth Health announces at-home program to address rural challenges after $20M gift
Dartmouth Health and the Geisel School of Medicine at Dartmouth College announced Tuesday they’re launching a new at-home health care program, an effort to address healthcare delivery challenges in rural New Hampshire and Vermont where patients often live far from doctors and health facilities.
Business Briefcase: DSI unveils updated logo design
SHENANDOAH — The “Return to Prominence” revitalization group Downtown Shenandoah Inc. has unveiled a new logo, according to its September-October DSI Herald bulletin. “While our previous logo served us well for many years, it was time for a…
Independence Health System plans upgrades to Latrobe Hospital
Independence Health System plans to enhance the Latrobe Hospital Emergency Department and expand outpatient behavioral health.
Redmond youth mental health facility to break ground Tuesday
Construction on an in-patient youth mental health treatment facility in north Redmond will begin Tuesday. And health care providers say it will fill a much-needed hole in Central Oregon’s health […]
[Science Bulletin] KERI develops direct carbon coating technology for substrates
Korea Electric Research Institute grows graphene and graphite thin films at room temperature while MSIT launches safety inspections for semiconductor labs
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Column: The price of price controls in Oregon healthcare
Oregonians want their politicians to do something about healthcare costs. The politicians have tried. One response from the state Legislature: Price controls. Limit prices and Oregonians may pay less. But […]
Local health care CEOs express concern about Medicaid changes
Federal changes coming to Medicaid in 2027 are already concerning the leaders of St. Charles Health System, Summit Health and Mosaic Community Health. They warned the public in a City […]
Spokane's Teleport Block Party brings local businesses together
A writer goes to Spokane's Teleport Block Party and highlights two local businesses.
Memories for profit: Is influencer marketing becoming too much?
Wimbledon removes accreditation for influencers to attend the U.S. Open.
U2 reveals new album with Dolly Parton's final vocal duet
Fifty years ago this week, drummer Larry Mullen Jr. posted a handwritten note on a school bulletin board seeking "musicians to form band.” Five decades later, that band – U2
The Bulletin wins the Miwon Peace Prize
The Bulletin is honored to be awarded the 2026 Miwon Peace Prize for raising global awareness of existential risks and using scientific rigor to warn humanity about planetary threats.
Building the future: UMass celebrates $125M Computer Science Laboratories
AMHERST — Inside a room at the Physical Computing Makerspace on the University of Massachusetts campus, a 3D printer is fabricating a chalk case that a teaching assistant will use to carry writing utensils. The case’s design started as a computer file, drawn up nearby by Bennett Gillig, a UMass graduate student pursuing a master’s […]
BBC to axe sports bulletins on its news channel
Cuts are part of plan to save £500m and lose as many as 2,000 staff by 2028
UConn’s Dan Hurley voices support for Protect College Sports Act
Dan Hurley says he supports the Protect College Sports Act, calling for national rules on NIL pay and transfers as UConn opens practice this week
Texans throw some weird bulletin-board material after Bengals beatdown
A comment in the aftermath of the Bengals routing the Texans is starting to get attention.
Editorial: Central Oregon getting needed children's mental health facility
The emergency room at St. Charles hospital Bend is not the ideal place for a child to get mental health care when they are in crisis. But there can be […]
Business Bulletin: AlignLife expands; AAA Translation rates; MU Health Care earns
Catch up on local business awards, acquisitions and donations.
Commentary: Dancing with the W2 Stars reaches far beyond one evening of entertainment
Let me tell you the “why” behind a cheeky dance competition and your friend’s relentless hints for donations: Valley Residential Services, writes Sheila Hagar.
Can windows cool buildings without electricity?
Thermochromic smart windows can automatically adjust solar and thermal radiation in response to temperature, offering a passive route to reduce building energy demand and improve indoor comfort. A new review published in Science Bulletin examines why these windows have not yet achieved large-scale application, despite rapid materials progress. The authors identify key challenges in spectral regulation, switching temperature, response speed, durability, scalable fabrication, glazing integration, lifecycle impacts, and building control. They argue that future development should shift from isolated material optimization toward deployment-oriented design and system-integrated adaptive building envelopes.
DOL/EBSA Narrows Mental Health Parity Enforcement Focus to Three Priority Areas
On September 8, the Department of Labor's Employee Benefits Security Administration (EBSA) issued Field Assistance Bulletin No. 2026-03, outlining how it
Dartmouth Health lays off 124 in effort to ‘improve long-term sustainability’
Dartmouth Health, the hospital system that operates eight hospitals and clinics throughout New Hampshire and Vermont, announced this week that 124 employees have been laid off and 303 openings canceled, for a total of 427 positions terminated.
Tim Cox rejoins Informative Research to lead the company’s business process automation efforts
GARDEN GROVE, Calif., Sept. 17, 2026 (SEND2PRESS NEWSWIRE) — Informative Research (IR), a leading technology provider of data-driven credit and verification solutions for the lending industry, today announced that Tim
ACA health coverage enrollment in NH declined by an estimated 4.8K after tax credits expired
After a set of tax credits designed to help Americans afford healthcare expired, 4,868 fewer New Hampshire residents were enrolled in ACA Marketplace healthcare plans, according to an analysis of federal data by KFF.
From immigration to voting to education, the pointed politics of the deep freeze
There is nothing accidental or incidental about the freezing out of immigrant populations. In fact, across policy areas the “freezing” of populations is not only a prong but the point.
Spoiled in Bend: From poop scooping to massages, Bend businesses cater to dogs
On any given day in Bend, one business may be ridding yards of dog waste, another may be pulling a mobile dog gym into a driveway and another may be […]
DOL Mental Health Parity Bulletin 2026: MHPAEA Compliance Best Practices
On September 8, 2026, the DOL's Employee Benefits Security Administration issued Field Assistance Bulletin No. 2026-03 to clarify MHPAEA compliance and nonquantitative treatment limitations. DOL enforcement will focus on blanket treatment exclusions, medical necessity/prior authorization processes, and network adequacy. Read our alert for a practical compliance roadmap.
Health officials urge measles vaccine as school starts
As Central Oregon students return to school, the state is seeing a new low in kindergarten vaccination rates. That comes amid a measles outbreak and public health professionals urging people […]
Science in action program brings Zags and local schools together
The Science in Action program allows any major the chance to get involved with the community.
The jail is a hospital: 90 percent of inmates need physical, mental healthcare
Alexandria Vega, a behavioral health specialist in the Deschutes County Jail, transitions from cell to cell. In one, an inmate is suicidal. In another she provides formal therapy. For a […]
Walla Walla Fair parade brings crowd to Main Street
Attractions abounded for the weekend crowd of Walla Walla Fair and Frontier Days on Saturday, Sept. 5, both at the fairgrounds and in downtown Walla Walla.
VIDEO: Inside an AI-powered lab trying to replace scientists
The Bulletin goes inside the lab to see how it works and ask whether AI can do science without scientists.
General Duffy's Waterhole goes up for sale in downtown Redmond
Owners of a downtown Redmond community gathering place, taphouse, food truck lot and live music and event space have listed it for sale after eight years in business. General Duffy’s […]
A new strategy enables precise fabrication of nanoporous carbon structures
Nanoporous carbon materials have attracted significant interest for applications in lightweight structural materials, microdevices, and bio-integrated systems due to their low density, chemical stability, electrical conductivity, and tunable mechanical properties. However, existing fabrication approaches often struggle to simultaneously achieve precise patterning, controllable porosity, and desirable mechanical performance. A research team led by Professor Min Qiu at Westlake University has developed a new fabrication strategy, termed Mix-ice lithography (Mix-IL), that enables direct construction of nanoporous carbon structures with tunable pore architectures and complex geometries. The study has been published in Science Bulletin.
From climate change to the economy to healthcare, NH voters seek solutions with their ballots
Scott Thompson, a retired mechanic from Epsom, usually doesn’t vote in midterm elections, but after a GOP candidate for state representative showed up at his door he decided to make plans to vote on Tuesday.
Commentary: Who would want the US to be run like a business?
When pushing for the United States to be run more like a business, please keep in mind that framework naturally conflates the populace with labor and public servants with bosses. […]
Risky business: Is Bend maxed out on food carts?
Food carts have been a staple in Bend for over a decade. The arrival of new carts and another pod on the horizon suggests the scene still has room to […]
PrimeGlobal launches APAC initiatives for cross-border business support
PrimeGlobal, an accounting and business advisory association, has introduced two new initiatives across Asia Pacific (APAC) region to support cross-border collaboration.
First Star Wars Zero Company Patch Coming Next Week
The first post launch patch for Star Wars Zero Company is coming very soon. EA Star Wars has finally shared some information about an update and what it will address. This news comes after some ra…
Defeated by physics
The Pentagon's $3.2 billion bet on space-based boost-phase missile defense ignores basic orbital dynamics, offering no real protection while fueling a costly, destabilizing arms race in space.
Health Sector Bulletin August 2026
in English on Syrian Arab Republic; published on 1 Sep 2026 by Health Cluster
Community Bulletin Board #11
Unlock Coen’s full potential. Becoming a Dawnwalker doesn’t come without its share of burdens… but it also grants access to powerful abilities. Coen doesn’t have to rely on his sword alone.
Business Bulletin: Delta Dental and ATB win; Sunset Hills Subaru helps
Catch up on local business awards, donations, certifications and openings.
Science Confirms 'Leisure Guilt' Is Real—and You're Likely Wasting Hours on It
A new study published in Personality and Social Psychology Bulletin reveals that Americans spend a full 14 percent of their downtime worrying about productivity instead of resting.
Higher costs, fewer choices: Another health insurance provider pulls out of Deschutes County
Moda Health will pull out of the Deschutes County individual health insurance marketplace in 2027, leaving residents with just two providers to choose from in 2027. The hundreds of Deschutes […]
Business Bulletin: The Victor wins; Hall Render opens; Belle-Clair reopens; Jump Company earns
Catch up on local business awards, openings and projects.
Beat the clock: The politics of daylight saving time in New Hampshire
The perennial debate over daylight saving time in the U.S. is coming around again, but for one New Hampshire state representative, it's never gone away.
USPTO Expands Category A Patent Bar Admission Criteria to Include Biomedical Science Degree
The USPTO published a Federal Register Notice Tuesday announcing administrative updates to the General Requirements Bulletin (GRB).
Why is climate action “easier said than done”? The key lies in the strong coupling between climate and society
A new Perspective in Science Bulletin argues that the persistent gap between climate science and climate action stems from a conceptual blind spot: treating climate and social systems as separate domains rather than as one integrated, co-evolving entity. The authors introduce the Climate-Social Coupling System (CSS) paradigm and, by re-contextualizing the classic Environmental Kuznets Curve, sort national trajectories into “strong,” “weak,” and “de-coupling” states, showing that governance is the decisive, reversible steering mechanism that determines a country’s climate future.
MDHHS Issues Mental Health Framework Provider Enrollment and Billing Updates
The Michigan Department of Health and Human Services (MDHHS) recently released a final policy bulletin updating enrollment, supervision and billing requirements under the state’s Mental Health Framework.
The Bulletin welcomes Sharon Weinberger as editor-in-chief
The Bulletin’s new editor-in-chief, Sharon Weinberger, has dedicated her career to covering the intersection of science, technology, and national security and will guide the Bulletin’s editorial efforts as it enters its eighth decade of informing the public on catastrophic risks.
Downtown Bend business district transitioning to new board and director
The Downtown Bend Business District is in transition. Its executive director and three board members are stepping down, as property owners vote for seven new board members this week. The […]
American Nero: Why Trump is trying to burn down the National Academy of Sciences
Carnage in pursuit of power, revenge, personal financial gain, and ego.
Eagles Get More Bulletin-Board Material Ahead of 2026 Season
The Philadelphia Eagles are the two-time reigning NFC East champs, and are just 18 months removed from the Super Bowl. The Eagles were 11-6 in 2025, a three-game drop off from the 2024 season where they won 14 games and defeated the Kansas City Chiefs 40-22 in Super Bowl LIX. Plus, Philadelphia fell 23-19 to the San Francisco 49ers in the wild-card round.
Grappling Bulletin: FloGrappling & ONE Championship Enter Strategic Partnership
-FloGrappling and ONE Championship have entered into a strategic partnership that aims to more actively ensure the best in the world will be active and available at the biggest events in the world, including ONE, WNO, and Flo-partnered events like ADCC & IBJJF majors. -Helena Crevar scored a big win at ONE: The Inner Circle 22, defeating Paige Ivetter Clymer by decision. Crevar and Clymer will be both in the same bracket at the ADCC World Championships, with the potential for a rematch.
Central Bend business owners reject economic improvement district
The city of Bend will end plans to create an economic improvement district for the neighborhood east of downtown Bend after a super-majority of property owners did not support the […]
Bend-based entertainment business in 2026 Jefferson County Fair & Rodeo, replacing carnival
The Jefferson County Fair & Rodeo will have a carnival after all. The 541 Bounce Experience will offer waterslides, bounce houses, carnival games, obstacle courses and “more daring, interactive games” […]
Courts won’t settle the fight over AI and creative work: Politics will
“We’re going to live in a world where all of the capital and power concentrates into the hands of five or six companies. That’s not a free society. That’s
New Hampshire student athletes drop lawsuit over state's transgender sports ban
New Hampshire transgender student athletes drop lawsuit against a state law barring them from girls’ sports teams
Ayotte signs three childcare bills into law, including business tax credit
New Hampshire Gov. Kelly Ayotte has signed three bills related to childcare into law.
Long Reads for the Long Weekend
(Welcome to the Entertainment Strategy Guy, a newsletter on the entertainment industry and business strategy. I write a weekly Streaming Ratings Report and a bi-weekly strategy column, along with occasional deep dives into other topics, like today’s article. Please subscribe.) Happy Fourth of July weekend! As has been a tradition of mine going back to the beginning of the EntStrategyGuy website, I’m sharing my favorite long reads of the last year, like I did in 2019, 2020, 2021, 2024, and 2025. Let’s dive right in! Subscribe “Different Prices for the Same Ride: How Uber and Lyft Use AI to Get More Money Out of You“ by Derek Kravitz in Consumer Reports I don’t think surveillance pricing, like the kind described in this brilliant Consumer Reports article, is long for the world—it’s toxically unpopular—but we’ll see if either party takes on this issue. If I ran a political party focused on affordability, I would focus on a few pro-consumer and pro-market policies: Banning non-compete agreements. Ending surveillance pricing Eliminating junk fees (read more here...) Ensuring “right to repair” for consumer (and military!) products Capping excessive app store fees Stopping digital/algorithmic price-fixing tools. Preventing automatic subscription price increases. And more. If you want to fight inflation, there are a lot of great ways to do it quickly. Speaking of higher prices... “Secret Documents Show Pepsi and Walmart Colluded to Raise Food Prices Across the Economy“ by Matt Stoller in BIG Again, I think a political party should focus on lowering prices for consumers. And deals like this—Walmart making a deal/forcing Pepsi to offer the lowest prices at its stores and nowhere else—hypothetically lower prices at Walmart...but raise them everywhere else. “15 DUIs, still driving: California’s failure to take repeat drunk drivers off the road“ by Robert Lewis and Lauren Hepler in CalMatters CalMatters does terrific reporting in California, something the Golden State desperately needs more of, and this article is a great example of that. “PugLips: The next insanely popular thing you’ve never heard of…” by Simon Carless in Game Discover Co I thought that this parody article (and yes, it’s a parody, but I was definitely unsure at first) was hilarious and totally nailed how much tech/business journalism feels these days. Actually, three of my favorite articles this year were on hype in the video game industry, including Georg Zoller’s “The Video Game Industries Very Dark Night”—which I linked to recently and wrote a follow-up here—and Owen Mahoney’s “Derek Zoolander, Videogame Exec”. In particular, I like Mahoney’s focus on user experience as a guide to what trends will actually grab hold of customers. “The Matrix Lies“ by Evan Shapiro in Media War & Peace Evan Shapiro’s first person account of his experience with AI was hilarious. I think LLMs capabilities have significantly grown from last summer, and yet...my editor/researcher just had an abysmal experience using an LLM to do a quite basic task (which our LLM normally does each week) and the LLM made a mistake on every single data entry...along with seven different mistakes affecting twelve of the twenty or so entries, including mistakes that are explicitly spelled out in the prompt. That’s a brutal failure rate. Again, if you use AI/LLM for data collection, you need to take a lot of extra steps to verify and check the data. “Ghosts in the Balcony: A Cross-Country Trip to 58 Theaters Fighting to Survive“ by Matthew Frank in The Ankler I thought Matthew Frank’s pitch to head across America to visit theaters sounded insane aggressive at the time—at least it felt that way to someone a decade older than him; man, to be in your twenties again, am I right?—but I knew the result would be great. And it was, a terrific feature by a great young writer. Also, I loved Matthew’s recent article on who’s getting the precious few entry level jobs in Hollywood. (Hint: nepotism.) “Disney erased FiveThirtyEight“ and “Did Las Vegas get too greedy?” by Nate Silver in Silver Bulletin I love media history and analysis, and there’s no one better to get the history of FiveThirtyEight than from Nate Silver, who wrote about his personal experience in one of my favorite pieces from this year. I also loved Nate’s breakdown of what’s causing Vegas’ woes, but I’ll offer one criticism, summarized as “Might I suggest antitrust?” Many centrists/center-right/libertarian thinkers (Nate is self-described as the latter) often don’t consider consolidation or antitrust as factors in policy issues like housing, America’s military readiness, or, in this case, Las Vegas. Even if libertarians want to debunk antitrust/consolidation concerns, I’d love to read that debunking. In this case, Vegas is incredibly consolidated (though it also has been for a long time) and I’d have loved to read Nate at least contending with this factor, since he addresses almost every other potential factor for Vegas’ decline. “Why Microsoft’s Carbon Removal Pullback Is Such a Big Deal“ by Robinson Meyer in Heatmap News I’m a big supporter of carbon removal efforts, but this nascent industry faces a lot of headwinds, including this big move most recently. I think it’s clear that solar panels and batteries should be able to get the world to its carbon footprint goals, but effective carbon renewal remains necessary to prevent the worst impacts of global warming. “AI is killing the cheap smartphone“ by David Oks LLMs and AI will impact the world in ways we’re not ready for, and already, third world countries are seeing the prices of cheap cellphones skyrocket due to the cost of chips skyrocketing. This article by David Oks is a terrific breakdown. “100 Days of Madness: Netflix, Paramount, Warner and the Future of Hollywood“ by Wade Major at Hollywood Heretic Wade Major dove deep into Hollywood/streaming’s financials in this must read piece. Not that I agree with everything in this article (read my take on Warner Bros./Paramount here) but the analysis is top notch. I think many people discount how quality thinking, regardless of the argument/conclusion, will make you a better thinker. “Erased by the UFC: Frank Shamrock, The MMA GOAT of the 20th Century“ by Nate Wilcox in The MMA Draw Newsletter Growing up playing the UFC fighting game on the Dreamcast, Frank Shamrock was my favorite MMA fighter, and this history/tribute to him was great. Other Fun Reads “The Hardest Part Of History To Tell Is How It Felt“ by Craig Fehrman at Defector “Unmasking the Sea Star Killer“ by Craig Welch at bioGraphic “What Could Save the Industry? Fin-Syn“ by Richard Rushfield in The Ankler Alex Rollins Berg in Underexposed on movie bumpers, pillow shots, Disney trash cinema, cult films, and Casablanca. David H. Montgomery in YouGov’s The Surveyor on punctuation marks, condiments, dinosaurs, and comic strips and kids media. “How Medium finally pivoted its way to profitability“ and “Why the best journalists on YouTube are all former Vox employees“ by Simon Owens in Simon Owens’s Media Newsletter “It’s Not Just You, Netflix Shows Have Gotten Slightly Shorter: Here’s What the Data Says“ by Kasey Moore at What’s on Netflix “Numlock Awards: How Diane Warren became the biggest loser in Oscar history“ by Nathaniel Rakich and “Numlock Awards: The Oscar Bait era is over. The Oscar Chum era is here.” by Walt Hickey & Michael Domanico at Numlock Awards
Health Sector Bulletin June 2026 Special Edition SHF Standard Allocation
in English on Syrian Arab Republic; published on 1 Jul 2026 by Health Cluster
Annex Health Sector Bulletin June 2026
in English on Syrian Arab Republic; published on 1 Jul 2026 by Health Cluster
Wa-Hi junior Lars Sandven selected for prestigious national science camp
The residential summer camp provides academic and leadership experience in STEAM fields.